Abstract: The present invention comprises methods and circuits for spread spectrum frequency modulation that reduce peak spectral noise at the outputs or inputs of switching regulators. More specifically, the present invention modulates the operating frequency of the switching regulator in accordance with a frequency modulation waveform having a shape coordinated to a peak noise amplitude waveform that describes the correlation between the operating frequency of a switching regulator and the peak noise amplitude at the regulator's input or output absent spread spectrum frequency modulation.

Abstract: A digital frequency jittering circuit for varying a switching frequency of a power supply is disclosed. The digital frequency jittering circuit includes a random data generator, an analog to digital functional module, and a digital to analog functional module. The random data generator has an oscillator for generating an oscillating signal having the switching frequency; a delay module for delaying the oscillating signal by first and second delay amounts to generate first and second delayed signals, wherein the first delay amount is not equal to the second delay amount; and a phase error detecting module for detecting an phase error between the first and the second delayed signals to generate a random data. The analog to digital functional module converts the random data into a digital random value. The digital to analog functional module varies the switching frequency of the oscillating signal according to the digital random value.

Abstract: A digital frequency jittering circuit for varying a switching frequency of a power supply is disclosed. The digital frequency jittering circuit includes a random data generator, an analog to digital functional module, and a digital to analog functional module. The random data generator has an oscillator for generating an oscillating signal having the switching frequency; a delay module for delaying the oscillating signal by first and second delay amounts to generate first and second delayed signals, wherein the first delay amount is not equal to the second delay amount; and a phase error detecting module for detecting an phase error between the first and the second delayed signals to generate a random data. The analog to digital functional module converts the random data into a digital random value. The digital to analog functional module varies the switching frequency of the oscillating signal according to the digital random value.

Abstract: Provided is a low power random bit generator utilizing a multiplying digital to analog converter (MDAC) which is used in a switched capacitor amplifying circuit and an analog to digital converter with a pipeline architecture. The low power random bit generator includes: an MDAC, outputting a predetermined analog voltage formed by using a ground voltage, a reference voltage, an initial voltage and a digital signal; a comparator, outputting a direct current (DC) voltage determined by comparing the analog voltage with the ground voltage; and a data storage unit, storing a predetermined digital signal corresponding to the DC voltage, and outputting the digital signal.

Abstract: A phase locked loop circuit (PLL) has a reference terminal for receiving a reference signal and an output terminal for providing an output signal.

Abstract: A clock signal generator varies a frequency of a digital clock over a selected range of frequencies. The generator employs a divider for lowering a frequency of a clock signal. A counter increments synchronously with the signal, and causes a selected sequence of outputs to be generated by a pattern generator. The pattern generator output forms an input to a digitally controllable delay line which receives the lower frequency clock signal. The pattern generator causes the digital delay line to vary a frequency of the lowered frequency clock signal between selected boundaries. The varying frequency clock signal is then raised up again such that a final clock has a varying frequency, and will exhibit less EMI spiking during switching of an associated, synchronous digital data device. The solid state nature of the generator allows for simple fabrication, inexpensive manufacture and ready integration into digital circuitry, such as multifunction integrated circuits.

Abstract: A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in columns and rows. Each oscillator in a column is unique from the other oscillators in the column based on number of stages in the oscillator and fanout so that each oscillator will operate at a unique frequency. Oscillators of different columns within the array may differ by a common setting of the selects to these oscillators and the physical ordering of the oscillators in the column to further reduce the possibility of injection locking. A base delay cell provides selects to each column of oscillators such that each column may be programmed to operate at a different frequency from its neighbors.

Abstract: A clock signal generator varies a frequency of a digital clock over a selected range of frequencies. The generator employs a divider for lowering a frequency of a clock signal. A counter increments synchronously with the signal, and causes a selected sequence of outputs to be generated by a pattern generator. The pattern generator output forms an input to a digitally controllable delay line which receives the lower frequency clock signal. The pattern generator causes the digital delay line to vary a frequency of the lowered frequency clock signal between selected boundaries. The varying frequency clock signal is then raised up again such that a final clock has a varying frequency, and will exhibit less EMI spiking during switching of an associated, synchronous digital data device. The solid state nature of the generator allows for simple fabrication, inexpensive manufacture and ready integration into digital circuitry, such as multifunction integrated circuits.

Abstract: An apparatus for providing a jittered clock signal has a reverse-biased diode. The reversed-biased diode has a leakage current which decreases a reverse voltage on the diode, time-dependent on a shot-noise of the leakage current. The apparatus for providing a jittered clock signal further has a unit for periodically increasing the reverse voltage of the diode to a value, which is above a switching value and the apparatus has a unit for comparing the reverse voltage of the diode to the switching value and for outputting a jittered clock signal dependent on the comparison.

Abstract: A tamper detection circuit for an integrated circuit includes a pseudo-random generator. A first line is connected to the output of the generator and a second line is connected in parallel via an inverter. A number of XOR gates are coupled to the first and second lines at locations along their length. Output from the XOR gates enables various general operational circuits of the integrated circuit. In the event of one of the lines being cut or otherwise tampered with then the output from the XOR gates will indicate a tamper state. The general operational circuits respond by either resetting or deleting critical data from memory such as the integrated circuit's authentication key. In a preferred version a number of trigger transistors connected to ground are inserted into the paths of the first line and the second line. A physical attack upon the integrated circuit causes a nearby trigger transistor to pull its attached line to ground thereby causing the output of local XOR gates to indicate a tamper state.

Abstract: A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchronized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output clock signal during concurrence periods. The digital clock manager includes a delay lock loop and a digital frequency synthesizer. The delay lock loop generates a synchronizing clock signal that is provided to the digital frequency synthesizer. The output clock signal lags the synchronizing clock signal by a DLL output delay. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay. By matching the DLL output delay to the DFS output delay, the digital clock manager synchronizes the output clock signal and the frequency adjusted clock signal.

Abstract: Circuit for generating a spread spectrum clock (CGSSC) that employs a mechanism to modulate the input voltage (V_ctrl) to the VCO to achieve dithering. The CGSSC includes a voltage controller oscillator (VCO) that generates an output signal (F_out). The VCO includes an input coupled to a voltage control node for receiving a voltage signal and an output for generating a clock signal that has a frequency dependent on the received voltage signal. A VCO input voltage modulation mechanism (VIVMM) is coupled to the voltage control node (V_ctrl) for modulating or adjusting the voltage at the VCO input voltage node in a controlled manner to generate a spread spectrum clock.

Abstract: In the key installation system for improving the confidentiality and concealment of the key, a first decrypting circuit decrypts an encrypted key EKEY1(EDK(MK1)) using an encrypted key EDK1(MK1) as the key. A second decrypting circuit decrypts an encrypted key EMK1(KEY1) using the output of the second decrypting circuit, that is, an internal key KEY1 as the key. A third decrypting circuit decrypts the encrypted key EDK1(MK1) using the output of the second decrypting circuit, that is, an internal key MK1 as the key, to generate a final secret key DK1.

Abstract: A white noise generator comprising a MOSFET operated in its linear region and having zero source-drain DC bias current. This is achieved by connecting the source or drain terminal of the MOSFET to a gate terminal of a MOSFET amplifier that may be implemented as a multi-stage differential amplifier. Such a noise source avoids the effect of DC current responsible for generating 1/f noise and has a small physical size that results in low parasitic capacitance of the device itself.

Abstract: A voltage-controlled oscillator comprising a LC tank circuit coupled to a pair of transistors and crossed-coupled to a pair of emitter follower transistors each transistor having a collector, an emitter and a base, the voltage controlled oscillator being characterized in that a supply voltage applied to the collectors of the emitter follower transistors is substantially different from a supply voltage applied to the bases of the emitter follower transistors.

Abstract: A PLL circuit is described. The PLL circuit includes: a signal generator; and a spread spectrum modulator coupled to the signal generator, where the spread spectrum modulator receives a control voltage as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage. In one embodiment, the spread spectrum modulator includes at least one selector, where the at least one selector selects a plurality of voltage levels that correspond to a spread mode and percentage of spread for the spread spectrum modulator.

Abstract: A method for generating random numbers includes the steps of providing a liquid crystal cell containing a liquid crystal material, wherein a potential difference is applied across said liquid crystal material to cause a chaotic turbulent flow. The resulting flow or physical result of the liquid crystal material is measured to generate a baseline measurement, and subsequently the at least one physical property is measured again to generate a plurality of reading measurements. Determining the difference between each of the reading measurements and the baseline measurement, and setting bits based on the differences generates a sequence of random numbers. An apparatus for generating random numbers is also disclosed. These truly random numbers may then be used to encrypt data prior to transmission.

Abstract: A noise generator for generating multi-octave, high-level, millimeter- and submillimeter-wave noise is disclosed. According to one embodiment of the invention, the noise generator includes: a microwave noise source; a microwave power-amplifier chain; a level-set attenuator; a frequency multiplier; and a transmission structure. The output of the generator has a high-intensity noise power spectrum over a frequency range from about 60 GHz to about 1 THz. This type of noise is particularly suited and has sufficient power for testing and calibrating millimeter- and submillimeter-wave components, devices, and circuits; material evaluation and characterization; and for use as a broadband millimeter- and submillimeter-wave noise source for a Fourier Transform Spectrometer.

Abstract: An electrical circuit generates an oscillating signal that produces reduced electromagnetic interference by way of modulation of the frequency of the oscillating signal within a specified frequency range. A randomized signal generator creates a randomized signal, which is then used to drive a frequency range converter that is employed to produce a frequency modulation signal. The current state of the frequency modulation signal is based on the current state of the randomized signal, with the converter limiting the current state of the frequency modulation signal so that the oscillating signal will only operate within the specified frequency range. A variable frequency oscillator then generates the oscillating signal whose frequency is based on the current state of the frequency modulation signal.

Abstract: A PLL circuit is described. The PLL circuit includes: a signal generator; and a spread spectrum modulator coupled to the signal generator, where the spread spectrum modulator receives a control voltage as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage. In one embodiment, the spread spectrum modulator includes at least one selector, where the at least one selector selects a plurality of voltage levels that correspond to a spread mode and percentage of spread for the spread spectrum modulator.

Abstract: A clock signal generating device is described, having an oscillator and a PLL connected downstream thereof. The clock signal generating device is distinguished by the fact that a phase shifting device is provided between the oscillator and the PLL. This phase shifting device can temporally shift the edges of the signal output by the oscillator to a variable extent, and feeds the resultant signal to the PLL as an input signal. Such a clock signal generating device makes it possible to realize a spread spectrum oscillator which is constructed in a simple manner and can be made small.

Abstract: A digitally controlled angle noise signal generator for generating a signal with precise and accurate noise. The signal generator is formed of a digital noise generator for generating a digital noise signal &thgr;N, and a digital signal generator for forming an internal signal S. The digital signal generator receives the digital noise signal &phgr;N and modulates the internal signal S with the digital noise signal &phgr;N to generate a digitally controlled signal yg=S{&thgr;N}, where is the modulation operator, with precise and accurate noise.

Abstract: A method of producing a clock signal with reduced electromagnetic interference spectral components includes providing a first clock signal; producing a second clock signal by delaying the first clock signal; and generating a jittered clock signal by switching between the first clock signal and the second clock signal at times selected responsive to a random number generator.

Abstract: A pulse generator. The pulse generator has a pseudo random number generator, a comparator coupled to the pseudo random number generator, and a register coupled comparator. The comparator performs comparisons of values generated by the pseudo random number generator and a value in the register, wherein the comparator outputs a pulse that is modulated according to the comparison. A low-pass filter may coupled to the comparator output and the register may receive samples of a digital signal. Low-pass filtering the comparator output implements a digital-to-analog converter that is less expensive than conventional delta-sigma modulator DACs and has better performance than conventional PWM DACs.

Abstract: A spreading code generator generates a spreading code specified by a matrix order and row number, which are matrix elements.

Abstract: A frequency variation apparatus is provided for use in a hardware-based random number generator. The frequency variation apparatus includes sampling frequency variation logic and a sampling frequency oscillator. The sampling frequency variation logic produces a noise signal that corresponds to parity of two independent and asynchronous oscillatory signals. The sampling frequency oscillator is coupled to the sampling frequency variation logic. The sampling frequency oscillator receives the noise signal, and varies a sampling frequency within the random number generator in accordance with the noise signal.

Abstract: A random number generator on an integrated circuit has a first clock generator circuit with a first voltage supply for generating a first signal of a first frequency or of a first frequency range. A second clock generator circuit has a second voltage supply for generating a second signal of a second frequency or of a second frequency range, such that the second frequency or a mean value of the second frequency range is lower than the first frequency. A generator samples the first signal with the second signal and-generates at least one random number in dependence on the result of the sampling. The clock generator circuits are located as far away from one another as possible on the integrated circuit and/or the two voltage supplies are isolated from one another and/or at least one guard ring is placed around each of the clock generator circuits.

Abstract: An oscillator 10 with a noise reduction function has a memory 80 that memorizes modulation data DM for performing the spread spectrum modulation input from an output terminal fout, a modulation signal output circuit 60 that generates a modulation signal SM from the modulation data DM memorized in the memory 80, and a mixer 53 that overlays the modulation signal SM on the control voltage VC of a voltage control oscillator (VCO) 54 of a PLL circuit 50, and it becomes possible to output a spread spectrum modulated output signal CLv under a specification desired by a user by memorizing in the memory 80 the modulation data DM that corresponds to the spread spectrum modulation the user tries to set.

Abstract: A signal generator and signal receiver, as well as method of signal generation and transmission, in which selected unstable periodic orbits of a lossy chaotic system are identified and extracted, and portions of the orbits concatenated together to form a resultant signal. The selected orbits are known to the signal detector a priori. The signal detector detects the transmitted signal by correlation of the received signal with the known extracted orbits, also allowing the detector identify information which the generator imposed onto the signal.

Abstract: A frequency synthesizer, a multi-channel carrier generator, and a transceiver, as well as a method for generating a sub-carrier frequency are described. The frequency synthesizer includes two directly-connected, sequential chains of flip-flops, the first chain having N flip-flops, and the second chain having M flip-flops. The first chain of N flip-flops is clocked by a reference frequency input. Each chain provides a clocked output to an optional duty-cycle recovery circuit, which is in turn coupled to a frequency-update module. There is a sub-threshold low-pass filter included in the frequency-update module which feeds into an oscillator, providing, in turn, the generated frequency as an input to the second chain of M flip-flops, and a sub-carrier frequency output.

Abstract: A technique of time dithering a fully digitally-controlled oscillator (DCO) tuning input employs a shift register 1306 and a multiplexer 1308 responsive to a sigma-delta modulated delay control to minimize spurious tones generated by a DCO 200. The shift register 1306 is clocked via a divided-down high-frequency reference provided by the DCO 200 output signal. The multiplexer 1308 is clocked via a frequency reference that is reclocked and synchronized to the DCO 200 output signal. The multiplexer 1308 output is thus time dithered in response to a delay control to minimize perturbations caused by switching.

Abstract: A circuit includes a first voltage-controlled oscillator (VCO) that generates a feedback clock. The circuit further includes a phase frequency detector, a charge pump and a loop filter that together receive a reference clock and the feedback clock, and in response thereto, generates a first voltage signal. The circuit further includes a timing generator that generates a control signal having varying periods, and a voltage modulator that receives the first voltage signal and the control signal, and in response thereto, generates a second voltage signal and a third voltage signal. The second voltage signal is provided to the first VCO. The circuit also includes a second VCO that receives the third voltage signal and which outputs a spread spectrum clock.

Abstract: A frequency variation apparatus is provided for use in a hardware-based random number generator. The frequency variation apparatus includes sampling frequency variation logic and a sampling frequency oscillator. The sampling frequency variation logic produces a noise signal that corresponds to parity of two independent and asynchronous oscillatory signals. The sampling frequency oscillator is coupled to the sampling frequency variation logic. The sampling frequency oscillator receives the noise signal, and varies a sampling frequency within the random number generator in accordance with the noise signal.

Abstract: A random signal generator (1) has at least two functional groups (2a, 2b, 2c) each of them having one random sequence generators (3a, 3b, 3c), one exclusive-or gate (4a, 4b, 4c) and one memory element (5a, 5b, 5c). One of the two inputs (6a, 6b, 6c) of the exclusive-or gate (4a, 4b, 4c) of each functional group (2a, 2b, 2c) is connected to a random sequence signal output (7a, 7b, 7c) of the random sequence generator (3a, 3b, 3c) of the functional group (2a, 2b, 2c) and the other input (8a, 8b, 8c) to a data output (9a, 9b, 9c) of the memory element (5a, 5b, 5c) of the functional group (2a, 2b, 2c). The output (10a, 10b, 10c) of the exclusive-or gate (4a, 4b, 4c) of each functional group (2a, 2b, 2c) is connected to the data input (11a, 11b, 11c) of the memory element (5a, 5b, 4c) of the functional group (2a, 2b, 2c). The memory elements (5a, 5b, 5c) of the functional groups (2a, 2b, 2c) are connected to one another via data lines (13) for the purpose of shifting their memory contents.

Abstract: In a noise sequence generator, a plurality of memories store plural types of noise sequences that are non-correlated with each other, respectively. A noise sequence readout section reads out the noise sequences stored in the plurality of memories so that the code periods are prime numbers of each other. A sequence-adding section adds the noise sequences read out in parallel from the plurality of memories by means of the noise sequence readout section, thereby outputting the addition result as a series of noise sequences. In a CN controller, a setting section sets a value to determine an amplitude of a digital modulation signal row to a register. A multiplying section multiplies the setting value of the register by the to-be-inputted digital modulation signal row. A CN adding section adds a series of noise sequences outputted from the sequence adding section of the noise sequence generator to an output of the multiplying section, and outputs the addition result.

Abstract: A low noise clock oscillator in standard surface mount plastic or ceramic form. With the same soldering pads design such devices can be replace with a convention standard surface mount clock oscillator to reduce Electro-magnetic Interference or RFI (Radio Frequency Interference) without redesign of the main board. The oscillator is characterized by using a spectrum spread clock generator and a spread controller on an elevated platform to reduce common mode emission currents.

Abstract: In the particular embodiments of the invention described in the specification, a first signal generator produces a signal which changes in cycles having approximately straight line segments between maximum and minimum values at a first rate and a second signal generator produces a signal which changes in cycles having approximately straight line segments at a second rate which is an order of magnitude greater than the first rate. The maximum level of the second signal during any cycle is dependent upon the instantaneous signal level of the first signal and the minimum level of the second signal during any cycle is dependent upon a selected fraction of the instantaneous signal level of the first signal. The second signal is used to control the speed of a motor in a continuously changing random manner.

Abstract: A high-frequency crystal oscillator capable of outputting a signal at a frequency, for example, higher than 500 MHz without using a multiplication amplifier. The high-frequency crystal oscillator comprises a voltage controlled Colpitts oscillation circuit operating at the fundamental frequency of a quartz-crystal element, means for increasing the level of harmonic component in an output from the Colpitts oscillation circuit, an SAW (Surface Acoustic Wave) filter for selecting a component of a predetermined order of the harmonic component, and a broadband amplifier for amplifying the component selected by the SAW filter. The means for increasing the levels of harmonic component is, for example, a resistor for setting the operating point of a transistor in the oscillation circuit such that an output signal is distorted.

Abstract: A random number generator has a simple configuration using know inexpensive electronic parts and can generate the true physical random numbers at a required generation speed. Such a random number generator can provide the true physical random numbers to any sectors of society at dramatically low cost A random pulse generator comprises a thermal noise generating element (2) having a resistor, a conductor or a semiconductor such as a diode adapted to generate thermal noises Hen no electric current is supplied to them, an analog-amplifier circuit for amplifying the irregular potential generated from the thermal noise generating element and a waveform shaping circuit (6) adapted to take out the output of the amplifier circuit as random rectangular pulse signals.

Abstract: Random pulse generators and generating systems using at least three oscillators. The output signals of at least two of the oscillators are combined to disturb the output signal of a final oscillator. For one configuration, combined output signals of at least two phase shift oscillators are used to modify the feedback signal of a final phase shift oscillator, thus disturbing the output signal of the final oscillator. For another configuration, the output signals of at least two phase shift oscillators are used to drive a subtractor whose output signal is combined with the output signal of a final phase shift oscillator to drive a subsequent subtractor, thus disturbing the output signal of the final oscillator.

Abstract: The present invention is an apparatus and a method for generation of random numbers. The apparatus comprises an alpha-radiation source, such as Am 241, for which the decay product produces no secondary radiation with the energy equal or higher than that of the prime alpha radiation. The alpha particles emitted by the isotope and having reached the detector have a narrow energy spectrum and, hence, produce identical electrical pulses in a detector. An alpha-particle detection system is provided which includes a differential discriminator in combination with a logical selector. This combination of elements allows a positive identification of individual events of alpha-decay in the alpha-radiation source to be made and filters out any other signals produced by different radiation sources both inside and outside the apparatus. An electronic unit processes the stream of identical electric pulses into a stream of random numbers.

Abstract: A circuit and method for generating a variable frequency clock signal that uses a first, lower frequency oscillator, to modulate and vary the frequency of a second, higher frequency oscillator to generate a variable frequency clock signal. The circuit includes a first oscillator, a control circuit, and a second oscillator. The first oscillator generates a first signal having a substantially fixed-frequency magnitude. The control circuit is coupled to receive the first signal from the first oscillator and outputs control signals based on the received first signal. The second oscillator is coupled to receive the control signals from the control circuit and generates the variable frequency magnitude clock signal in response to the received control signal.

Abstract: A random number generator on an integrated circuit has a first clock generator circuit with a first voltage supply for generating a first signal of a first frequency or of a first frequency range. A second clock generator circuit has a second voltage supply for generating a second signal of a second frequency or of a second frequency range, such that the second frequency or a mean value of the second frequency range is lower than the first frequency. A generator samples the first signal with the second signal and-generates at least one random number in dependence on the result of the sampling. The clock generator circuits are located as far away from one another as possible on the integrated circuit and/or the two voltage supplies are isolated from one another and/or at least one guard ring is placed around each of the clock generator circuits.

Abstract: In the particular embodiments of the invention described in the specification, a first signal generator produces a signal which changes in cycles having approximately straight line segments between maximum and minimum values at a first rate and a second signal generator produces a signal which changes in cycles having approximately straight line segments at a second rate which is an order of magnitude greater than the first rate. The maximum level of the second signal during any cycle is dependent upon the instantaneous signal level of the first signal and the minimum level of the second signal during any cycle is dependent upon a selected fraction of the instantaneous signal level of the first signal. The second signal is used to control the speed of a motor in a continuously changing random manner.

Abstract: An improved random number generator for micro-controllers is provided with multiple free running oscillators. These oscillators may be ring oscillators. They run at different frequencies. A phase difference between at least two of the oscillators provides the random number. The determination of a phase difference can be done by sampling the high speed oscillator using the lower speed oscillator. This sampling of the oscillators for the determination of a phase difference can be controlled by an oscillators as well. The random number is picked up from a shift register which provides feedback to a control circuit which can alter the frequency of one or more (including all) of the oscillators so that an increased randomness can be achieved. The random number from the shift register is loaded into a linear feedback shift register (LFSR) to generate independent uniform random data.

Abstract: A random number generator generates high quality random numbers by sampling the output of a voltage controlled oscillator (VCO) at a frequency much lower than the frequency of the oscillator output. The output frequency of the oscillator is changed significantly during each sampling interval to help ensure the phase relationship of the VCO output and the sampling frequency is unpredictable. That may be accomplished by logically combing the sampling clock and an output from a linear feedback shift register in an exclusive OR gate and supplying that output as the most significant bit used to generate the voltage to control the oscillator. Additional outputs from the linear feedback shift register are also used to generate the control input to the VCO. A distilling circuit such as a CRC circuit or a linear feedback shift register shifts in successive output samples and generates a number therefrom to further increase the randomness of the generated random number.

Abstract: A circuit includes a first voltage-controlled oscillator (VCO) that generates a feedback clock. The circuit further includes a phase frequency detector, a charge pump and a loop filter that together receive a reference clock and the feedback clock, and in response thereto, generates a first voltage signal. The circuit further includes a timing generator that generates a control signal having varying periods, and a voltage modulator that receives the first voltage signal and the control signal, and in response thereto, generates a second voltage signal and a third voltage signal. The second voltage signal is provided to the first VCO. The circuit also includes a second VCO that receives the third voltage signal and which outputs a spread spectrum clock.

Abstract: A circuit and method for generating a variable frequency clock signal that uses a first, lower frequency oscillator, to modulate and vary the frequency of a second, higher frequency oscillator to generate a variable frequency clock signal. The circuit includes a first oscillator, a control circuit, and a second oscillator. The first oscillator generates a first signal having a substantially fixed-frequency magnitude. The control circuit is coupled to receive the first signal from the first oscillator and outputs control signals based on the received first signal. The second oscillator is coupled to receive the control signals from the control circuit and generates the variable frequency magnitude clock signal in response to the received control signal.

Abstract: An apparatus is described comprising a noise source coupled to an input of a gain stage. The apparatus also includes a noise shaping stage that forms a shaped noise signal by reducing 1/f noise introduced by the gain stage. The noise shaping stage has an input coupled to an output of the gain stage. The apparatus also has a decision circuit that decides whether the shaped noise signal, or a signal derived from the shaped noise signal corresponds to a 1 or a 0. A method is described that amplifies a first noise signal to produce a second noise signal. A shaped noise signal is formed by reducing 1/f noise introduced to the second noise signal by the amplifying. A random sequence is generated by comparing, against a reference, the shaped noise signal or a signal derived from the shaped noise signal.

Abstract: The present invention offers a method and a circuit for generating codes enabling transmission of long-codes to start on a reverse channel in a shorter waiting time. The method involves corresponding a shift quantity between the beginning of a sequence M or long-codes cycle, and each timing to a combination of a plurality of masking data; determining a combination of masking data for timing to start generation of long-codes in response to a transmission request at a point of time as soon as possible; and shifting of an initial value of a vector according to the masking data.