Abstract: An improved clock generation circuit is provided that operates with a single input clock frequency, and includes a Phase Locked Loop circuit (PLL) with a digital accumulator in the feedback loop, in which either the Most Significant Bit or the Carry Bit of the binary adder is used as the modulated feedback clock to the phase/frequency detector of the PLL. In one embodiment, a fixed add/phase amount is used to drive one of the inputs of the binary adder to generate a fixed output frequency. If it is desired to modulate the output frequency, then an Add Amount Modulator circuit can be provided that presents a varying numeric value to one of the inputs of the binary adder. The MSB or Carry Bit is communicated to an address look-up table, which then outputs an address to a memory circuit, which in turn presents a different add amount to the binary adder.

Abstract: A circuit includes a first oscillator having transistors to produce a first signal with random variations resulting from device channel resistance of the transistors.

Abstract: A flexible data rate matching method and apparatus by symbol repetition in a data communication system. To generate a sequence of N symbols from a sequence of L code symbols less than the N symbols in a system having an encoder for generating the sequence of L code symbols and a channel interleaver for receiving the sequence of N symbols, symbols at generally equidistant (N−L) positions are detected among the L code symbols. The detected symbols are sequentially inserted before or after the detected symbols by repetition.

Abstract: In a random number generating circuit, a resistive element is arranged between a power supply line which supplies a power voltage and one of a plurality of logic gate circuits. An insulating layer is arranged between the resistive element and a conductive line. As a result, a capacitor is formed between the resistive element and the conductive line, and random numbers can be generated as a result of the capacitance of the capacitor.

Abstract: A method, and associated apparatus, for generating a pseudo-random number sequence. Determinations are made of compatible configurations of windmill generators for a selected windmill polynomial. Implementation of a windmill generator is made through use of word-oriented memory elements. Words stored in the memory elements are selectively outputted to form portions of a pseudo-random number sequence.

Abstract: In a frequency synthesizer 1 that has a high spurious component elimination ratio, if the integer frequency division value is changed and a fractional frequency division value is to be generated, rounding circuit 6 rounds the random number generated by random number generation circuit 7. Based on the integer value that is thereby generated, frequency division value control circuit 5 generates an integer frequency division value. Because the integer frequency division value changes based on a random number, there is no regularity, and spurious components are never generated in output signal OUT. Even if compensation circuit 37 generates a compensation current and superimposes it on the output of charge pump circuit 35, the influence of the ripple current output from charge pump circuit 35 cannot be completely eliminated.

Abstract: A system is provided for generating multiple frequencies in a specified frequency band, with a specified step size between frequencies, in which the spectral purity of the frequencies is assured. The switching speed between frequencies is very fast, limited only by the speed of the switches used. In one embodiment, only five tones are generated as the base for the rest of the synthesis, in which the relationship of the five tones is f0+/−⅛f0 and +/−{fraction (1/16)}f0. The subject system in one embodiment, utilizes a channel synthesizer and a doppler offset synthesizer which may be utilized in air defense systems for generating the transmit channels to be able to permit a missile seeker to transmit a signal at the appropriate frequency. In one embodiment, spectral purity is achieved by providing a number of stages of up converting, expanding, and dividing down of an input signal.

Abstract: A method of using a phase lock loop to receive an oscillating input signal and produce an output signal, the phase lock loop comprising a plurality of flip-flops which are chained together, the plurality of flip-flops including a first flip-flop having a first output, including a second flip-flop having an input coupled to the first output and having a second output, and including a third flip-flop having an input coupled to the second output, the phase lock loop further comprising a control node, the method including using the flip-flops to determine time spacing between transitions to perform a frequency comparison of the output signal relative to the input signal; extracting a clock from an input digital signal; and performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator.

Abstract: An amplitude insensitive synchronized nonlinear system (AISN) that allows communication between nonlinear systems operating in the chaotic realm which is insensitive to attenuation or signal noise affecting the amplitude of the drive signal, thereby allowing communication between remote systems where the amplitude of the transmitted signal has been varied by an unknown amount.

Abstract: An apparatus for implementing a game having a deterministic component and a non-deterministic component wherein a player uses the game through at least one player interface unit. Each player interface unit generates a player record indicating player-initiated events. A random number generator provides a series of pseudo-random numbers and a rules library stores indexed rules for one or more games. An interface registry stores mapping records where the mapping records are used to associate the player-initiated events to pre-selected rules in the rules library. A control means is coupled to the player interface to receive the output of the player interface unit, coupled to the interface registry, the rules library, and the random number generator.

Abstract: This invention relates to an electrical device for generating a multi-rate pseudo random noise (PN) sequence comprising sequence generation means adapted to output a plurality of sequence values on the basis of a step control signal (St), said device further comprising selection means adapted to select one of said plurality of sequence values on the basis of a select value (Mt), and step control means adapted to provide said step control signal (St).

Abstract: A system and method of providing featureless covert communication is described. After synchronization is achieved between a covert transmitter and a covert receiver using two channels, one of which is a transmitted reference signal, a single channel is used to transmit the bulk of the communication message. The featureless covert communication system uses a digitally controlled noise source (capable of reproducing a pre-selected pseudo-random signal indistinguishable from ambient noise) at both transmitter and receiver. The digitally controlled noise source produces an uncorrupted reference signal at both locations. Since only once channel is used to transmit the message, 3 dB in power is saved. And, since the same reference signal is being generated locally at the receiver, corruption of the reference signal is eliminated, which improves the efficiency of the system by at least another 10 dB.

Abstract: A circuit is designed with a plurality of logic circuits (370-374) for producing an offset state matrix. The circuit includes a first logic circuit (380-383) coupled to receive N elements of a respective row of a transition matrix and N elements of column of an input state matrix. The first logic circuit produces a multi-bit logical combination of corresponding bits of the respective row and the column. A second logic circuit (390) is coupled to receive the multi-bit logical combination and produces a respective element of the offset state matrix.

Abstract: A pseudorandom sequence generator including a first feedback shift register having at least one input and at least one output and a first controller having an output in communication with the at least one input of the first feedback shift register; the first feedback shift register operating at a first speed S1 and the first controller operating at a second speed S2. In one embodiment the first speed S1 of the first feedback shift register is an integer multiple of the second speed S2 of the first controller. In another embodiment the first feedback shift register includes a shift register having an input, an output, and at least one tap; and a feedback function generator having a first input in communication with the at least one tap of the shift register, a second input in communication with the output of the first controller, and an output in communication with the input of the shift register; the feedback function generator includes at least one feedback function.

Abstract: An apparatus having a white noise source which is coupled to a gain stage having an amplifier. The gain stage is coupled to a noise shaping stage which is also coupled to a decision circuit. Another apparatus having a white noise source which is differentially coupled to a gain stage that has a cascade of open loop amplifiers. The gain stage is differentially coupled to a noise shaping stage which is also differentially coupled to a decision circuit. A method that involves differentially coupling white noise into a gain stage. The white noise is differentially amplified with an amplifier which produces a first white noise signal. 1/f noise and offset voltage is substantially removed from said first white noise signal to produce a second white noise signal. A random sequence signal is produced by deciding whether the second white noise signal is a 1 or 0.

Abstract: The present invention provides a phase-locked loop having a multi-phase voltage controlled oscillator. The phase-locked loop comprises a divided-by-N counter, a divided-by-M counter, a phase frequency detector, a charge pump, a loop filter, a multi-phase voltage controlled oscillator, a switching unit, and a clock counter. It utilizes a multi-phase voltage controlled oscillator instead of a conventional voltage controlled oscillator and a switching unit is used to select the output signal from the multi-phase voltage controlled oscillator. The switching time of the switching unit is controlled by the clock counter to achieve the effect of frequency expansion.

Abstract: A novel and improved method and apparatus for a fast-slewing pseudorandom noise sequence generator is described. One or more loadable PN generators are controlled by a DSP or microprocessor in conjunction with a free-running counter which maintains a reference offset count. The PN generator will typically be part of a finger or searcher. The DSP or microprocessor may assist in other finger or searcher functions as well as the slew function, and can control one or more fingers and/or searchers. Each PN generator is comprised of a loadable linear feedback shift register (LFSR) or its equivalent, a loadable counter for maintaining an index of the state of that particular PN generator, and a slew control device capable of receiving a slew command and controlling the LFSR and index counter to enact an advance or a retard of a certain offset distance.

Abstract: An improved chopper stabilized operational amplifier is disclosed, along with an improved method of timing the switchings of chopper switches in such an amplifier. The disclosure includes an integrated circuit and method for generating a true random voltage signal having a truly random RMS voltage value within a selected range. The true random voltage signal is obtained by amplifying and bandpass filtering random white noise voltages generated by a component of the circuit. The white noise voltages include shot noise voltages generated by bipolar transistors in an input amplifier stage. The random signal generator circuit and method is employed with an oscillator to form a random clock signal generator on the integrated circuit chip. The amount of time between each clocking pulse output by the random clock signal generator truly randomly varies within a selected range of time, and repeats only by random chance.

Abstract: A vector generator generates one or more pseudo-random noise PN sequences as matched-filter PN vectors for a matched-filter correlator of a code division, multiple-access (CDMA) demodulator. The period and clock of the local PN code sequence may be employed as a time reference, and each matched-filter PN vector has a known code-phase offset with respect to the local PN code sequence. Matched-filter PN vectors having a chip-length on the order of a data symbol period, such as 64-chip sequences, are generated within a short period of time compared to the period of the local PN code sequence. A state of the local PN code sequence is periodically captured from the local PN code sequence, which state is employed by a PN generator generating a similar PN code sequence but clocked at a higher rate. Consequently, a series of offset PN code sequences are generated in advance of the local PN code sequence.

Abstract: A high frequency anharmonic oscillator provides a broad band chaotic oscillation with a noise-like spectra. The oscillator output signal is suitable for modulation by data providing for improved secure communication. The chaotic oscillator is based upon a forced second order Duffing equation that is tolerant of delay in the feedback path for high frequency operation.

Abstract: A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit comprising: a voltage controlled oscillator having a control node and an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

Abstract: A pseudo-random noise series generator which can change the timing of generation of a PN series arbitrarily and with no instantaneous cut-off of the output. At the time of system start, the whole period or a certain beginning length of a PN series generated by a tapped shift register is stored into a RAM. The stored PN series is output from a position designated by an address signal. An address generator for generating the address signal on an externally applied timing control signal increments an address by one for each step from an initial value set by the timing control signal. In the case where a new timing different from the old timing is set by the timing control signal, the address is incremented or decremented instantaneously by a difference between the old timing and the new timing and a normal incrementing operation is thereafter started again.

Abstract: A random number generator using, for example, a voltage controlled oscillator (VCO) which receives a noise input and at least one differential oscillator. The differential oscillator(s) provided oscillator signals to a differential sense amplifier which is sampled under control of the VCO.

Abstract: A method and an apparatus for determining an encryption key associated with an integrated circuit having a memory plane that includes a matrix of electric contacts on it's surface and a layer of inhomogeneous electric resistivity material disposed on the matrix. An encryption key is determined by the integrated circuit on the basis of the random distribution of the electrical resistances connecting the various electric contacts of the matrix.

Abstract: A system of spreading the energy of higher harmonic frequencies in digital circuits to lower the interference to bandpass receivers is disclosed. A set of passive, impedance-regulated circuits, preferably housed in a standard enclosure, comprises a power restoring unit, a modulating signal generator, an internal oscillator and an impedance spreading unit. The circuits are equivalent to passive resonators such as crystal resonators used in standard oscillators. Any existing standard oscillator that uses common crystal resonators can be transformed into a spectrum-spread oscillator by replacing the crystal resonator with the disclosed circuit, whereby a tightly controlled small frequency spreading occurs in the fundamental clock frequency. Further an active oscillator is disclosed wherein a spreading circuit spreads the frequency of the clock signal originally generated by the oscillator based on a sequence of processing the original clock signal.

Abstract: A digital standard cell implemented ring oscillator circuit for placement within an integrated circuit device. In one embodiment, the digital standard cell ring oscillator circuit is used in conjunction with a system for generating non-deterministic (e.g., random) output signals which can be used for data encryption. A random number generator circuit is used within the above system and the standard cell ring oscillator of the present invention is used to provide oscillator signals to different frequency legs of the random number generator circuit and can also be used to supply a jitter clock. The timing characteristics (e.g., frequency) of the standard cell ring oscillator vary with its fabrication process, its fabrication environment, and the temperature when used; timing characteristics are therefore unpredictable from "chip" to "chip" and from one point in time to another with respect to the same "chip." This increases the non-deterministic properties of the random number generator.

Abstract: A method and apparatus for the selection of random values from a set of N non-sequential values includes software in ROM and RAM for information pool storage. Coupled to the ROM and RAM, a microprocessor sorts the values from smallest to largest, initializes local variables, processes a current value from a first value of the set, and compares the difference to a current information pool entry difference. A range increment is incremented if the difference equals the current information pool entry difference and a new information pool entry is created if the difference does not. The information pool is stored and random values are selected by generating a pseudo random number, constraining the pseudo random number between one and N, indexing into the information pool using the pseudo random number to create a pool entry index and generating the random value using a selected pool entry first value.

Abstract: Apparatus for providing a reference pseudo-noise ("PN") sequence, and for providing a secondary PN sequence shifted with respect to the reference PN sequence by a number of chips that can be sequentially shifted. The apparatus includes a first pseudo-noise sequence generator ("PNSG"), the PNSG generating the reference PN code, having N stages, each stage being at one of two states, and having a feedback loop from the output of the PNSG, the value on the feedback loop being stored in each stage 1, 2, 3, . . . N, after being multiplied by a constant associated with the stage, C1, C2, C3, . . . CN, respectively, and the result added to the value in the previous stage, with "0" being deemed to be the value in the stage previous to the first stage, and then stored in the stage. Also provided is a mask generator/shifter comprising a second PNSG having N stages, wherein the N stages of the second PNSG may be loaded with a shift-and-add mask, M=m.sub.1, m.sub.2, . . . m.sub.N-1, m.sub.N.

Abstract: An improved chopper stabilized operational amplifier is disclosed, along with an improved method of timing the switchings of chopper switches in such an amplifier. The disclosure includes an integrated circuit and method for generating a true random voltage signal having a truly random RMS voltage value within a selected range. The true random voltage signal is obtained by amplifying and bandpass filtering random white noise voltages generated by a component of the circuit. The white noise voltages include shot noise voltages generated by bipolar transistors in an input amplifier stage. The random signal generator circuit and method is employed with an oscillator to form a random clock signal generator on the integrated circuit chip. The amount of time between each clocking pulse output by the random clock signal generator truly randomly varies within a selected range of time, and repeats only by random chance.

Abstract: The present invention provides an apparatus for generating a differential noise between a power and ground planes in a printed wiring board (PWB). The apparatus comprises a power plane, a ground plane, and a signal transmission circuit. A plurality of cuts comprising a first pattern is formed on the power plane. The ground plane also provides a plurality of cuts comprising a second pattern. Both the power plane and the ground plane are disposed in the PWB. A signal transmission circuit transmits a signal current over the ground plane and the power plane. The signal current induces an image return current on both the power plane and the ground plane. The first and second patterns of cuts on the power plane and the ground plane, respectively, disrupt the image return current and cause a differential voltage noise to be generated between the power plane and the ground plane.

Abstract: A low noise clock oscillator in modular form to plug into a standard 14 or 8 pin DIP clock oscillator socket on the motherboard of a host device to retrofit the host device without redesign of the host device motherboard so that the host device can reduce its EMC emissions sufficiently to pass EMC emission tests. The oscillator is characterized by use of a spread spectrum clock generator, EMC filters between the clock generator and the Vcc, ground and clock bus coupling points to the motherboard and a single point ground connection to the motherboard. This oscillator module allows an easy retrofit to a host device that has already been designed to substantially lower EMC emissions that can be traced to the clock by as much as 20 dB without expensive, time consuming redesign efforts to add shielding, more grounds and possibly reroute the motherboard traces.

Abstract: A method is disclosed whereby a high performance, high integrity, cryptographically secure sequence generator based on zeta one-way functions is specified for pseudorandom sequence generation, authentication, key transfer by public discussion, and message transmission by public-key encryption. The method encompasses a new one-way function with trapdoor based on Artin reciprocity in an algebraic number field. Public keys are pseudorandom sequences based on zeta one-way functions. In the simplest instance of this method, public keys are quadratic signatures, i.e. special sequences of Jacobi symbols. The generation, transfer, and sharing of private keys is a process based on the lax of quadratic reciprocity. The computational complexity of the quadratic signature problem provides the foundation for the cryptographic security of this method. This new trapdoor one-way function is distinct from constructions in the prior art.

Abstract: A signal generator has a variable reference oscillator, a variable oscillator and a phase locked loop for generating an output having jitter and wander. The variable reference oscillator generates a reference having a varying phase offset over a first phase modulation frequency interval and a constant output over a second phase modulation frequency interval. The variable oscillator generates a constant output over the first phase modulation frequency interval and a variable output over the second phase modulation frequency interval. The phase locked loop includes a phase detector, a phase summing node and oscillator with the phase detector coupled to receive the outputs of the variable reference oscillator and the oscillator, and phase summing node coupled to receive the outputs of the variable oscillator and the phase detector.

Abstract: A first pseudo random number generating circuit sequentially provides an output signal to a matching detecting circuit in response to a clock signal. A second pseudo random number generating circuit generates an initial value, and then, sequentially provides an output signal to a storage device in response to an output signal from the matching detecting circuit and the clock signal. Data with the output signal as an address is provided as an output signal from the storage device. When the matching detecting circuit detects matching between the output signals, the matching detecting circuit provides the output signals to the second pseudo random number generating circuit and an AND logic circuit. As described above, when the output signal of the matching detecting circuit is provided, the output signals from the storage device are provided as respective output control signals.

Abstract: A random number generator using a single, slow, voltage controlled oscillator which receives a noise input and a plurality of high frequency ring oscillators. The ring oscillators are sampled under control of the slow oscillator. A circuit is used between the output of each of the ring oscillators and its respective D-type latch to assure that the sampling is unbiased, that is, that there will be near even distribution of 1s and 0s in the random numbers.

Abstract: A high frequency arbitrarily modulated signal and noise generator utilizes digital numerically controlled oscillators providing interbusiness directly to an adder and which are phase modulated. The digital adder feeds a digital analog converter, eliminating the need for a digital multiplier while providing amplitude or phase modulation with high resolution and at high processing speeds.

Abstract: A method and apparatus for generating noise to be used in evaluation and testing of digital or analog integrated circuits. One or more noise generators fabricated on a substrate generate noise representative of the digital switching noise generated by a digital integrated circuit. The noise generator may be programmable to generate noise over a wide frequency and amplitude range. In addition, a plurality of noise generators may be used to independently and simultaneously generate noise signals with multiple frequencies and amplitudes. A test circuit, either analog or digital, is fabricated on the same substrate. The generated noise signal(s) are generated for use in the evaluation and testing of the effects of the noise on the analog or digital test circuit.

Abstract: A method to generate a random number from certain input wherein at least parts of the input are modified by data that are independent of the generation of the random number and of the data included in the generation of the random number and a circuit configuration having a processing unit containing an encryption algorithm and a memory into which input is filed. Upon demand for a random number, the processing unit generates a random number using an encryption algorithm and input present in the memory, the current input then being changed by added data.

Abstract: A phase modulator circuit and method for generating an output signal having individually positionable edges is described. The phase modulator includes a programmable pulse generator, such as an interval counter, a delay, or a ring oscillator for producing the output signal, and a control value source, such as a memory, for delivering a sequence of control values to the generator. The control values determine the time between successive output pulses. A programmable interval counter includes a free running counter, the output of which is compared to a control value, preferably stored as a modulo data value, to generate an output pulse. A first programmable delay circuit includes a ring oscillator having plural delay lines for fine control of edge positioning. To fully synchronize the delay circuit to a coarse control interval counter, the clock input to the interval counter can be provided by the ring oscillator.

Abstract: A random number generating apparatus includes a noise source, a circuit for generating timing signals from the noise source, and a digital circuit that freely and continuously cycles through a predetermined distribution of states. The states of the digital circuit are stored at random times in accordance with the timing signals and are collected to form bytes of random numbers.

Abstract: According to the present invention, the solution includes the hardware hash algorithm block to automatically generate data to hash from its initialization values and to run unassisted instead of needing a continuous supply of additional input data. This approach according to the present invention solves the above shortcomings of related solutions by eliminating the need to continuously feed input data to be hashed to obtain a high fault coverage. This reduces the sizes of the firmware and test vectors necessary to test the hardware. Also, since the hardware autonomously generates new data to hash, other hardware modules can be tested in parallel. This reduces the overall test time and cost. To remove the requirement of inputting multiple fixed length sub-blocks, additional sub-blocks are created from the initial sub-block using a hardware expansion function, and the hardware continues to run unattended for some predetermined number of sub-blocks.

Abstract: Methods and circuitry for generating a cryptographic hash function using a strong pseudo-random generator along with the input data to create high quality pseudo-random keys as indices to pseudo-random functions, as well as a pseudo-random function from 2n bits to 2n bits given a pseudo-random function from n bits to n bits.

Abstract: An FM signal generator generates an FM signal obtained by frequency-modulating a reference frequency signal with a modulating frequency signal. A first mixer mixes the FM signal and an input signal having a predetermined carrier frequency and outputs a pair of frequency signals having sum and difference frequencies thereof. A first signal extracting unit extracts one of the pair of frequency signals as an intermediate frequency signal. A delay circuit delays the extracted intermediate frequency signal by a predetermined time. A second mixer mixes the delayed intermediate frequency signal and the FM signal and outputs a pair of frequency signals having sum and difference frequencies. A second signal extracting unit extracts the frequency signal of the pair of frequency signals which corresponds to the carrier frequency component as a phase-modulated signal. The modulation degree and modulation frequency in phase modulation for the phase-modulated signal can be set in wide ranges.

Abstract: A purely digital randomizer system generates an undeterministic data block using standard cell library units and includes a random number generator. The generator preferably includes at least two metastable blocks that each include a plurality of D-type flip-flops. Each flip-flop is coupled to a dedicated free-running oscillator whose frequency is based on a relative prime number for each frequency leg. Each of the D-type flip-flops is also coupled to receive a common jitter clock signal. The flip-flops are thus forcibly operated in a metastable state by intentionally violating the flip-flop set-up or hold time margins of incoming data relative to the jitter clock. To further maximize entropy, the flip-flop outputs are exclusively `OR`d ("EX-OR'd") and then passed through first and second shift registers of uneven and preferably even and odd bit lengths. Preferably each shift register includes at least one metastably-operated D-type flip-flop, to further promote randomness.

Abstract: Method and apparatus for an integrated noise circuit for generating broadband gaussian noise with specified spectral flatness, matching impedance, and power output characteristics. A diode section operated in an avalanche breakdown mode is the primary noise source. A resistor network is selected to provide the specified matching impedance. Additional series resistor sections in the circuit are laser trimmed in production for specified spectral flatness and output power. The integrated noise circuit may be packaged for surface mounting on a printed circuit board.

Abstract: A pseudorandom number generator which uses linear feedback shift registers and a nonlinear function circuit and can make the conditioned output distribution of generated pseudorandom numbers uniform even if the conditioned output distribution of the nonlinear function circuit has some deviation. The generator has a shift register to which the output of the nonlinear function circuit is inputted as a serial input, an initial value setting circuit for setting random initial values to the linear feedback shift registers and the shift registers, and an adder for adding predetermined bits of the parallel outputs of the register and outputting a pseudorandom number stream. The generator can be used to generate a cryptogram which cannot be deciphered by the correlation attack method.

Abstract: The present invention pseudo-random number generator produces a high precision number suitable for use as a data encryption communications security (COMSEC) key from a highly mobile computer platform. The random number generator is especially suitable for use with military radios and other like applications requiring a random number bit string of high precision. The present invention random number generator produces four pseudo-random numbers of 32-bits and uses only the last 28 bits of each number. A multiplicative linear congruential generator with multiplier 16807 and prime modulus 2.sup.31 -1 is used to produce the 32-bit pseudo-random numbers. This generator produces a sequence of remainders of large modulus. The last 28 bits of the 32-bit numbers are combined to produce one high precision number of 112 bits.

Abstract: A system and method for fuzzy spread spectrum communication. The system includes a fuzzy spreader for spreading an input signal over a range of frequencies and fuzzy despreader for extracting the spread input signal from the range of frequencies. In the illustrative implementation, the inventive system a fuzzy pseudo-random generator for use in the fuzzy spreader and the fuzzy despreader. The fuzzy pseudo-random generator uses a novel method for generating pseudo-random numbers. It does not use encryption or decryption techniques. The invention further provides a method for adaptive rule generation and a novel method for identifying the centroid of the set of output numbers. This allows the fuzzy system to learn spreading rules that favor data compression, compact multiplexing, bandwidth conservation, and other communication tasks as well as rules that favor security.

Abstract: A digital controller provides digital signals to audio modules; the digital signals include both clock signals and data. All of the logic circuits of the controller and of the modules are clocked on the receipt of a rising edge. However, to avoid interference from regular clock pulses, the clock pulses are altered to have a variable mark-space ratio which means that the clock pulses arrive at random times and have random widths and thus appear to be randomized. Use of randomized clock signals can avoid tones appearing in an audio system, and also avoids interference effects in other electrical systems. The use of randomized clock signals is particularly helpful when designing digital circuits which meet current regulations controlling electromagnetic emissions.

Abstract: A synchronous pseudo-noise (PN) code sequence generating circuit generates a plurality of PN code sequences which should be synchronized with each other. A feedback-type PN code generator generates a master PN code sequence. Each of N code converters, which are provided for each of N channels, converts the master PN code sequence to a PN code sequence of the corresponding channel in accordance with a mask pattern unique to the corresponding channel. The mask patterns for each channel are stored in the corresponding mask memory.