Abstract: A fixed-frequency control circuit and method detect the difference between the frequency of a pulse width modulation signal and a target frequency to adjust a current used to determine the on-time or off-time of the pulse width modulation signal, such that the frequency of the pulse width modulation signal is stable at the target frequency.

Abstract: The PWM control circuit is provided. The PWM control circuit includes: a PWM control signal generator that generates a PWM period signal defining a period of a PWM signal and a PWM resolution signal specifying a resolution in one period of the PWM period signal; and a PWM unit that generates the PWM signal based on the PWM period signal and the PWM resolution signal, wherein the PWM control signal generator changes a frequency of the PWM resolution signal while keeping a frequency of the PWM period signal unchanged.

Abstract: In a particular embodiment, a circuit device is disclosed that includes a data generator adapted to output a random pulse sequence having a particular spectral shape. The circuit device further includes a pulse edge control circuit to selectively apply a carrier suppression operation to at least one pulse-width modulated (PWM) signal in response to the random pulse sequence to produce at least one modulated PWM output signal. The spectral energy associated with a PWM carrier of the modulated PWM output signal at a carrier frequency and associated harmonics is changed such that the modulated PWM output signal has a spectral shape defined by the particular spectral shape.

Abstract: An adaptive pulse positioning modulator including a sense circuit which provides a compensation signal indicative of output voltage error, a filter circuit having an input receiving the compensation signal and an output providing an adjust signal, a leading ramp circuit which provides a repetitive first leading edge ramp signal having a slope which is adjusted by the adjust signal, a comparator circuit which provides a first start trigger signal when the first leading edge ramp signal reaches the compensation signal and a first end trigger signal when a first trailing edge ramp signal reaches the compensation signal, a trailing ramp circuit which initiates ramping of the first trailing edge ramp signal when the first start trigger signal is provided, and a pulse control logic which asserts pulses on a PWM signal based on the trigger signals.

Abstract: Methods and apparatus for translating duty cycle information in duty-cycle-modulated signals to higher frequencies or higher data rates. An exemplary duty cycle translator includes a duty cycle evaluator, a high-speed digital counter, and a comparator. The duty cycle evaluator generates a first digital number representing a duty cycle of a low-frequency input duty-cycle-modulated (DCM) signal. The comparator compares the first digital number to a second digital number generated by the high-speed digital counter, and generates, based on the comparison, an output DCM signal having a higher frequency or data rate than the frequency or data rate of the low-frequency input DCM signal but a duty cycle that is substantially the same as the duty cycle of the low-frequency input DCM signal.

Abstract: In one embodiment, the digital pulse width modulator of these teachings includes comparators and a number of phases and capable of increasing resolution without increasing clock frequency. In another embodiment, the digital pulse width modulator (DPWM) of these teachings includes equality comparators and a number of phases and increases resolution without increasing clock frequency. A further embodiment of the system of these teachings includes a priority encoded comparator component (in one instance including a number of comparators) comparing duty cycle commands against preset minimums, that embodiment being referred to as a frequency Foldback component. Other embodiments and embodiments of the method of these teachings are also disclosed.

Abstract: Switched-mode amplifiers and devices having such amplifiers include quadrature pulse-width modulation that is based on cartesian (as opposed to polar) coordinates. Two sets of pulses that represent respective in-phase and quadrature components of a conventional cartesian-coordinates input signal can be combined such that the combined set of pulses can be provided to a switched-mode amplifier without nonlinear cartesian-to-polar transformation and its associated wider internal bandwidth and other problems.

Abstract: A method of generating a MPWM signal for a portable device such as a cellular telephone. For a first duty cycle that includes a MPWM frequency having N magnitude levels, the method generates a first waveform comprising a first and a second On pulse during a first MPWM frequency period. The first and second On pulses are separated by an Off period.

Abstract: An integrated control circuit according to aspects of the present invention includes a capacitor to develop a first current during a first time duration in response to a charge current and to develop a second voltage during a second time duration in response to a discharge current. A comparator is also included and is coupled to the capacitor to indicate when the voltage on the capacitor reaches the second voltage. A control logic sets a duty ratio of a periodic output signal in response to the time it takes the capacitor to discharge from the first voltage to the second voltage. An oscillator is coupled to provide a timing signal to the control logic. In one aspect, the control logic includes an output that is coupled to the oscillator to change a frequency of the oscillator.

Abstract: In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively invert and swap the at least one PWM signal with a logic-inverted duty-cycle complement of the at least one PWM signal at discrete time intervals to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit.

Abstract: The objective of this invention is to provide a circuit that generates a spread frequency spectrum waveform with shaped frequency spectrum distribution. The waveform generator has a spread spectrum waveform generating circuit that generates a waveform with a spread spectrum and frequency spectrum distribution shaping circuit that shapes the frequency spectrum distribution of the spread spectrum waveform. In one embodiment, distribution shaping circuit can perform shaping such that the spread spectrum waveform has a frequency spectrum distribution having a spectrum reducing part in at least one band. Also, in one embodiment, the frequency of the spread spectrum waveform can vary periodically or nonperiodically.

Abstract: Noise reducing circuitry may be included in a pulse width modulation circuit. The pulse width modulation circuit may include a comparator adapted to receive an analog signal and a sawtooth signal and to compare such signals to generate a pulse width output. In general, the noise reducing circuitry may include a sawtooth signal generating circuit configured to generate a sawtooth signal including an up ramp and a sawtooth signal including a down ramp. A control circuit may be coupled to the sawtooth signal generating circuit for controlling the sawtooth signal generating circuit based on whether a relatively narrow or relatively wide pulse width is to be output by the pulse width modulation circuit. Methods for reducing noise in a pulse width modulation circuit may generally involve dynamically controlling a direction of ramp of a sawtooth signal that is to be input to the comparator of the pulse width modulation circuit.

Abstract: The PWM control circuit is provided. The PWM control circuit includes: a PWM control signal generator that generates a PWM period signal defining a period of a PWM signal and a PWM resolution signal specifying a resolution in one period of the PWM period signal; and a PWM unit that generates the PWM signal based on the PWM period signal and the PWM resolution signal, wherein the PWM control signal generator changes a frequency of the PWM resolution signal while keeping a frequency of the PWM period signal unchanged.

Abstract: This disclosure is directed to techniques for increasing the power efficiency of a modulator.

Abstract: A pulse width modulator for modulating a rectangular carrier signal in accordance with an input signal includes a modulating unit that receives the input signal and provides a digital output word. The output word has a pre-defined number of digits comprising a first contiguous set of binary ones (“1”) and a second contiguous set of binary zeroes (“0”) and in which the fraction of the binary ones (“1”) represents the digital input signal. The modulator also includes a random number generator that generates a pseudo-random sequence, and a flipping unit configured to flip, or not, the output word provided by the modulating unit in accordance with the pseudo-random sequence thus providing a randomly modified digital pulse width modulated output signal.

Abstract: In one embodiment, the digital pulse width modulator of these teachings includes comparators and a number of phases and capable of increasing resolution without increasing clock frequency. In another embodiment, the digital pulse width modulator (DPWM) of these teachings includes equality comparators and a number of phases and increases resolution without increasing clock frequency. A further embodiment of the system of these teachings includes a priority encoded comparator component (in one instance including a number of comparators) comparing duty cycle commands against preset minimums, that embodiment being referred to as a frequency Foldback component. Other embodiments and embodiments of the method of these teachings are also disclosed.

Abstract: A communication apparatus including: a modulator which modulates a reference clock signal having a predetermined basic frequency and outputs a modulated clock signal whose value fluctuates at a first frequency with respect to the basic frequency; a PWM signal generator which generates a PWM signal at a second frequency, with the modulated clock signal being as an operation clock; a switching portion which outputs a signal by switching an analog signal on the basis of the PWM signal; a filter which passes a signal included in an output signal of the switching portion, a frequency of the passed signal being lower than a third frequency, and a setting portion which sets the first frequency and the second frequency such that a fourth frequency in which a duty value of the PWM signal fluctuates is higher than the third frequency and such that the first frequency is higher than the second frequency.

Abstract: New methods for generating through-zero pulse-width modulation are disclosed. In one approach, a periodic reference signal varies over time over at least one portion of the period. A pulse-width control signal varies linearly with time over at least one portion of the reference signal. The reference signal is compared with the pulse-width control value to produce a first pulse waveform. The value of a function of the control value is subtracted from the first pulse waveform to produce through-zero pulse-width modulation. In another approach, the difference in value between two ramp or sawtooth periodic waveforms is computed to produce a pulse waveform with a time-varying DC offset that varies linearly in time. The time-varying offset-term is retained with the pulse waveform, producing through-zero pulse-width modulation.

Abstract: This invention relates to a power control circuit, and, an inventive PWM controller, switching circuit, high voltage discharge circuit and magnetic amplifier are also introduced and used to construct the power control circuit. The power control circuit has featured power saving and wide frequency band.

Abstract: A multichannel digital pulse width modulator/digital pulse frequency modulator uses a single ring oscillator that is shared by multiple channels. The ring oscillator has taps that can be used for least significant bit (LSB) precision of the generated PWM signal. The ring oscillator also produces a ring clock that is used to synchronize logic in the channels. Since the logic in the channels are synchronized by the ring clock, the channels can each independently produce different frequency PWM (or PFM) signals and still share the same ring oscillator.

Abstract: A pulse transmitter having a relatively simple structure and generating a pulse modulating signal even at a high transmission rate. In the pulse transmitter, a symbol pulse generating part (103) generates a symbol pulse of amplitude level ? when data S1 is “0,” and that of amplitude level &ggr; when data S1 is “1” in the first pulse slot section, the data pulse generating part (104) generates a data pulse of amplitude level 0 when data S2 to Sn is “0,” and that of amplitude level ? when data S2 to Sn is “1” in a later pulse slot section. The relationship of the amplitude levels keep the relation ?<?<&ggr. An adder (105) adds the symbol pulse and the data pulse and outputs the sum as a pulse modulating signal.

Abstract: In one embodiment, the digital pulse width modulator of these teachings includes comparators and a number of phases and capable of increasing resolution without increasing clock frequency. In another embodiment, the digital pulse width modulator (DPWM) of these teachings includes equality comparators and a number of phases and increases resolution without increasing clock frequency. A further embodiment of the system of these teachings includes a priority encoded comparator component (in one instance including a number of comparators) comparing duty cycle commands against preset minimums, that embodiment being referred to as a frequency Foldback component. Other embodiments and embodiments of the method of these teachings are also disclosed.

Abstract: The frequency characteristic of a voltage-feedback class-D amplifier circuit for driving an output load is improved. A triangular-wave correction circuit which compensates a gradient of a triangular wave is provided to a triangular-wave signal generator which supplies a triangular wave signal used as a PWM carrier to a comparison circuit for performing PWM modulation of an input signal. In an area where a duty of a command value for an output circuit drive becomes about 50%, a slew rate (gradient) of the triangular wave is decreased.

Abstract: Systems and methods for minimizing startup transients in digital audio controllers that may result in audible artifacts in the output of an audio amplification system. One embodiment comprises a digital PWM amplifier that includes a mechanism for controlling the amount of dead time in the audio output signal. When the amplifier starts up, the PWM signals provided to the output stage are simultaneously deasserted (i.e., there is dead time) for most of each switch period. The amount of dead time is gradually reduced over a series of switch periods until a nominal operating amount of dead time in each switch period is reached. Thus, the PWM signals are slowly ramped up from having a very large percentage of dead time (e.g., nearly 100%) to having a very small percentage of dead time (e.g., 1-2% to prevent shoot-through.

Abstract: Systems and devices for ripple reduction in a DC/DC converter are presented. The disclosed systems and methods enable ripple reduction in discontinuous conduction mode (DCM) operation. In DCM, the inductor current peak to peak ripple may be reduced based on the load current. To achieve the reduction of the inductor peak to peak current ripple, a digital counter is used to count the time between consecutive PWM pulses. The digital output of the counter is used to control the pulse width modulation. As the digital output of the counter increases, the PWM on-time decreases. Since the PWM pulse is demanded by the load in DCM mode, the peak to peak inductor ripple is modulated by the counter, or, in turn, modulated by the load current.

Abstract: Embodiments of the present invention include switching amplifier circuits and methods. In one embodiment, the present invention includes a low distortion method of driving a switching amplifier comprising modulating an audio input signal to produce a half-wave rectified pulse-width modulated signal and a complementary half-wave rectified pulse-width modulated signal. These signals may be amplified in a power amplifier and combined in a feedback circuit to generate a first feedback signal and a second feedback signal, which may be coupled the inputs of a modulator for controlling the output signal.

Abstract: A practical method and system for oversampled digitally controlled DC-DC converters is presented. To minimize the switching losses while maintaining all advantages of the oversampling, “glue logic” and application specific oversampling digital pulse-width modulator are introduced. Experimental results demonstrate transient response with 50% smaller deviation than that of conventional controllers, allowing for proportional reduction in the size of the power stage output capacitor.

Abstract: A pulse width modulating (PWM) circuit includes an activating module and a pulse generating module connected to the activating module. The activating module includes a current resource and a compensation unit. The current source generates an activating current, and the compensating unit detects the activating current and compensates the activating current if the activating current changes. The activating current is input to the pulse generating module to generate pulse voltages output by the pulse generating module.

Abstract: In a device (10) for modulating Cartesian base band signals (I, Q) a first and second mapping unit (12, 14) each map signal samples of a corresponding Cartesian signal (I, Q) to intermediary signal sections having only two non-zero levels provided symmetrically around zero for forming two intermediary signals (S1, S2). A first and second processing unit (16, 18) each map each intermediary sections of an intermediary signal (S1, S2) to segments of a corresponding pulse train (S3, S4) through providing a positive pulse in one half of a segment if the corresponding signal section has a positive signal level and a positive pulse in another half of the segment if the corresponding signal section has a negative signal level. A delay unit (20) delays the pulses of one train in relation to the other and a combining unit (22) combines the trains for provision to a power amplifier (24).

Abstract: Output circuits using pulse width modulation (PWM) and/or pulse density modulation (PDM) are described. In one aspect, a PWM output circuit includes a PWM modulator that operates based on a square wave signal instead of a sawtooth or triangular wave signal. In another aspect, a PDM output circuit includes a PDM modulator that uses variable reference voltages to reduce variations in switching frequency. In yet another aspect, a dual-mode output circuit supports both PWM and PDM and includes a pulse modulator and a class D amplifier. The pulse modulator performs PWM on an input signal if a PWM mode is selected and performs PDM on the input signal if a PDM mode is selected. The class D amplifier receives a driver signal from the pulse modulator and generates an output signal.

Abstract: An electric motor, having a stator (465), a rotor (470), and an apparatus for evaluating a signal provided for controlling said motor (110), comprises a receiving unit (430, 440) for receiving a control signal (PWM_mod), which is a pulse width modulated signal (PWM) onto which a data signal (DIR, DATA) is modulated. An evaluation unit (440) is provided for evaluating the modulated control signal (PWM_mod). The unit is configured to extract, from the modulated control signal (PWM_mod), data provided for operation of the motor (110). The control apparatus includes a signal generator (450) configured to generate, on the basis of the extracted or ascertained data provided for operation of the motor (110), at least one control signal for the motor (110), such as a commanded direction of rotation. Piggybacking other control data onto the PWM power level signal reduces hardware investment, by permitting omission of a signal lead which would otherwise be required in the motor structure.

Abstract: The signal generating apparatus includes a signal modulating unit, a selection signal generating unit, and a phase adjusting unit. The signal modulating unit is utilized for processing a modulation upon an input signal to generate a modulated signal. The selection signal generating unit is utilized for generating at least a first selection signal. The phase adjusting unit is coupled to the signal modulating unit and the selection signal generating unit, and is utilized for receiving the modulated signal and adjusting a pulse width of the modulated signal to generate an output signal according to the first selection signal.

Abstract: A pulse width modulating (PWM) circuit includes an activating module and a pulse generating module connected to the activating module. The activating module includes a current resource and a compensation unit. The current source generates an activating current, and the compensating unit detects the activating current and compensates the activating current if the activating current changes. The activating current is input to the pulse generating module to generate pulse voltages output by the pulse generating module.

Abstract: A method and apparatus is described for a time modulated signal. A cosine function is used as the basis for the signal with time intervals at the maximum and minimum values of the cosine function defining the encoded data. The received waveform is twice differentiated to provide a cosine function from which zero crossings are detected and the time intervals determined.

Abstract: A method for reducing the transition rate of a pulse width modulated signal representing an original signal having a predetermined frequency range of interest and producing an output signal, the method including the steps of: combining pulses from a predetermined number of consecutive frames into a combined pulse; and positioning the combined pulse within the predetermined number of consecutive frames, such that the output signal has substantially the same Fourier Transform phase as the pulse width modulated signal, for at least the predetermined frequency range of interest of the original signal.

Abstract: A pulse width modulation signal generator includes a triangular wave generator, a voltage comparator, and a wave shaping circuit. The triangular wave generator generates a triangular wave signal and a pair of first and second pulse signals. The first pulse signal is pulsed for a given duration of time when the triangular wave signal reaches a minimum limit thereof. The second pulse signal is pulsed for a given duration of time when the triangular wave signal reaches a maximum limit thereof. The voltage comparator generates a first pulse width modulation signal by comparing the triangular wave signal with an externally supplied direct current signal. The wave shaping circuit generates a second pulse width modulation signal by removing chattering components occurring immediately after rising and falling edges of the first pulse width modulation signal with a masking signal generated based on the first and second pulse signals and the first pulse width modulation signal.

Abstract: Provided is a pulse width modulation (PWM) pulse generating circuit, a device including the circuit, and a PWM control method. The circuit includes a detector to detect the frequency of the PWM clock signal and output a frequency detection signal including whether the frequency of the PWM clock signal is higher than a reference frequency, and a PWM pulse signal output unit to generate a PWM pulse signal according to a data signal, the PWM clock signal, and the frequency detection signal. When the frequency detection signal includes that the frequency of the PWM clock signal is higher than the reference frequency, the PWM pulse signal output unit generates the PWM pulse signal having a predetermined allowable pulse width or a pulse with that is higher than the predetermined allowable pulse width.

Abstract: In a device, a pulse modulation switching logic is provided to generate switching signals of a pulse modulator so as to generate a pulse modulated signal with a first pulse modulation control parameter and a second pulse modulation control parameter. The first pulse modulation control parameter is controlled on the basis of a first control signal, and the second pulse modulation control parameter is controlled on the basis of a second control signal. A first control loop is provided to generate the first control signal from an output signal derived from the pulse modulated signal. A second control loop is provided to generate the second control signal on the basis of the output signal. The first and second control signals are applied to concurrently control the first and second pulse modulation control parameters.

Abstract: A multichannel digital pulse width modulator/digital pulse frequency modulator uses a single ring oscillator that is shared by multiple channels. The ring oscillator has taps that can be used for least significant bit (LSB) precision of the generated PWM signal. The ring oscillator also produces a ring clock that is used to synchronize logic in the channels. Since the logic in the channels are synchronized by the ring clock, the channels can each independently produce different frequency PWM (or PFM) signals and still share the same ring oscillator.

Abstract: The present disclosure relates to I/Q modulation circuits, devices, and methods.

Abstract: A pulse width modulation (PWM) signal generator generates a PWM signal having a specified effective PWM duty resolution for a corresponding cycle window. The PWM signal generator receives an N-bit value representing a duty to be implemented and sets values X and Y to the M least significant bits and the N-M most significant bits, respectively, of the N-bit value. The value M can be determined based on the value N and a maximum implementable frequency of a clock signal used to time the generation of each PWM cycle. The PWM signal generator generates a cycle window of 2M PWM cycles, each PWM cycle of the cycle window having a duty of either Y or Y+1. The number of PWM cycles in the cycle window having the duty Y+1 is based on the value X and the PWM cycles having a particular duty are contiguous within the cycle window.

Abstract: Provided is a control technique of a PWM conversion type power converter capable of compensating for a voltage error due to voltage drop mainly at a switching element and managing a switching time of a PWM signal at the same time, and capable of suppressing increase/decrease of software operation load and addition of a hardware circuit to the minimum. A semiconductor integrated circuit having a PWM signal generating unit which generates a PWM signal is provided with a PWM timer unit including a counter counting a pulse width of a pulse signal inputted from the outside with delay from a PWM signal, a register loading a counter value of the counter in synchronization with the PWM signal, and an A/D converting unit converting an analog signal serving as a source signal of the pulse signal inputted from the outside to a digital signal.

Abstract: A digital pulse width modulation device includes a counter, a first comparator and a second comparator, wherein the first and second comparators are connected in parallel with each other and in series with the counter. The counter is capable of sending a count signal to the first and second comparators simultaneously, starting a count when the counter receives a clock signal, and transmitting the count signal to the first and second comparators. If the first comparator receives a pulse duty width signal, the count of the count signal will generate a pulse output of the corresponding duty cycle. If the second comparator receives a total pulse duty length signal and the count of the count signal reaches a number of the total length, a clear signal will be outputted to the counter to reset the counter to zero, so as to achieve the effect of correcting the output pulse.

Abstract: An example digital-to-analog converter (DAC) for a power supply controller includes a first node, a second node, a current source, and a switch. The first node is to be coupled to provide a first analog signal to a variable oscillator of the power supply controller. The second node is to be coupled to provide a second analog signal to the variable oscillator of the power supply controller. The switch is coupled to the current source and configured to couple the current source to the first node to provide current to the first analog signal in response to a binary digit received by the DAC, where the switch is further configured to couple the current source to the second node to provide current to the second analog signal in response to a complement of the binary digit.

Abstract: A pulse width modulator (PWM) includes a driver and a two-way integrator. The driver is coupled to output a first and a subsequent period of a PWM signal. Both the first and the subsequent periods include the PWM signal changing between first and second states. The two-way integrator is coupled to integrate an input current and coupled to generate a duty ratio signal in response to integrating the input current. The driver determines a duty factor of both the first and the subsequent periods by setting the PWM signal to the second state in response to the duty ratio signal. The two-way integrator includes a capacitor that integrates the input current during the first period by charging the capacitor and integrates the input current during the subsequent period by discharging the capacitor.

Abstract: System and method for digitizing analog voltage signals. A first voltage signal may be received at a comparator. A ramp signal may be received at the comparator. The ramp signal may be generated by a ramp generator. An output signal may be generated by the comparator. The output signal may indicate whether the analog voltage signal or the ramp signal is greater. The output signal may be conveyed to logic circuitry by the comparator. Control information may be conveyed by the logic circuitry to the ramp generator. The ramp generator may generate the ramp signal based on the control information. The logic circuitry may determine a digital representation of the first voltage signal based on the output signal from the comparator and the control information.

Abstract: A microcomputer includes: a CPU executing a predetermined calculation process; and a PWM timer generating a PWM pulse. The PWM timer includes a RAM for storing a duty value of the PWM pulse and a PWM controller for generating the PWM pulse. The PWM controller includes a PWM counter for counting up from a predetermined value as an initial value. The PWM pulse has an unit waveform, which is generated based on comparison between the duty value of the RAM and an output value of the PWM counter. The RAM outputs a new duty value at every comparison without functioning the CPU so that the duty value of the PWM pulse is changed in chronological order.

Abstract: A PWM signal generating circuit outputs a stable PWM signal for increasing and decreasing a duty ratio at a predetermined rate within a predetermined period without requiring an improvement of a process capacity of a CPU as compared to a conventional PWM signal generating circuit. The PWM signal generating circuit consists of a plurality of circuit elements each of which outputs a digital signal. A first counter circuit periodically changes a PWM signal output therefrom into an active state. A second counter circuit changes the PWM signal, which has been changed into the active state by the first counter circuit, into an inactive state within each cycle. The second counter circuit increases and decreases an active-to-inactive time period from a time when the PWM signal is changed into the active state to a time when the PWM signal is changed into the inactive state.

Abstract: An apparatus and a method for a I-Q quadrature modulation transmitter monitor a phase bias between an I branch and a Q branch of the I-Q quadrature modulation transmitter. The I-Q quadrature modulation transmitter includes the I-branch, the Q-branch equipped with a phase bias, and a tap. The apparatus is installed between the tap and the phase bias, and monitors the phase between the I branch and the Q branch which phase is introduced by the phase bias. The apparatus includes the following components: a module squarer, receiving signal from the tap and outputting a module square of the received signal; a multiplier, to multiplying data of the I-branch, data of the Q-branch and the module square to output a multiplied signal; and an averager, averaging the multiplied signal output by the multiplier. The phase between the I branch and the Q branch may be corrected according to monitoring results.

Abstract: A module including a case; an electrical switching device configured to control power to a load; and a controller coupled to the electrical switching device. The electrical switching device and the controller are substantially encapsulated by the case. Functionality of the module can be exposed through a communication interface in the case.