Abstract: A D/A conversion circuit for performing D/A conversion at high speeds. The D/A conversion circuit includes a resistor string including a plurality of resistor elements connected between a low-potential power supply and a high-potential power supply. A plurality of first switch groups are connected to the connection nodes between the resistor elements for selectively outputting voltages at the connection nodes. The outputs of the switches of the first switch groups are connected in common to a corresponding one of the nodes. The plurality of nodes are connected to an output terminal of the D/A conversion circuit via a second switch group. Predetermined switches of the first switch groups are connected in parallel to third switches to apply voltages to the nodes.

Abstract: A comparator has a differential input stage, a current source coupled to the differential input stage for providing a tail current to one side of the differential input stage, and a differential load coupled to the differential pair and having at least one diode coupled load transistor per differential side. A load current through either one of the at least one diode coupled load transistor on either differential side is mirrored with a current mirror configuration to provide a current be fed to a respective node, each node being coupled to a respective variable biasing current source and a respective other side of the differential input stage, so as to provide a variable positive feedback to the differential input stage.

Abstract: A data driver used in a current-driving display device for receiving a digital signal and for outputting a gray-scaled current signal to a data line. The data driver includes a digital-to-analog current converter for transforming the digital signal into an analog current signal, a current-copying/reproducing module, and a control circuit. The current-copying/reproducing module is used to store a predetermined voltage for conducting the analog current signal in a transforming/storing status and to conduct a reproducing current signal to the data line in a reproducing/sustaining status. The control circuit is electrically connected between the digital-to-analog current converter and the current-copying/reproducing module for providing a switch between the transforming/storing status and the reproducing/sustaining status. The reproducing current signal is the gray-scaled current signal and is almost equivalent to the analog current signal.

Abstract: This invention discloses a digital to analog converter (DAC) for converting a digital signal with a predetermined number of bits to a corresponding analog signal, the DAC comprises a first current source element having a first control signal, the first control signal controlling the conduction current provided by the first current source element, and a second current source element having a second control signal, the second control signal controlling the conduction current provided by the second current source element, wherein the first and the second control signals have different voltages during operation of the DAC.

Abstract: In an mode of this invention, a digital/analog conversion circuit, includes: a digital/analog conversion portion which outputs a first current according to an input digital signal; and a first current mirror circuit which generates a mirror current according to the first current and outputs the mirror current as an analog signal, the digital/analog conversion circuit converting the digital signal into the analog signal, and further including: a second current mirror circuit, which generates a first mirror current according to the first current; and a third current mirror circuit, which is connected to a reference voltage, and to which the first mirror current is input, and which generates a second mirror current equal to the first current, according to the first mirror current, between the digital/analog conversion portion and the second current mirror circuit.

Abstract: A multi-mode digital-to-analog converter (DAC) configured to operate in a plurality of modes.

Abstract: Embodiments relate to a current cell circuit in a digital-analog converter. According to embodiments, a current cell circuit in a digital-analog converter may include a current source connected to a power voltage terminal to generate current having a predetermined magnitude, a first current switch transferring current provided from the current source to a first output terminal, a first current generator detecting output voltage from the first output terminal and generating the amount of reduced current from the detected voltage, and a first current supplier supplying the amount of current generated from the first current generator to the first current switch. According to embodiments, current variations at a constant output voltage may be minimized. This may make it possible to obtain more stable frequency characteristics.

Abstract: An apparatus for analog-to-digital conversion using successive approximation is provided. There is a successive approximation register or SAR controller for providing a digital code representing a conversion result, and an integral non-linearity (INL) compensator configured to provide an INL compensation signal for reducing INL of the analog-to-digital conversion in response to the digital code.

Abstract: A system for generating a programmable exponential analog output signal, comprising a digital to analog conversion circuit for converting said digital signal into an analog output signal, the digital to analog conversion circuit having a substantially exponential transfer function defined by a programmable ratio of values of components. Preferably, the conversion circuit is implemented as a current mirror (100), with the exponential transfer function being defined by the mirror ratio. Thus, each transistor of the current mirror (100) defines a step of the digital to analog conversion circuit, and the ratio between adjacent steps is substantially constant. The transistors may be substantially equally sized or binary weighted relative to each other, and can be switched from the input to the output under the control of a tree based thermometer line decoder.

Abstract: A successive approximation analog-to-digital converter includes a capacitor array having a plurality of switch capacitors therein with varying weights, each having a common plate connected to a common node and a switched plate. A SAR controller samples an input voltage on said capacitor array in a sampling phase and redistributes the charge stored therein in a conversion phase by selectively increasing the voltage on select capacitors of the capacitor array in accordance with a SAR conversion algorithm. Circuitry controls the sampling of the input voltage by the capacitor array and is responsive to at least one applied bias current. The at least one applied bias current operates at a first level responsive to a first mode of operation of the SAR ADC and operates at a second level responsive to a second mode of operation of the SARADC.

Abstract: A pipelined current mode analog-to-digital converter, including: a plurality of stages each having a first sample and hold circuit configured to receive an analog signal having a current; the sample and hold circuit having at least first and second outputs; the first output having a current from a current copier configured to copy the analog signal; the second output having a current from a current mirror configured to mirror the analog signal; a current mode analog-to-digital converter configured to create a digital signal from the second output, the second output being connected to an input of the analog-to-digital converter; and a current mode digital-to-analog converter configured to convert the digital signal back to an analog signal, wherein an output of the digital-to-analog converter is subtracted from the first output of the sample and hold circuit.

Abstract: A resistor network digital-to-analog converter (DAC) subdivides each sampling clock cycle of the DAC into a number of phases. For at least one bit input of the DAC associated with a desired input resistor weight, the input bit value is sampled at each phase. Each of those sampled values is then applied to a respective resistor branch, the parallel set of resistor branches forming the parallel equivalent of the desired input resistor weight for that bit input. Such application may be, for example, via a slew-rate controlled driver, to smooth transient edges in the generated analog output signal. The resulting analog signal experiences reduced reconstruction errors at a higher frequency while consuming less power than a comparable oversampling DAC. Shifting reconstruction errors to higher frequencies relaxes downstream filtering requirements, which simplifies analog signal filtering and allows, for example, the use of current-mode low pass filters.

Abstract: A current output circuit with bias control and a method thereof are provided. The current output circuit includes a current mirror circuit comprising a first transistor and a second transistor having respectively two drains, and a control circuit coupled to the current mirror circuit. The control circuit receives drain voltages of the first transistor and the second transistor, and adjusts a respective gate bias of the first transistor and the second transistor according to a respective drain voltage thereof.

Abstract: When a semiconductor circuit, in which a stabilizing capacitor 2 for stabilizing a reference voltage Vbias is connected to a reference voltage terminal RT, recovers from a power down state to an operational state, a current mirror circuit 40 provides current mirroring of a current Ia of a first current path Ph1, which generates an OFF threshold voltage ref1 of a hysteresis comparator 1, to generate a current Ib of a second current path Ph2, which generates the reference voltage Vbias. The reference voltage Vbias is input to the comparator 1 as an input voltage vin. When the reference voltage Vbias becomes equal to the OFF threshold voltage ref1, the comparator 1 immediately stops the charging of the stabilizing capacitor 2 by a current source I1.

Abstract: A D/A converter of the current switching type has a first current mirror circuit that D/A converts the upper (n?m) digits in n bit data to be converted and a weighting current circuit block or a second current mirror circuit that D/A converts the lower m digits in the data, by cascade connecting the weighting current circuit block or the second current mirror circuit at the upstream or at the downstream side of an output side transistor other than the output side transistors of the first current mirror circuit. In this manner, current flowing through the output side transistor flows as diverting currents to the weighting current circuit block or the second current mirror circuit corresponding to the digit weights of the lower m digits, and the diverting currents are taken out at the outputs of the D/A conversion circuit as analog converted currents of the lower m digits.

Abstract: A D/A converter of the current switching type has a first current mirror circuit that D/A converts the upper (n?m) digits in n bit data to be converted and a weighting current circuit block or a second current mirror circuit that D/A converts the lower m digits in the data, by cascade connecting the weighting current circuit block or the second current mirror circuit at the upstream or at the downstream side of an output side transistor other than the output side transistors of the first current mirror circuit. In this manner, current flowing through the output side transistor flows as diverting currents to the weighting current circuit block or the second current mirror circuit corresponding to the digit weights of the lower m digits, and the diverting currents are taken out at the outputs of the D/A conversion circuit as analog converted currents of the lower m digits.

Abstract: In an mode of this invention, a digital/analog conversion circuit, includes: a digital/analog conversion portion which outputs a first current according to an input digital signal; and a first current mirror circuit which generates a mirror current according to the first current and outputs the mirror current as an analog signal, the digital/analog conversion circuit converting the digital signal into the analog signal, and further including: a second current mirror circuit, which generates a first mirror current according to the first current; and a third current mirror circuit, which is connected to a reference voltage, and to which the first mirror current is input, and which generates a second mirror current equal to the first current, according to the first mirror current, between the digital/analog conversion portion and the second current mirror circuit.

Abstract: A design structure embodied in a machine readable medium, the design structure including a current mirror including N stages, each stage comprising 2n?1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N?1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, every input of the N inputs connected to a different stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.

Abstract: A digital to analog converter. The digital to analog converter including a current mirror comprising N stages, each stage comprising 2n?1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N?1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, every input of the N inputs connected to a different stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.

Abstract: One embodiment of the present invention includes a pipelined analog-to-digital converter (ADC) comprising a plurality of pipeline stages. At least one of the plurality of pipeline stages comprises a feedback transistor-follower combination interconnected between a positive source voltage and a summation node and configured to set a voltage of the summation node approximately equal to a sample-and-hold voltage associated with a preceding one of the plurality of pipeline stages. The at least one of the plurality of pipeline stages also comprises a current mirror coupled to the feedback transistor-follower combination configured to provide a first current that is approximately equal to a second current that is associated with the feedback transistor-follower combination. The at least one of the plurality of pipeline stages further comprises an output resistor configured to set an output voltage of the respective at least one of the plurality of pipeline stages based on the first current.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for protection for the transmission of higher amplitude outputs required of differential amplifiers formed by thin oxide transistors with limited maximum voltage tolerance used where compliance with communication protocol standards requires handling voltages which may, in transition, exceed desirable levels is provided by limiting the voltage across any two device terminals under power down conditions.

Abstract: The invention relates to integrated circuits comprising a set of identical differential pairs of two transistors each (T1, T2; T3, T4) one receiving a variable voltage (Vinp, Vinn) at its base and the other receiving a fixed reference voltage (Vrefp, Vrefn). In order to reduce the dispersion of the offset voltages of said differential pairs, it is provided that the transistor (T2, T4) that receives a fixed reference voltage has an emitter surface at least twice as large as the transistor (T1, T3) that receives a variable voltage at its base. Application to signal folding circuits and to analog-to-digital converters using differential pairs of transistors.

Abstract: In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor has a source coupled to the output node and a gate coupled to a bias voltage. A current source circuit selectively biases the second MOS transistor to act as part of a source-follower circuit when the output node is to be in a second state. Additionally, a memory circuit has an input coupled to the output node, and an output. The memory circuit is configured to temporarily store a Boolean value of the output node when the output node transitions from the first state to the second state. Further, a discharging circuit is coupled to the output node and a second reference voltage.

Abstract: A data line drive circuit is equipped with a single line driver and a gate voltage generation circuit. The single line driver is constructed such that N groups (where N is an integer 2 or larger) of series connections of drive transistors and switching transistors are connected in parallel. The gate voltage generation circuit includes two transistors constituting a current mirror circuit, a drive transistor, and a constant voltage generation transistor. The range of an output current Iout can be controlled by changing any of the design values of the parameters including: relative values Ka and Kb of the gain coefficient for the transistors, the source voltage VDREF of the gate voltage generation circuit, and the gate signal VRIN of the drive transistor.

Abstract: A D/A converter includes a plurality of current sources configured to be on or off according to input digital data; a constant voltage source configured to apply a constant voltage to the current sources; current supply wirings provided between the constant voltage source and the respective current source, the current supply wirings respectively having equal length from the constant voltage source to the respective current source; ground-side wirings summing up output currents from the plurality of current sources; and output terminals connected to the ground-side wirings, the output terminals outputting analogue data corresponding to the input digital data.

Abstract: A current mirror type D/A converter circuit is constructed with transistor cells each including a MOS transistor, a gate region of which MOS transistor has folded stripe configuration in a plan view thereof, or a current flowing direction in a channel of which is a folded stripe in plan view.

Abstract: A radio frequency digital-to-analog converter with a programmable current output. In exemplary aspects of the invention, improved apparatus and methods for providing (i) current mirror matching, (ii) enhanced current pulse rising edge performance, (ii) reduced base voltage swing, and (iv) compensated high voltage swing, are provided. The foregoing apparatus and methods can be applied to any RF signal application (wireless or otherwise), including for example wireless cellular handsets.

Abstract: A current output circuit with bias control and a method thereof are provided. The current output circuit includes a current mirror circuit comprising a first transistor and a second transistor having respectively two drains, and a control circuit coupled to the current mirror circuit. The control circuit receives drain voltages of the first transistor and the second transistor, and adjusts a respective gate bias of the first transistor and the second transistor according to a respective drain voltage thereof.

Abstract: A D/A converter circuit includes a first current mirror circuit and a second current mirror circuit. The first current mirror circuit has a plurality of output side transistors provided correspondingly to digits of data to be converted and generates en analog current by obtaining, in at least one of the output side transistors, a current corresponding to the weight of the digit of the data being converted. The second current mirror circuit is connected on an upstream or downstream side of the output side transistors and corresponding to a lower digit of the data. An analog current is generated with the second current mirror circuit by obtaining a current corresponding to a weight of a digit that is less than 1.

Abstract: A digital current source used to mirror a reference current is provided. The digitally controlled analog current source multiplies a current from a master mirror transistor producing an output current that is a digitally controlled multiple of the reference current. The circuit comprises a plurality of one bit current mirror cells. Each one bit current mirror cell comprises a mirror transistor receiving an analog gate voltage from a master mirror transistor and providing a drain voltage, an operational amplifier configured to maintain the drain voltage for the mirror transistor equivalent to the analog gate voltage, and a switch configured to receive one control bit, the switch enabling current mirroring when the mirror voltage is substantially equivalent to the master mirror voltage. The digital current source further includes a common line summing element employed to receive and compile currents from each of the one bit current mirror cells.

Abstract: Source potentials of n output transistors are fixed by common fixed voltage, and sources are connected to a current output terminal. A drain and a gate of an input transistor are commonly connected to the drains and the gates of the output transistors respectively. A first current-to-voltage conversion unit is connected onto the drain side of the input transistor to convert current Im2 flowing through the input transistor into voltage Vx1. A second current-to-voltage conversion unit converts reference current Iref into voltage Vx2. The voltages Vx1 and Vx2 are input to a first error amplifier, and the first error amplifier adjusts gate voltages of the input transistor and output transistors. n switches are provided on a path through which output of the first error amplifier reaches the gate of the output transistor. A control unit controls on/off of the switch according to a digital signal.

Abstract: A low-noise programmable current source includes an output digital to analog converter for providing an output load current; and a control circuit, responsive to an input defining a predetermined load current for generating, for the digital to analog converter, a control word and a control voltage; the control word and the control voltage drive the digital to analog converter to produce the predetermined load current and the control voltage sets the compliance voltage of the digital to analog converter to minimize current noise in the digital to analog converter.

Abstract: A current range control circuit for a data driver in an organic light emitting display. The data driver includes a shift register for outputting a latch control signal, a data latch for sequentially receiving video data and to output the video data in parallel, a digital to analog converter for converting the outputs of the data latch into analog currents, and the current range control circuit for outputting data currents corresponding to the analog currents and controlling the data current range using current range control signals. Because it is possible to control the range of the data currents output from the data driver, it is possible to use the data driver in various pixel circuits or electroluminescent devices by changing the current range control signals, and to make the drain voltages of the transistors that form a current mirror equal to each other to obtain the desired current values.

Abstract: Protection for the transmission of higher amplitude outputs required of differential amplifiers formed by thin oxide transistors with limited maximum voltage tolerance used where compliance with communication protocol standards requires handling voltages which may, in transition, exceed desirable levels is provided by limiting the voltage across any two device terminals under power down conditions.

Abstract: Reference generator embodiments are provided with low output impedances to enhance reference stability in the presence of varying loads. The generators are structured to provide these impedances in an efficient manner (i.e., with low supply currents) and also to provide both sink and source currents to better handle large transient current demands. The generators also include cascode structures that facilitate operation with low values of a supply voltage and that provide a low sensitivity to variations in this supply voltage. The embodiments are especially suited for use in signal converter systems.

Abstract: A reference buffer includes a first current mirror, a second current mirror, a first source follower coupled in series to a branch of the first current mirror and receiving a first initial reference voltage and outputting a first reference voltage, a second source follower coupled in series to a branch of the second current mirror and receiving a second initial reference voltage and outputting a second reference voltage, and a resistor coupled between a first node and a second node outputting the first and second reference voltages, respectively. The first node is disposed between the first current mirror and the first source follower and the second node is disposed between the second current mirror and the second source follower. The voltage difference between the first reference voltage and the first initial reference voltage is substantially same as that between the second reference voltage and the second initial reference voltage.

Abstract: The present invention is intended to provide an A/D converter making it possible to reduce the power consumption of an output interface. The A/D converter includes an output current value designation register that holds a value sent from an upper-level unit, and an output current value designation circuit that controls a constant current source, which supplies a constant current to a low-voltage differential signal output circuit, according to the value held in the output current value designation register so as to designate an output current value.

Abstract: A method of Digital to Analogue conversion of an input signal Do for suppressing the effect of clock-jitter in a Delta-Sigma analogue to digital converter, or class D amplifier, comprises charging a capacitor to a reference voltage value (Vref) during a first phase (?) of a clock signal, discharging the capacitor during a second phase (?2) of the clock signal, wherein the discharge is regulated by a biased transistor, responsive to the voltage on the capacitor, in a first part of the second phase to provide an approximately constant discharge current, and regulated in a second part of the second phase for rapidly discharging the capacitor before the end of the second phase; and providing an output (Ud, OUT) as a function of the discharge current and the input signal Do. The output signal Ud, may be applied as a feedback signal to a loop filter in a Delta-Sigma converter. Alternatively, the output may represent the output of a Class D amplifier.

Abstract: Embodiments of a current range control circuit, data driver and organic light emitting display are disclosed, wherein the current range control circuit is configured to adjust a range of an input current in the data driver according to a type of display device. One embodiment of the data driver comprises a data latch configured to sequentially receive video data according to a latch control signal and output the video data in parallel. A multiplexer multiplexes the outputted video data, and a D/A converter converts the multiplexed video data into analog current signals. The data driver further comprises a current range control circuit configured to receive data current signals from the D/A converter and output a demultiplexed data current. The current range control circuit is further configured to adjust a range of the data current according to a current range control signal.

Abstract: A current source cell of one embodiment according to the present invention comprises: first and second transistors which are complementarily switched by a control signal; a constant current source which is commonly connected to one ends of current paths of the first and second transistors; third and fourth transistors which are respectively connected between the other ends of the current paths of the first and second transistors and first and second output terminals, and which being in normally conducting states; and an inversion amplifier having an input terminal which is commonly connected to the one ends of the current paths of the first and second transistors, and having output terminal which is commonly connected to control terminals of the third and fourth transistors.

Abstract: A current driven D/A converter sets an OFF control voltage (BIAS3) for turning off NMOS transistors M12P, M12N, M22P, M22N, M32P and M32N at a voltage close to an ON control voltage (BIAS2). This makes it possible to reduce the swing of the control voltage (ON control voltage-OFF control voltage) of the NMOS transistors, and hence to reduce the noise due to charge injections through parasitic capacitances, and noise of a ground voltage or power supply voltage due to flowing of discharge currents from the parasitic capacitances to the ground or power supply at turn off of the transistors, thereby being able to offer a high performance current driven D/A converter.

Abstract: An apparatus for error compensation of a self calibrating current source adapted for compensating errors of at least one self calibrating current source. The compensation apparatus includes an imitative self calibrating current source, a current source reference apparatus and an error compensation apparatus. The imitative self calibrating current source is used to simulate the structure of the self calibrating current source to generate an error bias signal as the error of the self calibrating current source. The current source reference apparatus is used to generate an ideal bias signal. The error compensation apparatus generates a compensation bias signal to compensate errors of the self calibrating current source according to the difference of the error bias signal and the ideal bias signal.

Abstract: A high accuracy D/A converter includes D/A converter sections including 64 current cells for outputting a current corresponding to 1 LSB of 8-bit input data and a D/A converter section including 63 current cells, a reference current generating section for supplying the respective D/A converter sections with reference currents, and a decoder for activating each of the current cells from the D/A converter sections to the D/A converter section in the stated order in a cyclic manner when the 8-bit input data value is increased, and deactivating one each of the activated current cells from the D/A converter section to the D/A converter section in the stated order in a cyclic manner when the 8-bit input data value is decreased.

Abstract: A compact and highly accurate A/D converter includes series-connected computation cells, the number of which is equal to the number for bits in an output signal. The first computation cell includes a first comparison unit for subtracting a reference current from a first input current to generate a first current, and a second comparison unit for subtracting a second input current from the reference current to generate a second current. The second computation cell includes first and second comparison units having the same configurations as those in the first computation cell. The computation cells of latter stages have the same configurations as the second computation cell. Current mirror circuits included in the first and second comparison units of each computation cell generate the first and second currents. Each computation cell outputs a current having an absolute value in accordance with one of the first and second currents.

Abstract: In a transmitter/receiver for bidirectional communication with a transmission medium, the transmitter comprises an amplifier having an input terminal for signals to be transmitted, an output stage with output terminals coupled via resistors to the transmission medium, and a negative feedback circuit connected with its input terminals to the output terminals and with its output terminal to the input terminal of the amplifier. The receiver is connected with first input terminals to the output terminals of the output stage. A current mirror is connected with its input terminal to the input terminal of the amplifier output stage and with its output terminals via resistors across a load. The load is connected across second input terminals of the receiver. The receiver is adapted to extract signals received from the transmission medium by subtracting voltages between said second input terminals from voltages between said first input terminals.

Abstract: According to an aspect of present invention, a quantizer is provided with reduced power consumption and area. Such a feature is attained by providing the input signal and a reference signal on input terminals of a pre-amplifier, and coupling the differential output terminals of the pre-amplifier to the gate terminal of respective transistors. The drain/source currents of the transistors are provided to a current latch, which generates the comparison result. The latches and transistors are replicated conveniently to interpolate additional reference values. The width to length (W/L) of the channels in each replicated set are set to different values to cause the reference signal to be at corresponding strength.

Abstract: A DAC circuit can include a plurality of current source circuits configured to operate responsive to respective different bias voltage signals and respective true and complementary binary digit signals.

Abstract: A wide gain range current digital-to-analog converter (DAC) is presented that includes a unit current cell having a current source module biased by a current source voltage bias, a differential switch module, a main cascode module biased by a first bias voltage and an attenuation cascode module biased by a second bias voltage, configured such that a particular current gain range is obtained at the main cascode module output when a unit current cell current is at or above a current threshold. The output current at the attenuation cascode module output can be input into a current attenuator when the unit current cell current is below the current threshold to obtain additional current gain range. The current attenuator can include a plurality of attenuator cells that can be programmed to a desired level of current gain in linear decibels or linear step intervals. Smaller step sizes can be obtained by programming a current source within the step intervals.

Abstract: I describe and claim an improved digital-to-analog conversion device and method. The device comprises a current supply circuit to generate a plurality of control currents responsive to a plurality of digital signals. An input voltage generating circuit is adapted to generate a plurality of input voltages responsive to the digital signals and the control currents. And a plurality of operational amplifiers is adapted to output a plurality of analog signals responsive to the input voltages.

Abstract: An accurate high current mirror circuit produces a mirrored current that matches an input current to produce an accuracy at the output of a subsequent stage of amplification of greater than 0.01%. A plurality of transistor devices are arranged in a symmetrical configuration and divided into two groups. The transistors in each of the two groups are connected in parallel to produce a high mirror current from a high input current. A distribution of a source voltage produces the same source voltage at each of the plurality of transistors. An input current metallization and a mirror current metallization are formed within the symmetrical configuration to have a same value of impedance. A plurality of P-channel transistors within the current mirror circuit control a voltage of a point on the input metallization to be the same as a reference voltage, thus causing the mirror current to be referenced around the reference voltage.