Abstract: A video DAC for driving video displays with reduced power dissipation is presented. This is accomplished using a dual driver circuit connected to a current mirror, the dual driver comprising a strong driver and a weak driver. The dual driver permits switching current between the video load and a dummy load. The current to the dummy load is disabled during periods when the video signal remains steady for a predetermined period of time. The dual driver, using the weak driver, disables the current to the dummy load during video blanking and synchronization periods. This scheme substantially reduces the power dissipation in the DAC.

Abstract: A sign bit integrator and method for generating a signal to correct an offset in a signal processing system that can distort the output from the system. A charge pulse is generated when the sign of a input signal is sampled in order to provide an offset correction signal with a polarity opposite that of offsets in the system. The charge pulse is provided to a pair of transistors whose size ratio sets the magnitude of the charge pulse. The polarity of the charge pulse is set responsive to a sign bit in the input signal. An integrator capacitor provides the offset correction signal to the signal processing system. A third transistor may be switchably substituted for one of the pair of transistors to change the ratio of sizes and thus change the magnitude of the charge pulse to thereby change the speed with which the offset correction is made. The sign bit integrator and method may be used to correct distortion in a voice signal in a telephone system.

Abstract: A high speed low power digital-to-analog (D/A) converter (DAC) includes a plurality of least significant bit (LSB) cells that collectively define a total output of the DAC. Each LSB cell includes a differential current driver that has reduced capacitive loading due to a cascode structure of the current driver wherein transistors are biased to desired levels and current sources are switched on and off to control the differential output signal.

Abstract: A high speed digital-to-analog (D/A) converter (DAC) includes a plurality of least significant bit (LSB) cells that collectively define a total output of the DAC. Each LSB cell includes a differential current driver that has reduced capacitive loading due to a cascode structure of the current driver wherein transistors are biased to desired levels and current sources are switched on and off to control the differential output signal.

Abstract: An analog input signal current is split into a tree form. Hierarchical subtraction process for subtracting a comparison reference current is performed in each current path in the tree structure. At the final stage of the tree structure, the current is compared with a reference current to obtain a digital signal on the basis of results of comparison.

Abstract: A digitally controlled calibration circuit for a DAC includes a primary DAC having a first reference current input, a second input for receiving a digital signal representative of the DAC conversion factor, and an output for providing the analog signal; a secondary calibration DAC has associated with it a reference network connected to a first input of the secondary DAC for conducting a reference current, and a device for connecting the output of the secondary DAC to the reference network, the second DAC includes a second input for receiving a digital signal for adjusting the output of the secondary DAC fed back to the reference network for adjusting the reference current; and a device for interconnecting the reference current with the first reference current input of the primary DAC for digitally controlling the reference current input of the primary DAC for digitally controlling the reference current to that primary DAC and digitally effecting calibration of the primary DAC.

Abstract: A digital to analog converter and method for conversion is provided that includes an R-2R resistor ladder network formed with a plurality of current bit switches in a GaAs HI.sup.2 L integrated circuit. Each bit switch and R-2R node in the ladder network is associated with a corresponding bit position in the binary signal input to the converter. An arrangement of bipolar transistors (Q1, Q4) and diodes (D2-D3) is included in each bit switch (100) that steers current through one of two alternate paths, based on the logic state of the binary input signal (i e., "high" or "low" state). For one logic state of the binary input signal, current flows through the switch from the output of the digital to analog converter (110). For the alternate signal state, current flow from the output of the digital to analog converter is blocked. Therefore, each bit switch (100) operates as a single-pole-double-throw current mode switch under the control of the binary input signal (Ai).

Abstract: A current duplicator (10) is provided for receiving a calibration current and providing an output current to a load (10). Current duplicator (10) includes a transconductor (14) having a differentially coupled input with a parasitic capacitance for storing a differential voltage during a supply period. This parasitic capacitance also converts a difference current into the voltage during a feedback period. The difference current is equal to the difference between the output current and the calibration current. Transconductor (14) converts the voltage into the output current. The current duplicator also includes a first switch network for coupling the output current to the load (12) during the supply period. The output current remains within a predetermined amount from the calibration current during the supply period. A second switch network feeds back the difference current to the input during the feedback period at least until the output current becomes substantially equal to the calibration current.

Abstract: A ground translation circuit in a transmitter of a transceiver of a data transmission network for transferring symbol information contained in analog pulses from circuits referenced to logic signal power to circuits referenced to an independent DC voltage ground return for transmission over a bus. Complementary ground translation circuits in a receiver of the transceiver for transferring the analog pulses referenced with respect to the independent DC ground return back to circuits referenced to logic signal power.

Abstract: A multiplying digital-to-analogue converter of the kind in which digitally weighted currents proportional to a voltage applied to an analogue input are generated at respective outputs of a current mirror arrangement. These currents are switched to an output in accordance with the value of a digital signal applied to a digital input. In order for the converter to accommodate an analogue input voltage of either polarity relative to ground and generate corresponding output currents, a bias current is applied to the current mirror input from a current source. This results in digitally weighted bias currents being generated at the current mirror outputs. These bias currents are offset by corresponding bias currents generated at respective outputs of a second current mirror arrangement.

Abstract: A digital to analog converter (DAC) incorporates a novel subranging voltage output DAC that delivers high multiplying bandwidth while consuming low power and requires small silicon area. The higher order digital input bits (MSBS) select a voltage range (VMSB) from a first resistor divider DAC network. The VMSB is then applied to the input of a small high speed low power differential input single ended output LSB programmable attenuator amplifier. Transistor follower devices effectively buffer the MSB section to the LSB section and increase bandwidth and speed of operation as well as permitting multichannel sharing of a single precision MSB voltage divider network.

Abstract: A multiplying digital-to-analog converter which includes an R-2R chain network is characterized in that, for partial or complete potential equalization, the chain network for an n-bit-wide digital signal applied to the converter comprises (n+m) connection points, where n,m are natural integers greater than zero, the connection point (n+m) produces the output signal of the converter. A first current mirror is provided which produces a constant first current that can be switched to the individual connection points (1+m) to (n+m). The least significant bit of the digital signal is allocated to the connection point (1+m) and the most significant bit to the connection point (n+m) and the first current is switched only to those connection points whose allocated bit has a first state.

Abstract: A semiconductor integrated circuit device includes a bias generating circuit having an operational amplifier connected to receive an input voltage at its inverting input terminal to produce a gate voltage. A field transistor has its gate connected to receive the gate voltage from the operational amplifier and its drain connected to a resistor and to an noninverting input terminal of the operational amplifer. A field effect transistor has its gate connected to receive the gate voltage from the operational amplifier to produce a current corresponding to the input voltage. One group of current source is responsive to an output voltage of the bias generating circuit to produce a plurality of currents of an equal magnitude and one switching circuit is responsive to an input digital value to selectively output the currents from the group of current sources to its common output.

Abstract: A multiplying digital-to-analog converter for multiplying a bipolar input current by a digital word A having N bits a.sub.i including a current adder for adding a constant current to the bipolar input current to produce a unipolar current, a first current mirror responsive to the unipolar current for providing N binary weighted versions of the unipolar current, a second current mirror for providing binary weighted versions of the constant current, N current selection circuits respectively controlled the N bits a.sub.

Abstract: A digital-to-analog converter which has an input terminal for receiving first and second digital signals and a reference voltage generating circuit for establishing a reference voltage at a control terminal of a reference voltage transistor. The digital-to-analog converter also includes first and second current sources which each include a current source transistor having a control terminal connected to the control terminal of the voltage reference transistor. A first switch connected in the conduction path of the first current source transistor selectively allows current to flow to the output terminal and a second switch connected in the conduction path of the second current source transistor selectively allows a second current to flow to the output terminal.

Abstract: A digital-to-analog converter for use in a timing control loop. The converter includes a plurality of cells, each activated in response to a timing loop control signal. The converter also includes a resistive current mirror, with a first resistance R1, providing a reference curent which is mirrored in each cell by a current source FET. Each cell is constructed to switch the current from its current source FET through an output FET when a respective control bit provided to the cell is positive. Otherwise, the current is diverted through a sink FET. All of the cell output FETs are tied to a single resistance R2 which collects the currents of the active cells and provides the AC output of the converter. The converter's output is related only to the ratio R2/R1, thereby decoupling process, temperature, and voltage effects from the output of the converter.

Abstract: A digital-to-analog converter which includes a digital-to-analog conversion circuit of the current output type, a current-to-voltage conversion circuit receptive of an analog current produced form the digital-to-analog conversion circuit in correspondence to an input digital signal value, for converting the analog current to a voltage and producing it at the output thereof in an output stage of the converter, a first drive circuit for driving the digital-to-analog conversion circuit with constant current, and a second drive circuit which is controlled by the first drive circuit to drive the current-to-voltage conversion circuit with constant current, thereby it being made possible to arrange a plurality of digital-to-analog converters in a simple structure.

Abstract: An operational amplifier is provided and includes at least two input terminals of one polarity and another input terminal of the opposite polarity. The amplifier includes an amplifying portion which comprises a differential section for receiving input signals applied to the input terminals. The differential section includes at least two differential amplifiers which form difference signals from the input signals. A summing section receives the difference signals and forms a sum result therefrom. A multiplying section provides an amplification gain to the sum result to form an output signal of desired gain. The amplifier is also provided with a feedback for applying an input signal to one of the input terminals, the output signal. The amplifier can be configured to provide amplification gains of 2, 1/2, -1 and 1.

Abstract: An arrangement of switches and resistors for switching current into the summing node of an integrator uses a pair of switches for each resistor. Each resistor is connected at one end to a reference voltage. The other end of the resistor is connected to a first switch, which is in turn connected to the summing node. A second switch is connected between ground and the junction of the resistor and the first switch. One or the other of the two switches will always be on. When the first switch is on and the second one is off a current will flow from the reference voltage, through the resistor and into the summing node. When the first switch is off and the second one is on essentially the same current will flow from the reference voltage, through the resistor and into ground. The current will be nearly the same, since the virtual ground of the integrator approximates actual ground.

Abstract: A differential analog input signal is level-shifted and converted to single-ended form. Its average value is compared to the midpoint of a set of reference voltages. A control signal proportional to the average value forces the average of the single-ended signal toward the midpoint voltage. The single-ended signal is converted to uncoded digital form by a parallel comparator bank, and is then converted to coded digital form.

Abstract: A digital-to-analog converter which comprisesan input terminal (1) for receiving a digital input signal,an output terminal (2) for supplying the analog output signal,a current source circuit (3) having N current sources (I.sub.1 to I.sub.N) for generating N currents of substantially equal current intensity at N outputs (3.1 to 3N), anda combination circuit (4) having N inputs (4.1 to 4N) coupled to the N outputs of the current source circuit and an input (6) for receiving the digital input signal and an output (7).In order to convert a digital signal D which is presented to the input terminal (1) during a time interval (Ta), the time interval is sub-divided into at least two sub-intervals (T.sub.d1, T.sub.d2).

Abstract: A D to A converter comprising a series of stages each including a current mirror having an input and an output transistor (Q1 and Q3) and a current adjusting transistor (Q2, Q4) connected in parallel with each input and output transistor for adjusting the output current from the current mirror as a function of the operating states of the current adjusting transistors. The operating state of each current adjusting transistor is controlled by a digital signal applied to a switch (Q2S, Q2S') connected to the gate of each current adjusting transistor. Each stage also includes a control circuit (Q1C, Q3C) for maintaining equal the drain voltages of its input and output transistors whereby the current changes introduced in the output current of the converter stage are functions of the relative geometric sizes of the input, output and current adjusting transistors comprising the converter stage.

Abstract: A substantially constant current is divided between two lines in accordance with the relative values of an input voltage and a reference voltage respectively introduced to such lines. The currents through the first and second lines respectively charge first and second capacitances. The charges in the first and second capacitances respectively control the magnitudes of the currents flowing through first and second control members to charge the first and second capacitances. The control members are interconnected so that any difference between the flow of current through the control members and the associated capacitances between magnified. When the charge in an individual one of the capacitances reaches a particular value, a signal on an output terminal associated with the other capacitance changes from the first magnitude to a second magnitude. During this time, the signal associated with the first capacitance remains at substantially the first magnitude.

Abstract: A digital to analog converter comprises a plurality of resistors coupled in series, having first and second nodes at the repsective ends of the plurality of resistors coupled in series and a plurality of nodes, one each between each of the plurality of resistors. A multiplexing circuit is coupled to the first and second nodes and the plurality of nodes, for selecting the voltage on one of the first and second nodes and the plurality of nodes in response to a digital input signal and providing the result as an analog output signal. An input circuit is coupled to the first and second nodes for adjusting the voltage level at both the first and second nodes in response to the digital input signal, wherein the voltage difference between the first and second nodes remains substantially the same and the current through each of the resistors remains substantially the same.

Abstract: A parallel analog to digital converter and a method of processing at least two independnet signals therein are disclosed in accordance with the teachings of the present invention. The analog to digital converter has an improved sample and hold stage which, in addition to quantizing the analog signals, also multiplexes them. The sample and hold stage comprises at least two differential amplifier circuits, a latch stage, and a timing stage. Each differential amplifier circuit converts one analog input by comparing it to a reference voltage. The discrete output of the differential amplifier circuit is stored in the latch stage and outputted to an encoder. The timing circuit stage first selects one differential amplifier circuit to output its discrete signal, and then selects the latch stage to output its stored results. By sequencing through each differential amplifier circuit, the present invention effectively multiplexes the analog inputs.