Abstract: There is provided a digital to an analog converter (DAC) comprising a current source, a first logic circuit, wherein the first logic circuit receives a first switching signal and a low-power mode signal, a first switch controlled by the first logic circuit, wherein the first switch selectively couples the current source to a ground in response to a signal from the first logic circuit, and a second switch controlled by a second switching signal, wherein the second switch selectively couples the current source to a load in response to the second switching signal. The first switching signal and the second switching signal may be complementary and are based on a digital signal that is being converted into an analog signal. The low-power mode signal is provided to selectively switch the DAC into a lower power consumption mode.

Abstract: A first current mirror circuit that operates at the time of a rise in a first signal is connected to a current source, a second current mirror circuit that operates at the time of a rise in the first signal is connected to the first current mirror circuit, and a third current mirror circuit that operates at the time of a rise in a second signal is respectively connected to the current source and the point of connection between the first current mirror circuit and the second current mirror circuit. A pulse generation circuit for generating first and second signals from an external signal is provided. The second signal rises in sync with the first signal, and falls before the first signal.

Abstract: A data line drive circuit is equipped with a single line driver 300 and a gate voltage generation circuit 400. The single line driver 300 is constructed such that N groups (where N is an integer 2 or larger) of series connections of drive transistors 21 to 28 and switching transistors 81 to 88 are connected in parallel. The gate voltage generation circuit 400 includes two transistors 71 and 72 constituting a current mirror circuit, a drive transistor 73, and a constant voltage generation transistor 31. The range of an output current Iout can be controlled by changing any of the design values of the parameters including: relative values Ka and Kb of the gain coefficient for the transistors 31 and 32, the source voltage VDREF of the gate voltage generation circuit 400, and the gate signal VRIN of the drive transistor 73.

Abstract: Aspects of the invention can provide a digital-to-analog converting circuit capable of, after converting digital data into an analog current, correcting the current value based on digital current correction data without any complex processing. The exemplary digital-to-analog converting circuit can include a first digital-to-analog converting circuit portion and a second digital-to-analog converting circuit portion. First digital data (image data) can input to the first digital-to-analog converting circuit portion, and second digital data (current correction data) can input to the second digital-to-analog converting circuit portion. After the first digital-to-analog converting circuit portion converts the image data into a first analog current, the second digital-to-analog converting circuit portion can correct the first analog current based on the current correction data, and outputs the corrected current as a second analog current.

Abstract: In a D/A converter circuit including a current mirror circuit constructed with an input side transistor circuit and an output side transistor circuit, the input side transistor circuit comprises a series circuit of a first MOS transistor and a second MOS transistor and a first switch circuit connected in parallel to the first MOS transistor. Gates of the first and second MOS transistors are connected commonly and a source of either one of the first and second MOS transistors is connected to a drain of the other of the first and second MOS transistors and the second MOS transistor has a gate length shorter than a gate length of the first MOS transistor.

Abstract: The data-line driver circuit receives data currents from an external signal source and drives the pixel group of electro-luminescence display device. The data-line driver circuit has a first circuit group, a second circuit group and a shift register. The shift register controls the first circuit group to receive the data currents and controls the second circuit group to duplicate the data currents and then send them to the pixel group.

Abstract: Digital-to-analog converter circuits can include independently sized first and second current source transistors coupled to respective pluralities of first and second current provider transistors in current mirror configurations. The first and second current provider transistors can be sized proportionally to the first and second current source transistors respectively.

Abstract: A display driver comprises second and third MOSFETs for supplying reference currents equal to each other, a first current-input MOSET connected to the second MOSFET, a second current-input MOSFET connected to the third MOSFET, a plurality of mirroring devices which are placed between the first current-input MOSFET and the second current-input MOSFET and to which a current fed to each of the first and second current-input MOSFETs is distributed, and current adding means for changing the output current value by adding currents produced in the plurality of mirroring devices.

Abstract: Improved digital to analog converter (DAC) circuitry incorporating the ability to utilize a single DAC to generate either voltage or current outputs, and the ability to digitally adjust the gain and offset. Previous digital to analog circuitry has been limited to a single type of analog output per DAC and to the use of external precision resistors to set the gain and offset for a single DAC, or a group of DACs. By utilizing the same on-chip circuitry to supply both types of outputs, chip area, power consumption and cost is reduced while offering more flexibility to the customer. The ability to digitally adjust the gain and offset for a group of DACs eliminates the cost of external resistors, lowers the board area, and lowers the assembly cost for the end product. In addition, since gain and offset can be adjusted dynamically, maximum flexibility is provided to the customer.

Abstract: A method and apparatus for calibrating an electronic circuit which required scaled matching of some or all of its electronic components with nonvolatile programmably trimmable parameter sources (current, voltage, resistance, capacitance) is carried out in a top-down (highest order bit first, lowest order bit last) fashion without an analog division step. The method and apparatus are applicable, for example, to current-steering digital-to-analog converters (DACs), voltage-controlled oscillators (VCOs), voltage-steering DACs, and the like. In each of these applications the method and apparatus is used to match successive device outputs according to a desired scale factor, proceeding top-down from large output devices to smaller output devices, thereby successively shrinking the cross-device errors which accrue during the matching process.

Abstract: An analog-to-digital converter including analog-to-digital converting units connected in serial. The current comparator includes a current input terminal to receive a sampling current, a reference current input terminal to receive a reference current and a bit output terminal for outputting a bit signal. The current operation circuit includes a current output terminal for outputting a compared current according to the sampling current and the reference current. The operation controlling terminal selects the compared current according to the bit signal. The controlling terminal receives a clock signal to latch the bit signal. The analog-to-digital converting units output the bit signals in sequence in a period of the clock signal.

Abstract: A current-steering/reproducing digital-to-analog current converting circuit includes a digital-to-analog current converter for converting a digital signal into analog current signal, a current-storing/reproducing module, and a control circuit. The current-storing/reproducing module is used to store a predetermined voltage for conducting the analog current signal in a transforming/storing status and to conduct a reproducing current to a data line in a reproducing/sustaining status. The control circuit is electrically connected between the digital-to-analog current converting device and the current-storing/reproducing module for providing a switch between the transforming/storing status and the reproducing/sustaining status.

Abstract: A multi-channel circuit (1) comprising three channels (CH1 to CH3), each of which is provided with a current steering DAC (5) in which crosstalk between the respective DACs (5) is minimized. Each DAC (5) comprises binary scaled current source devices (Qs1 to Qsn) and current steering switches (Qt1 and Qf1 to Qtn to Qfn) for steering currents from the current source devices (Qs1 to Qsn) to summing nodes (11,12) across which an analogue signal is developed corresponding to a digital input word. Cascode devices (Qc1 to Qcn) are provided between the respective current source devices Qs1 to Qsn and the corresponding current steering switches (Qt1 and Qf1 to Qtn and Qfn) for preventing capacitive feedthrough of voltage swings on the current steering switches (Qt1 and Qf1 to Qtn and Qfn) for minimizing crosstalk between the DACs (5).

Abstract: The disclosed A/D conversion system is designed to signal the beginning or the impending beginning of an A/D conversion and/or to request the implementation of an A/D conversion from another A/D converter. As a result, it is possible to have a plurality of A/D converters work absolutely time-synchronously with minimal outlay.

Abstract: A voltage margin setting interface circuit has a single input pin, and is configured to program the slew rate and polarity direction of variation of the operation of a digital-to-analog converter, such as may be used to set a reference voltage level, for application to an error amplifier of a voltage regulator circuit of the power supply of a personal computer. A DAC clocking control circuit is coupled to an output port, and to respective DAC increment and decrement ports, and is operative to control the magnitude of output current, and to assert an output signal at one of the increment and decrement ports, in accordance with a prescribed relationship between the voltage and upper and lower ranges of the input voltage relative to its middle value.

Abstract: A data driver for driving pixels in an active matrix organic LED (AMOLED) is provided the data driver includes a plurality of converters configured to convert to analog current signal digital voltage signals in order to drive the pixels to emit light. Each converter has a plurality of current mirror devices configured to generate mirrored current signals by inputting two control signals. Meanwhile, the mirrored current signals can maintain their preciseness even if deviation of the characteristics of the transistors implanted within the current mirror devices occurs during fabricating.

Abstract: A data driver for driving pixels in an active matrix organic LED (AMOLED) is provided. The data driver includes a plurality of converters configured to convert to analog current signals from digital voltage signals in order to drive the pixels to emit light. Each converter has a plurality of current mirror devices configured to generate mirrored current signals by inputting two control signals. Meanwhile, the mirrored current signals can maintain their preciseness even if deviation of the characteristics of the transistors implanted within the current mirror devices occurs during fabricating.

Abstract: A shunt-shunt feedback current to voltage converter (60) including a compensating current (22) provided to the output of the amplifier (12) which mirrors the input current (14) advantageously removing the loading effects of the feedback resistor (Rf) to the amplifier (12). A current steering DAC (40) is utilized in conjunction with a plurality of polarity control switches (62) to provide either a source current or a sink current to the amplifier input, and a complementary sink current or source current, respectively, to the output of the amplifier such that the amplifier (12) does not provide any current to the feedback resistor. Thus, DC gain of the amplifier is maintained. The current steering DAC (40) provides a matched source current and sink current to achieve this architecture.

Abstract: A current steered digital to analog converter (DAC) circuit includes a reference input transistor, a plurality of current steered current sources each coupled to the reference input transistor and configured to provide a combined current source output and an output current mirror having an input coupled to the combined current source output. The output current mirror provides current gain to enable the DAC circuit to provide the required output current magnitude, while at the same time, enabling the DAC itself to operate with a smaller reference current into the DAC. The output current mirror may advantageously be either a regulated cascode current mirror or a high-swing cascode current mirror.

Abstract: Mulitplying digital-to-analog converters (MDACs) are provided that reduce signal distortion without significantly raising current demand. These goals are achieved with input structures that lower input impedances and enhance the driving of nonlinear capacitances that are generally presented by the DAC portion of these devices.

Abstract: Circuitry that generates an interface signal between a first and a second integrated circuit (IC). The circuitry includes a reference circuit that provides a reference signal, an interface circuit, and a circuit element. The interface circuit is implemented on the first IC, operatively couples to the reference circuit, receives the reference signal and a data input, and generates the interface signal. The circuit element is implemented on the second IC, operatively couples to the control circuit, receives the interface signal, and provides an output signal. The reference signal can be a voltage or a current signal, and can be generated in the first or second IC. The interface circuit can be implemented with a current mirror coupled to a switch array, and can be oversampled to ease the filtering requirement. The interface signal can be a differential current signal having multiple (e.g., four, eight, or more) bits of resolution. The circuit element can be, for example, a VGA, a modulator, or other circuits.

Abstract: A current correction circuit 500 eliminates beta mismatches between a thermometer encoded segment 102 and a R-2R ladder segment 106 of a current steering digital-to-analog converter 100. The circuit 500 consists of three replica MSB unit current sources, I1, I2 and I3. The replica current I1 acts as a replica to a cascode device 206 of the MSB unit 200 of the current steering DAC 100. The replica current I2 replicates an effective base current equal to the total base current in the R-2R ladder circuit portion 300 of the current steering DAC 100. The replica current I3 replicates the total base current of the L output switches 310 in the LSB segment 106 of the current steering DAC 100. A high impedance summing node 506 produces a correction current ICOR=I1−(I2+I3). This current is equal to the current difference between an MSB unit 200 and the LSB segment 106.

Abstract: A multi-channel circuit (1) comprising three channels (CH1 to CH3), each of which is provided with a current steering DAC (5) in which crosstalk between the respective DACs (5) is minimised. Each DAC (5) comprises binary scaled current source devices (Qs1 to Qsn) and current steering switches (Qt1 and Qf1 to Qtn to Qfn) for steering currents from the current source devices (Qs1 to Qsn) to summing nodes (11,12) across which an analogue signal is developed corresponding to a digital input word. Cascode devices (Qc1 to Qcn) are provided between the respective current source devices Qs1 to Qsn and the corresponding current steering switches (Qt1 and Qf1 to Qtn and Qfn) for preventing capacitive feedthrough of voltage swings on the current steering switches (Qt1 and Qf1 to Qtn and Qfn) for minimising crosstalk between the DACs (5).

Abstract: In a sigma-delta modulator the feedback circuit (4, 5) has an adjustable feedback factor controlled by an adjusting member (6) for adjusting the feedback factor of the feedback circuit.

Abstract: A segmented digital-to-analog converter circuit employs a tri-level technique to provide an output current in response to a bit code. DAC slice circuits are activated in unary fashion in response to their respective control signal, which are provided by a decoder circuit in response to the high-order bits. Each DAC slice circuit provides a binary weighted current to a summing node in response to the middle-order bits. One of the DAC slice circuits is selected to direct a portion of its total current to the input of a DAC_LOW circuit, where the input current is divided to provide a divided current to the summing node in response to the low-order bits. At certain code transitions a different DAC slice circuit is selected to provide the input current, and the previously selected DAC slice circuit redirects its total current to the summing node such that differential non-linearity errors are minimized.

Abstract: Power-up and power-down transient suppression are provided for an audio digital-to-analog converter with a single ended output to prevent annoying pops which accompany switching an audio system on and off. Power-up suppression is achieved by clamping an output signal to ground, driving the audio channel to ground, releasing the clamp and driving the audio channel gradually to its quiescent (zero signal) value. Power-down suppression is provided by using a positive feedback amplifier to accelerate current drain initiated by a constant current source used to bleed off the charge on output capacitor. The audio digital-to-analog converter sets operational mode based on ratios of a master clock to a channel selection clock. The techniques disclosed apply readily to the outputs received from CDs, CD-ROMs, DAT and other digital recording media.

Abstract: A digital-to-analog converter includes a number of current steering cells. In each current steering cell, a current source is biased by a differential amplifier to provide a high output impedance. The high output impedance in the current steering cell allows the digital-to-analog converter to operate under low supply voltage conditions.

Abstract: A mixed signal CODEC including an improved sigma-delta ADC (20) which limits input signals into a switched capacitor configuration and avoids adding circuit overhead in the signal path is disclosed herein. Additionally, it avoids overshoot and settling problems. This sigma-delta analog-to-digital converter (20), having an input signal and an output signal, includes a switch (sw1), a clipping circuit (21), and a known sigma-delta ADC (34). It solves the clipping signal problem by limiting the signal right at the input of the sigma-delta ADC (34). The clipping circuit (21) couples to the switch (sw1) and the sigma-delta ADC (34) for switching the voltage applied to the sigma-delta ADC between the input signal (vin) and at least one threshold voltage (Vn and Vp).

Abstract: An electron beam analog to digital converter wherein an input signal to be quantized is applied to the deflection circuitry of an electron beam generation device where the electron beam is made to sweep an angle proportional to the amplitude of the input signal in a first orthogonal direction (horizontal) across a linear array of detector elements which generates an output signal at the angle of deflection. A sinusoidal reference signal is simultaneously applied to a second set of deflection plates which causes electron beam to sweep in a second orthogonal direction (vertical) whereupon the deflected electron beam periodically sweeps across the detector array and a time sample of the output voltage is generated during a crossover interval. The detection voltage is then converted to an output signal having a binary value corresponding to the amplitude of the analog input signal.

Abstract: A digital-to-analog conversion circuit including a plurality of unit current output cells (1) arranged in a matrix. Each of the current output cells (1) includes a unit current source (11) having a power supply input and a current output, and a selecting switch (12) connected to the current output and having two switching output terminals. The circuit further includes at least one ½ and/or ¼ weighted current output cell (2) disposed on a row in the matrix, and at least one ½ and/or ¼ supplementary current source (8) disposed on a desired row so that the total current consumption of the unit, weighted and supplementary current sources on each row is substantially the same. A decoder responds to a digital signal to control the switching of the selecting switches one by one as the digital signal gradually increases.

Abstract: An electrooptical scanning analog-to-digital converter for converting an analog voltage signal from a source to its corresponding digital equivalent in accordance with the invention includes a laser providing a beam having an initial position and multiple deflected positions. The voltage signal forms a deflection input to the laser. A first voltage of the voltage signal provides for the initial position of the beam and multiple other voltages of the voltage signal provide for the plurality of deflected positions of the beam. The invention also includes a phototarget array that has a first phototarget mapped to the first voltage of the voltage signal and multiple incremental phototargets each mapped to one of the multiple other voltages of the voltage signal. The first phototarget and the multiple incremental phototargets are arranged along an axis, which may be in one implementation substantially perpendicular to the initial position of the beam.

Abstract: Encoding and decoding systems and methods for digital data in 24 bit sequences. An encoder generates state variables as a function of four or fewer bits of the 24 bit sequence, and encodes the sequence into 11 and 14 bit codewords. After transmission, the 11 bit and 14 bit codewords are decoded using recovered state variables. The encoding places a run length limit (RLL) of k=7 on a 25 bit codeword comprised of the 11 and 14 bit codewords to limit runs of zeros. Each of the 11 bit and 14 bit codewords are preferably also encoded with a run length limit of interleaved bits is i=7. The encoding and decoding systems and methods can be applied to a magnetic disc drive.

Abstract: Power-up and power-down transient suppression are provided for an audio digital-to-analog converter with a single ended output to prevent annoying pops which accompany switching an audio system on and off. Power-up suppression is achieved by clamping an output signal to ground, driving the audio channel to ground, releasing the clamp and driving the audio channel gradually to its quiescent (zero signal) value. Power-down suppression is provided by using a positive feedback amplifier to accelerate current drain initiated by a constant current source used to bleed off the charge on output capacitor. The audio digital-to-analog converter sets operational mode based on ratios of a master clock to a channel selection clock.

Abstract: An analog-to-digital or digital-to-analog system contains a converter (706). The converter is supplied with a clock signal (CLK1) at a frequency fs derived from a crystal of a frequency fs/N. The frequency fs is derived from the fs/N crystal frequency by using an edge-triggered clock multiplier 705 which multiplies the crystal frequency by the factor N. The result is a low-cost clock solution that incorporates clock jitter around a localized frequency of fs/N. Sigma delta processing circuitry (702) is then used to place a null (e.g., low gain area) in the quantization noise at the same frequency where clock jitter noise is high in order to cancel the adverse cumulative effects of these two types of noise.

Abstract: A sense-amplifier circuit comprising a plurality of sub-sense-amplifiers corresponding to respective reference potentials can operate fast when used for a multivalued information memory. The sense amplifier circuit is composed of sub-sense-amplifiers having different polarities according to corresponding reference potentials: a sub-sense-amplifier SN3 having the highest reference potential is of N (polarity) type and a sub-sense-amplifier SP1 having the lowest reference potential is of P (polarity) type. All sub-sense-amplifiers can operate according to improved characteristics assuring a reduced access time.

Abstract: This invention includes a current output sensor, and a current AD conversion means which is connected to the output side of the current output sensor and has a current mirror circuit arranged on the input side of a comparator in order to directly A/D-convert an output from the current output sensor. A signal can be stably processed with a small circuit scale and low current consumption.

Abstract: An operational amplifier with an offset compensation function and a D/A converter employing the same for eliminating an offset voltage above a certain limit. In the operational amplifier, a current mirror is provided between a high voltage line and first and second nodes, and a current sink is provided between a third node and a low voltage line. A first transistor controls a current amount flowing from the first node to the third node, and a second transistor controls a current amount flowing the second node to the third node. An amplifier is connected between the second node and an output line to amplify a voltage signal of the output line. A mirror controller responds to the voltage signal from the output line to control the second transistor, and a sink controller responds to the voltage signal from the output line to control the current sink.

Abstract: A multi-channel D/A converter is formed with a plurality of converter units, each having one single input transistor and a plurality of output transistors which together form current mirrors. Mutually corresponding ones of these output transistors of different ones of the converter units, which are switched on and off together, are disposed adjacently and connected together to a trunk power supply line such that the parasitic resistances through the conductive lines connected to the output transistors are alike and the conversion characteristics of the individual converter units also become alike. One common input transistor may be shared by all of the converter units for further improving the conversion characteristic.

Abstract: A D/A converter has one single input transistor used in common with a plurality of output transistors to together form current mirrors, and a decoder serves to sequentially select the current mirrors in response to a digital input, causing to generate a corresponding analog output from currents from selected ones of the current mirrors. The commonly used input transistor is centrally located with respect to the current mirrors such that the difference between the maximum and minimum distances, or that between the maximum and minimum parasitic resistances, between the input transistor used in common and the output transistors is reduced and the conversion characteristic can be improved.

Abstract: Power control circuitry is provided in an analog-to-digital converter (1) having a CDAC array (2) coupled to an analog input signal, a comparator (3), and a successive approximation register circuit (5). The power control circuitry includes a bias control circuit (4) responsive to a powerdown signal and associated wakeup signal to produce a bias control signal (V.sub.BIAS). The bias control circuit includes a controllable current mirror circuit (10) which produces a first voltage (V.sub.C) on a first conductor (13) when the powerdown signal is at a first level to allow operation of the comparator in conjunction with the CDAC array and the successive approximation register circuit. The bias control circuit also includes a wakeup circuit (20) which precharges the first conductor (13) to a predetermined bias voltage (V.sub.C ') that is close in value to the first voltage (V.sub.C) in response to occurrence of the first level of the powerdown signal. The bias control signal V.sub.

Abstract: An improved current steering cell for a DAC which eliminates the need for an inverter reduces the noise at the common mode. The cell includes a first and a second current steering MOS transistor of a first polarity type, each having a gate and a pair of current passing terminals. The cell has an input terminal for receiving digital input signals coupled to the gate of the first of the pair of current steering transistors, and a common mode node for receiving an input current coupled to the same one of the pair of current passing terminals of each current steering MOS transistor. The current output terminal of the cell is coupled to the other of the pair of current passing terminals of the first of the current steering MOS transistors.

Abstract: A metal-oxide-semiconductor digital-to-analog converter unit includes a multiplicity of current mirror components 20 in a symmetric array, a resistance network activated by voltage sources providing weighted biasing potentials for the current mirror components, and an electrical coupling of the current mirror components to compensate for variations physical properties across converter unit substrate area. The current mirror components 20 include a current steering portion 21.sub.0 -21.sub.N-1 and 25.sub.0 -25.sub.N-1 coupled to an annular bias transistor 22. The resulting digital-to-analog converter has improved performance characteristics when compared to previously implemented digital-to-analog converter units.

Abstract: A digital to analog converter that includes circuitry that converts sequences of positive and negative digital data samples into electrical currents and current mirror circuitry that generates an analog waveform by combining and amplifying the electrical currents.

Abstract: A multiplying digital-to-analog converter produces first and second output currents that have a magnitude difference equal to a gain value multiplied by a magnitude difference between first and second input currents. The multiplying digital-to-analog converter has first and second input nodes for carrying the first and second input currents and first and second output nodes for carrying the first and second output currents. A first input transistor has a first terminal coupled to the first input node, a second terminal with voltage that increases with increases in the first input current, and a third terminal for carrying a first input bias current. A second input transistor has a first terminal coupled to the second input node, a second terminal with a voltage that increases with increases in the second input current, and a third terminal for carrying a second input bias current.

Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.

Abstract: A pulse width modulation analog to digital converter can accommodate both wide band AC analog input signals and DC analog input signals. If the frequency of the input signal is much higher than the conversion rate of the PWM analog to digital converter, then the output digital pulse is of constant width versus the analog input signal amplitude. If the frequency of the analog input signal is lower than the conversion rate, then the output digital signal is a train of variable width pulses whose width tracks the amplitude of the analog input signal.

Abstract: A digital-to-analog converter circuit is configured by a digital-to-analog converter receiving data of m bits (where `m` is an integer arbitrarily selected), a voltage-follower circuit containing an operational amplifier, a current-mirror circuit and a current-switching circuit. Herein, the data of m bits are extended by bits b.sub.H and b.sub.L in low-order positions thereof, wherein b.sub.H is placed in a higher order than b.sub.L. A noninverting input of the operational amplifier is connected to an output of the digital-to-analog converter; and a feedback resistor is connected between an inverting input and an output of the operational amplifier. The current-mirror circuit, using MOS transistors, provides two constant currents I.sub.H and I.sub.L in response to the bits b.sub.H and b.sub.L respectively, wherein a relationship between the constant currents I.sub.H and I.sub.L is defined by an equation of I.sub.H =2.times.I.sub.L.

Abstract: A digital to analog converter that includes circuitry that converts sequences of positive and negative digital data samples into electrical currents and current mirror circuitry that generates an analog waveform by combining and amplifying the electrical currents.

Abstract: A flash A/D converter includes a plurality of master comparators for comparing a plurality of reference voltages and an input analog signal to absorb a current with a constant value from a non-inverted output or inverted output of each master comparator, a plurality of constant current sources, a plurality of load resistors and a plurality of slave comparators for outputting desired digital signals. The constant current value of one of the constant current sources coupled to a signal line coupled to the input of the slave comparator of a lower bit side is set to a value larger than that of one of the constant current sources coupled to a signal line coupled to the input of the slave comparator of a higher bit side. Thereby, it is possible to provide a flash A/D converter which has a low power consumption and a high speed.

Abstract: An analog memory unit that can be implemented, at least in part, on an application specific integrated circuit (ASIC), utilizes at least the ASIC arithmetic logic unit (ALU) to enhance performance and to generate and store an accurate measure of power line thermal status. The memory unit includes an analog-to-digital (A/D) converter for converting an input analog signal from a parallel R-C circuit to a digital signal and a scaler for scaling the digital signal from the A/D converter to within a range acceptable for further processing. The memory unit also includes an arithmetic logic unit (ALU) which receives input signals from the scaler and from a digital thermal memory. The input signal supplied to the ALU from the digital thermal memory is a four bit (digital) value proportional to the measured actual thermal status of the subject power line. The output of the ALU is connected to the input of latches which latch, or store, the digital signal produced by the ALU.