Abstract: A current-steering/reproducing digital-to-analog current converting circuit includes a digital-to-analog current converter for converting a digital signal into analog current signal, a current-storing/reproducing module, and a control circuit. The current-storing/reproducing module is used to store a predetermined voltage for conducting the analog current signal in a transforming/storing status and to conduct a reproducing current to a data line in a reproducing/sustaining status. The control circuit is electrically connected between the digital-to-analog current converting device and the current-storing/reproducing module for providing a switch between the transforming/storing status and the reproducing/sustaining status.

Abstract: A multi-channel circuit (1) comprising three channels (CH1 to CH3), each of which is provided with a current steering DAC (5) in which crosstalk between the respective DACs (5) is minimized. Each DAC (5) comprises binary scaled current source devices (Qs1 to Qsn) and current steering switches (Qt1 and Qf1 to Qtn to Qfn) for steering currents from the current source devices (Qs1 to Qsn) to summing nodes (11,12) across which an analogue signal is developed corresponding to a digital input word. Cascode devices (Qc1 to Qcn) are provided between the respective current source devices Qs1 to Qsn and the corresponding current steering switches (Qt1 and Qf1 to Qtn and Qfn) for preventing capacitive feedthrough of voltage swings on the current steering switches (Qt1 and Qf1 to Qtn and Qfn) for minimizing crosstalk between the DACs (5).

Abstract: A current source DAC has calibration of the current sources used for providing the analog output. There are two outputs, one of which provides the output current or else a differential output is provided. The calibration is cyclic and the current source outputs switched to the output terminals are selected as a function of the point within the calibration cycle. The current stage of the cyclic calibration process is thus taken into account in the D/A conversion. For example, the average time since calibration for all current sources having outputs switched to the first output may be approximately equal to the average time since calibration for all current sources having outputs switched to the second output. In this way, the average current of the cells switched to one terminal is identical to the average current of the cells switched to the other terminal, and the average current of the cells switched to each terminal remains constant in time irrespective of the digital signal value being converted.

Abstract: In an I/V converter circuit and a D/A converter, a wide pass band for signal can be obtained and current consumption can be reduced. A current is supplied through an input terminal to a first node, and a first bias current is supplied from a first bias-current generating circuit to the first node. The current supplied to the first node is mirrored to a second node, and a second bias current is supplied from a second bias-current generating circuit to the second node. A first control circuit controls first and second elements of a current mirror circuit so that the voltage of the first node is substantially equal to a bias voltage, a third element converts a current flowing therethrough to a voltage by using the bias voltage as reference, and a second control circuit controls the voltage output from an output terminal so that the voltage of the second node is substantially equal to the bias voltage.

Abstract: A system (e.g., a digital-to-analog converter (DAC)) includes a digital section and an analog section. The digital section has drivers that generate drive signals based on received digital input signals. The drive signals are received at switches in the analog section of the DAC. The switches generate analog signals therefrom. Swing values of the drive signals are limited to a predetermined amount to substantially eliminate glitch in the analog signals. The drivers can be coupled between first and second nodes that receive different power signal values. Controlling the power signal values allows for the limiting of the swing values. Limiting the swing values limits stored charged in the first and second switches, which substantially eliminates glitch in the analog signals. This can be done regardless on environmental variances (e.g., temperature variance) during operation of the DAC.

Abstract: A current-steering/reproducing digital-to-analog current converting circuit includes a digital-to-analog current converter for converting a digital signal into analog current signal, a current-storing/reproducing module, and a control circuit. The current-storing/reproducing module is used to store a predetermined voltage for conducting the analog current signal in a transforming/storing status and to conduct a reproducing current to a data line in a reproducing/sustaining status. The control circuit is electrically connected between the digital-to-analog current converting device and the current-storing/reproducing module for providing a switch between the transforming/storing status and the reproducing/sustaining status.

Abstract: An integrated data driver used in a current-driving display device includes a digital-to-analog current converter for transforming a digital signal into an analog current signal, and a plurality of sets of data driving circuits for driving a plurality of corresponding data lines. Each set of data driving circuits includes a current-copying/reproducing module and a control circuit. The current-copying/reproducing module is used to store a predetermined voltage for conducting the analog current signal in a transforming/storing status and to conduct a reproducing current signal, which is generated by the predetermined voltage, to the corresponding data line in a reproducing/sustaining status. The control circuit is electrically connected between the digital-to-analog current converter and the current-copying/reproducing module for providing a switch between the transforming/storing status and the reproducing/sustaining status.

Abstract: A data driver used in a current-driving display device for receiving a digital signal and for outputting a gray-scaled current signal to a data line. The data driver includes a digital-to-analog current converter for transforming the digital signal into an analog current signal, a current-copying/reproducing module, and a control circuit. The current-copying/reproducing module is used to store a predetermined voltage for conducting the analog current signal in a transforming/storing status and to conduct a reproducing current signal to the data line in a reproducing/sustaining status. The control circuit is electrically connected between the digital-to-analog current converter and the current-copying/reproducing module for providing a switch between the transforming/storing status and the reproducing/sustaining status. The reproducing current signal is the gray-scaled current signal and is almost equivalent to the analog current signal.

Abstract: A method for selecting cells in response to input codes of a digital-to-analog converter distributes noise based on cyclicality of selection patterns to reduce its value, without being dependent upon the input codes. A 6-bit current output type digital-to-analog converter has 63 current source cells C01 through C63. A prime number of, or 61, current source cells are used as cyclically selected cells. That is, 61 current source cells C02-C62, ranging from the second left-most current source cell C02 to the second right-most current source cell C62, are used as cyclically selected cells. The remaining left-most current source cell C01 and right-most current source cell C63 are used as non-cyclically selected cells. The cyclically selected cells, including the 61 current source cells, are selected in response to input codes using a Data Weighted Average (DWA) technique.

Abstract: Disclosed is a digital-to-analog (D/A) converter with low skew and glitches. The D/A converter has current cells each outputting a different current amount and current switches selectively enabling the current cells, and obtains an analog signal from voltages corresponding to output currents of the current cells by operating the current switches, characterized in that the current switches are each provided with MOS transistors each having an adjusted aspect ratio so as to have a constant capacitance load regardless of the output current amounts from the current cells. In such a D/A converter, parasitic capacitances of MOS transistors provided in the current switches are adjusted constant regardless of output current amounts, so that the D/A converter can operate at a high speed with low skew and glitch.

Abstract: “A compensating circuit for use in a switch circuit comprising scaled current steering switches, a switch circuit comprising the compensating circuit, and a method for minimising time-skew in switching scaled current steering switches” An eight bit current steering DAC comprising scaled current steering switches (ST0,SF0,ST(n−1),SF(n−1)) (where n=8) comprises a comprising plurality of compensating MOS switches (SCT0 and SCF0 to SCT(n−1) for minimising time-skew when switching selected ones of the current steering switches from one state to another. The compensating switches (SCT,SCF) are of type similar to the current steering switches (STi and SFi), and are sized so that the combined switching load presented to the corresponding driver circuit (Di) by the sum of the parasitic load capacitance of the current steering switch (STi or SFi) and the corresponding compensating switch (SCTi or SCFi) is substantially similar for each driver circuit (Di).

Abstract: A driver circuit for use in driving displays has an input receiving a digital input data having n bits for selecting one of a plurality of voltage levels for driving the circuit. The circuit also has an output, a plurality of digital signal lines coupled to the digital input data, and a plurality of active regions coupled to a first side of the output. Each of the plurality of active regions is coupled to a separate voltage level. The circuit further includes a plurality of pass transistors at a first subset of locations where the plurality of digital signal lines overlap the plurality of active regions, and a plurality of depletion-implanted transistors at a second subset of locations where the plurality of digital signal lines overlap the plurality of active regions. The number of the plurality of digital signal lines on one side of the output can be odd number, such as 2n−1, or can be 2n−2.

Abstract: A current steered digital to analog converter (DAC) circuit includes a reference input transistor, a plurality of current steered current sources each coupled to the reference input transistor and configured to provide a combined current source output and an output current mirror having an input coupled to the combined current source output. The output current mirror provides current gain to enable the DAC circuit to provide the required output current magnitude, while at the same time, enabling the DAC itself to operate with a smaller reference current into the DAC. The output current mirror may advantageously be either a regulated cascode current mirror or a high-swing cascode current mirror.

Abstract: In a semiconductor integrated circuit device, a reference voltage is connected to one input terminal of an amplifier, and the voltage appearing on the output side is divided by a plurality of resistors and is negatively fed back to the other input terminal of the amplifier to control the output voltage. Here, according to an input code fed to the semiconductor integrated circuit device, switching devices are turned on or off correspondingly to vary how the resistors are connected and thereby control the voltage division factor. Thus, the output voltage is set according to the input code.

Abstract: A high-precision high-linearity digital-to-analog converter (DAC) and a method for converting a digital input signal having N bits to a substantially equivalent analog current output signal is presented. The DAC segments the digital input signal bits into groups separate processing. The invention includes a first current-steering digital-to-analog converter configured to receive a first group of i input signal bits and a first reference current to produce a first current signal. A second current-steering digital-to-analog converter is configured to receive a second group of j input signal bits and the first reference current to produce an intermediate current signal. The intermediate current signal is scaled down by a factor of 2j to produce a second current signal. A summing circuit sums at least the first and second current signals to produce an analog current signal representative of the digital input signal value.

Abstract: A system and method are provided for controlling the on/off timing relationship between two transistors in a differential that are connected at a tail node to a common current generator. The on/off timing relationship is controlled by on/off signals that control the state of the transistors such that one transistor turns one while the other is turning off. An overlap signal is derived from the tail node excursion and is indicative of whether the on/off signals are overlapping too much or too little. A control signal is generated based on the overlap signal. The timing of driver signals used to derive the on/off signals is adjusted based on the control signal. When more overlap is needed, the timing of the driver signals is adjusted such that there is more overlap of the derived on/off signals. When less overlap is needed, the timing of the driver signals is adjusted such that there is less overlap of the derived on/off signals.

Abstract: A multi-channel bit-serial analog-to-digital converter with reduced channel circuitry is described herein in which a one-bit comparator circuit is split between a first part located within an input channel and a second part located outside the input channel. The external part of the comparator and the one-bit latch are shared by a plurality of input channels. In the preferred embodiment, a two-dimensional sensor array of pixel elements is fabricated in a single integrated circuit. Each of the pixel elements is an input channel which comprises a photodetector and the front-end part of the one-bit comparator. The external part of the comparator and the one-bit latch are formed in the periphery of the sensor array and are shared by a group of pixel elements, such as a column of pixel elements. In one embodiment, by connecting the output of an inverter to the control signal terminal of the comparator, the comparator can also be used as a buffer for analog readout.

Abstract: A digital-to-analog converter which can be used with multi-bit digital codes without increasing the module size thereof, as well as a current source and a differential amplifier, which are preferably used in the digital-to-analog converter. A constant current source supplies a current corresponding to the LSB in a digital code to be converted, resistors generate voltages corresponding to bits other than the LSB in the digital code, and as the generated voltages are applied to the gate terminals of MOSFETs, the MOSFETs permit passage of the currents corresponding to the bits other than the LSB in the digital code. A current source, together with the resistors, provides voltages to be applied to the gate terminals of the MOSFETs, which voltages make the MOSFETs operate in a sub-threshold region, and also make the MOSFETs permit passage of the currents corresponding to the bits.

Abstract: An analog-to-digital converter in which each of a plurality of comparators is, in a successive approximation manner, selectively enabled or disabled and the outputs from those comparators summed together to produce a digital signal therefrom. By weighting and mixing outputs of adjacent comparators in proportions calculated to provide an interpolated output of a virtual comparator between the actual comparators, many such virtual comparators can be created without the need for additional fixed hardware elements in the converter. By doing so, the converter is able to produce a digital output having n bits using only N actual hardware elements for comparing signals, where N<2n−1. Each of the plurality of comparators in the converter has an input for an enabling signal, which enabling signal can be manipulated to enable or disable individual comparators and to modify their outputs. A method for converting an analog input signal into a digital signal using such a converter.

Abstract: An digital-to-analog converting circuit of a display, used for a current-type data driver. The digital-to-analog converting circuit is characterized in that the ratio of channel-width to channel-length (W/L) for each transistor thereof is identical, such that no deviation occurs to the current of data output.

Abstract: A current mode digital to analog converter (DAC) that can provide an output signal having reduced glitch energy over a wide range of manufacturing tolerances and operating conditions includes a cross-over voltage controller with feedback, disposed between the current switch and the input data source. In a further aspect of the present invention, circuitry operable to generate a synchronized differential pair of digital signals as input to the cross-over voltage controller is included. In a still further aspect of the present invention, load matching circuitry is coupled to the cross-over voltage controller output terminals to reduce timing differences between various stages of the DAC.

Abstract: A method and apparatus for trimming a high-resolution digital-to-analog converter (DAC) utilizes floating-gate synapse transistors to trim the current sources in the DAC by providing a trimmable current source. Fowler-Nordheim electron tunneling and hot electron injection are the mechanisms used to vary the amount of charge on the floating gate. Since floating gate devices store charge essentially indefinitely, no continuous trimming mechanism is required, although one could be implemented if desired. By trimming the current sources with high accuracy, a DAC can be built with a much higher resolution and with smaller size than that provided by intrinsic device matching.

Abstract: Mulitplying digital-to-analog converters (MDACs) are provided that reduce signal distortion without significantly raising current demand. These goals are achieved with input structures that lower input impedances and enhance the driving of nonlinear capacitances that are generally presented by the DAC portion of these devices.

Abstract: Digital/analog converter with programmable gain for converting a digital input signal (Dn) into an analog output signal, the digital/analog converter (1) having: a signal input (2) for applying the digital input signal (Dn) a reference current source (7) for generating a reference current (Iref&phgr;), the current intensity of the reference current output by the reference current source (7) being adjustable via a setting terminal (4) of the digital/analog converter (1) current mirror circuits which mirror the generated reference current (Iref) with an associated current mirror ratio to form mirror currents a controllable switching device (57), which switches through the mirror currents output by the current mirror circuits, in a manner dependent on the digital input signal (Dn) present at the signal input (2), to a summation current node (62) for generating a summation current (Isum) and a current/voltage converter (17) for converting the generated summation current (Isum) into a corresponding voltage (U

Abstract: Unwanted voltage drops associated with the bit switches of a DAC are compensated with an output amplifier circuit for the DAC that includes a feedback circuit with a switch compensation resistance element that is connected in a combined series/parallel circuit with a feedback resistance circuit, so as to reduce both the size and associated capacitance of the resistance element.

Abstract: A current output circuit for use in a digital-to-analog converter is disclosed. The current output circuit includes a current source for providing a driving current, and a first output circuit coupled with the current source. The first output circuit includes a first metal-oxide semiconductor (MOS) transistor device having a source electrode thereof connected to the current source in series, a first voltage amplifier coupled between the source electrode and a gate electrode of the first MOS transistor device for keeping a voltage of the source electrode substantially constant, and a first controlled switch coupled between an operational voltage and the gate electrode of the first MOS transistor device for being switched ON or OFF in response to a first digital control signal, and allowing the driving current to be outputted from a drain electrode of the MOS transistor device when the first controlled switch is switched ON.

Abstract: A scrambling or encryption method involves analog-to-digital, digital-to-analog, analog-to-analog or digital-to-digital conversions that are constructed from one or more analog-to-digital or digital-to-analog conversions. For example, encryption of an analog signal converts the analog signal to an intermediate digital signal that is converted back into a scrambled analog signal. Encryption of a digital signal converts the digital signal to an intermediate analog signal that is converted back into an encrypted digital signal. The conversions between analog form and digital form and back can be repeated. A codec scrambling/descrambling and encryption/decryption implements one or more different analog-to-digital conversions and one or more digital-to-analog conversions. One embodiment of the codec includes a programmable conversion array that includes an array of transistors such as floating gate transistors in memory cells.

Abstract: A converter for converting digital data into differential analog signals includes a temperature and process independent bias voltage generator for generating a bias voltage and a digital to differential converter for converting a digital word into differential voltages. The digital to differential converter includes a first switching circuitry controlled by the digital word for selectively coupling a first output node to the bias voltage and a second output node to a supply voltage. Second switching circuitry controlled by a complement of the digital word selectively couples the first output node to the supply voltage and the second output node to the bias voltage. The first and second pairs of switches substantially simultaneously conduct at a desired differential cross-over voltage at the first and second output nodes based on the choice of the bias voltage such that the digital to differential analog converter operates from the operating voltage to the operating voltage plus the bias voltage range.

Abstract: A D/A converter circuit capable of handling a high bit number digital signal, having good linearity, and having a small occupied surface area is provided. The D/A converter circuit has n−m+1 capacitors (where m is a natural number, and smaller than n), and the supply and discharge of electric charge to one of the capacitors from among the n−m+1 capacitors are controlled by the lower m bits of a digital video signal. The supply and discharge of electric charge to the remaining n−m capacitors, from among the n−m+1 capacitors, are controlled by the upper n−m bits, from among the n bits, of the digital video signal.

Abstract: A method comprising identifying a sample rate of received audio content, receiving a conversion sample rate, and converting the received audio content to the received conversion sample rate. Wherein the conversion comprises utilizing a repeating sequence of packets where all but one of the packets of each sequence are truncated to a whole number of samples, while the remaining packet is rounded up to the next whole number of samples if the conversion fails to resolve packet size to a whole number.

Abstract: High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes is disclosed. Encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number are thermometer encoded and complemented to provide signals to drive analog conversion circuitry. The analog conversion circuitry includes sets of current cells, with each cell in a set contributing an equal amount to one or the other of the complementary legs of the analog output of the converter. Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance.

Abstract: A digital-to-analog converter which can be used with multi-bit digital codes without increasing the module size thereof, as well as a current source and a differential amplifier, which are preferably used in the digital-to-analog converter. A constant current source supplies a current corresponding to the LSB in a digital code to be converted, resistors generate voltages corresponding to bits other than the LSB in the digital code, and as the generated voltages are applied to the gate terminals of MOSFETs, the MOSFETs permit passage of the currents corresponding to the bits other than the LSB in the digital code. A current source, together with the resistors, provides voltages to be applied to the gate terminals of the MOSFETs, which voltages make the MOSFETs operate in a sub-threshold region, and also make the MOSFETs permit passage of the currents corresponding to the bits.

Abstract: A calibrated current source includes current source having an output node; a calibration circuit; a load circuit; a cascode switching circuit including a pair of cascode switches, one connected between the local circuit and output node, the other connected between the calibration circuit and the output node; and a bias circuit selectively applying a bias voltage to the cascode switches to selectively connect the load circuit and the calibration circuit to the output node while maintaining a constant voltage at the output node and across the current source to provide a consistent current to the load and calibration circuits.

Abstract: Located between the frustoconical needle tip and the cylindrical needle shank of a nozzle needle of a fuel injection valve is a frustoconical needle portion, into which is introduced a peripheral groove, by means of which damping is capable of being set, depending on the position of the groove, during the axial movement of the nozzle needle.

Abstract: A current switching cell for a multi-cell DAC, each cell having a data input and an analog output and including a current switching circuit having a current node; a current definition circuit for providing current to the current switching circuit at the current node; the current definition circuit having a parasitic coupling between the input and the current node; a driver circuit responsive to a data input for actuating the current switching circuit to provide an analog output from the current from the current definition circuit; and a control circuit responsive to at least one common control signal for controlling the current definition circuit and isolating the parasitic coupling between the current node and the common control signal; the driver circuit may also have a parasitic coupling between its driver input and the current node and the control circuit may isolate the parasitic coupling between the current node and the driver input.

Abstract: An analog switch comprises a first transfer gate, a second transfer gate, an inverter and a transistor switch. The first transfer gate has the first input terminal and the first output terminal, and controls transmission of an input signal in accordance with a first control signal and a second control signal which is an inverse signal of the first control signal. The second transfer gate has the second input terminal and the second output terminal. The second input terminal of the second transfer gate is connected to the first output terminal. The second transfer gate controls transmission of an input signal which has passed the first transfer gate in accordance with the first control signal and the second control signal.

Abstract: A DAC (1) comprises a pair of outer strings (4,5) of resistors Ra and Rb and an inner string (12) of resistors Rc connected in series with the outer string (4,5). The inner string (12) converts the LSBs, while the outer strings convert the MSBs. Outer switch networks (10,11) of switches Sa and Sb selectively switch the outer strings (4,5) to reference voltage terminals Vref+ and Vref− (8,9) for selectively coupling selected portions of the outer strings (4,5) to the respective voltage reference terminals (8,9) for decrementing the inner string (12) in steps corresponding to one MSB between the terminals (8,9). An inner switch network (15) of switches Sc selectively connects an analog output terminal (2) to one of the resistors Rc; corresponding to the LSBs so that the analog voltage on the output terminal corresponds to the digital input signal.

Abstract: In accordance with a preferred embodiment, a self-calibrated cell (and corresponding operation) is provided that receives a reference parameter (e.g., current, voltage, etc.) for storage in the cell and for supplying to a load. The individual cell is controlled to operate in different states or modes: either a redundant mode or a supplying mode. In the redundant mode, the reference parameter is stored in the current cell during a calibration phase or mode, and the stored reference parameter is dumped or otherwise transferred, preferably to ground, during a dumping state or mode. In the supplying mode, the current cell transfers or supplies the stored reference parameter to the load. The individual cell is controlled to operate in its dumping state both before the cell enters the calibration mode and also at the same time that the cell is switched from the calibration mode to the supplying mode. In accordance with a preferred embodiment, the individual cells may be employed in a cell array of a converter (e.g.

Abstract: A non-linear bulk capacitance bootstrapped current switch includes a current switch circuit including a source node and a first bulk connection having a first bulk capacitance associated with it; a current defining circuit connected to the source node and having a second bulk connection having a second bulk capacitance associated with it; and a tracking circuit for driving the voltage on at least one of the first and second bulk connections in response to the voltage on the source node to reduce the associated non-linear bulk capacitance.

Abstract: A composite digital-to-analog converter (DAC) includes a first DAC and a second DAC. The first DAC has a first range and a first error. The second DAC has a second range and a second error. The second range of the second DAC is less than the first range of the first DAC. The second range of the second DAC is greater than the first error of the first DAC. The second error of the second DAC is less than the first error of the first DAC. The composite DAC has a composite range and a composite error. The second DAC is coupled to minimize the composite error such that the composite range of the composite DAC is the first range and the composite error of the composite DAC is the second error.

Abstract: A circuit includes a switched current source having a switching transistor coupled in series to a bias transistor. An isolation transistor is coupled in series to an output of the switched current source. The width of the switching transistor is greater than the width of the isolation transistor.

Abstract: A low power cyclic RSD analog to digital converter (20) has a single RSD stage (22) that receives one of an analog input signal and a residual voltage feedback signal and converts the one selected signal to a digital output signal. The RSD stage (22) generates the residue voltage feedback signal. A first switch (32) is connected between a converter input terminal (30) and an input terminal of the RSD stage (22) for applying the analog input signal to the RSD stage input terminal. A second switch (52) is connected between an output terminal of the RSD stage (22) and the input terminal of the RSD stage. When the first switch (32) is closed, the second switch (52) is open so that the analog input signal is input to the RSD stage (22), and when the first switch (32) is open, the second switch (52) is closed so that the residual voltage feedback signal is input to the RSD stage (22).

Abstract: A digital-to-analog converter having a semiconductor resistor strip with plural voltage taps. One voltage tap formed of the semiconductor material defines a nonzero reference voltage for the converter. An auto-zeroing amplifier is utilized to charge a coupling capacitor to the nonzero reference voltage. In the conversion process, the analog voltages at the other voltage taps of the resistor strip are selected via a switch arrangement and coupled to the coupling capacitor. The linearity of the digital-to-analog converter is thus more independent of parasitic resistances that may be formed in the ground connection to the resistor string.

Abstract: A circuit includes an analog-to-digital (A/D) converter for multiplexing between a number of analog input signals and converting the selected analog input signals to a digital code representation. The A/D converter includes a comparator having a first input terminal connected to receive the first signal having a number of levels, a second input terminal connected to receive a multiple number of analog input signals, and a third input terminal for receiving a multiple number of input select signals. The comparator includes a multiplexer coupling the multiple number of analog input signals to a multiple number of corresponding input signal paths. The multiplexer selects one of the multiple number of input signal paths based on the multiple number of input select signals. In one embodiment, the A/D converter is applied in a digital image sensor for performing pixel-level analog-to-digital conversion using a multi-channel bit serial ADC technique.

Abstract: Briefly, in accordance with one embodiment of the invention, a digital-to-analog cell includes an analog circuit that provides, at least in part, an output signal. Transistors may be coupled to the analog circuit to provide source-side switching of the analog circuit.

Abstract: A method for upsampling a digital audio signal is described. The method includes receiving a first digital audio signal including samples and having a first sampling rate. The method also includes outputting at least one sample from the first digital audio signal as part of a second digital audio signal, the second digital audio signal having a desired second sampling rate, the second sampling rate being higher than the first sampling rate. The method also includes incrementing a counter for each sample from the first digital audio signal that is output as part of the second digital audio signal. The method also includes, when the counter exceeds a threshold number, inserting at least one synthetic sample as part of the second digital audio signal. The method also includes repeating the outputting, incrementing, and inserting until all the samples in the first digital audio signal have been output.

Abstract: A system for quantizing an analog signal comprises a first negative-resistance device. The first negative-resistance device has a first terminal coupled through a capacitor to receive a clock signal and a second terminal coupled to receive an analog input signal. A second negative-resistance device has a first terminal coupled to receive the input signal and a second terminal coupled through a capacitor to receive an inverted clock signal. An output terminal is coupled to the second terminal of the first negative-resistance device and the first terminal of the second negative-resistance device. A quantized output signal is generated at the output terminal.

Abstract: In a sigma-delta modulator the feedback circuit (4, 5) has an adjustable feedback factor controlled by an adjusting member (6) for adjusting the feedback factor of the feedback circuit.

Abstract: An eight bit current steering DAC comprising scaled current steering switches (ST0,SF0,ST(n−1),SF(n−1)) (where n=8) comprises a scaled load compensating circuit (12) comprising a plurality of compensating MOS switches (SCT0 and SCF0 to SCT(n−1) to SCF(n−1)). The compensating switches (SCT,SCF) are of type similar to the current steering switches (ST1 and SFi), and are sized so that the combined switching load presented to the corresponding driver circuit D1 by the sum of the parasitic load capacitance of the current steering switches (ST1 or SF1) and the corresponding parasitic switching load capacitance of the corresponding compensating switch (SCTi or SCF1) is substantially similar for each driver circuit D1. Additionally, by virtue of the fact that the switching load capacitance, and in turn the switching loads presented to the driver circuits (D1) are similar, the driver circuits (D1) are therefore also similar to each other.

Abstract: Digital-to-analog converters (DACs) are used to convert digital signals to analog signals. DAC's are typically made of transistors, linked in one of several ways, to quickly convert large amounts of digital information to useful analog signals. Sample applications may include compact disc players and DVD players. DACs with transistors having more uniform outputs result from better control of the source-to-gate voltage. This control may be achieved by using a current source for the gate voltages, or in other embodiments, by designing and manufacturing the bus bar for the source voltage and the gate voltage so as to achieve uniform source-to-source and gate-to-source voltages. With this control, uniform voltage drops, linear within 0.1%, may be achieved in transistors used in 5-bit to 15-bit DACs, leading to better conversion.