Abstract: A comparator (20, 30) for comparing first and second current inputs includes a first stage that has a first resistor (43) being coupled to a first input node and operable to produce the a first voltage level corresponding to the first current input at a first voltage node when a CLK signal is high. A second resistor (45) is provided and is coupled to a second input node and operable to produce a second voltage level corresponding to the second current input at a second voltage node when the CLK signal is high. A pair of cross-coupled transistors (36, 37) are coupled to the first and second voltage nodes when a CLK signal is high and are operable to latch the first and second voltage levels when the CLK signal is high. A first differential amplifier (60) is coupled to the first voltage node and is operable to receive the latched first voltage level at a non-inverting input and the latched second voltage level at an inverting, input and to generate a first amplified voltage level when the CLK signal is high.

Abstract: Differential switching circuitry, for use for example in a digital-to-analog converter, includes: a first switch element (S1) connected between a common node (CN) and a first output node (OUT1), and a second switch element (S2) connected between the common node (N) and a second output node (OUT2). First and second driver circuits (12, 14) correspond respectively to the first and second switch elements, each driver circuit switching its corresponding element ON and OFF in dependence upon an applied input signal (IN1, IN2). The driver circuits co-operate such that one switch element is ON when the other is OFF. Each switch element (S1, S2) is paired with a matching element (46, 44) in the other switch element's driver circuit. That matching element (e.g. 44) is coupled operatively to its paired switch element's driver circuit (14) and is matched, e.g.

Abstract: A digital/analog converter has a neuron MOS transistor, a maintenance circuit which keeps the drain potential of the neuron MOS transistor constant, and a current source. A linear dynamic range in terms of large signal is possible, so that converters having a larger input word size than, for example, only two bits can be realized in a simple way with low dissipated power. Such converters are of significance particularly for ULSI circuits.

Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs for digital signals and an output for an analog signal. It comprises a current amplification circuit having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors corresponding to the plurality of converter inputs and having their source terminals coupled together and to a first reference of potential. The converter has drain terminals coupled together and to the input of the amplification circuit, and has control terminals coupleable, under control from the inputs of the plurality, to different references of potential having selected fixed values.

Abstract: In a current amplifier, a current obtained by holding an input current from an input terminal by a first current sample/hold circuit is added through a connection to a current obtained by inverting the input current by a current inverter to generate a current twice the input current. This current is alternately sampled and held by second and third current sample/hold circuits and alternately output to an output terminal.

Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs for digital signals, and an output for an analog signal. It also contains a charge integration circuit having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors corresponding to the plurality of converter inputs, the MOS transistors all having their source and drain terminals coupled together and to the input of the integration circuit, and having control terminals coupleable, under control from the plurality of inputs of digital signals, to different reference voltages having selected fixed values.

Abstract: A current source apparatus with bias switches, applied in digital-to-analog converters, is disclosed. The current compliance and settling time performances can be promoted via improving the structure of the bias circuit and making the MOS transistors operate in the saturation region, without increasing the dimensions of the MOS transistors.

Abstract: When a pair of emitter-coupled transistor switches 22A and 22B are switched over, the D flipflop 26A shifts the base potential of a transistor buffer circuit 24 to reduce a potential fluctuation at a constant current source 21, reducing a current oscillation caused by the transient response of the constant current source 21 in which feedback control is performed by a comparator 214. In another construction, a potential oscillation waveform of the connected emitter node is stored in a RAM and the waveform read out of the RAM is added to the base of the transistor buffer circuit to reduce the current oscillation.

Abstract: An improved current steering cell for a DAC which eliminates the need for an inverter reduces the noise at the common mode. The cell includes a first and a second current steering MOS transistor of a first polarity type, each having a gate and a pair of current passing terminals. The cell has an input terminal for receiving digital input signals coupled to the gate of the first of the pair of current steering transistors, and a common mode node for receiving an input current coupled to the same one of the pair of current passing terminals of each current steering MOS transistor. The current output terminal of the cell is coupled to the other of the pair of current passing terminals of the first of the current steering MOS transistors.

Abstract: An improved current source cell apparatus for a digital/analog converter which is capable of off-setting noises and obtaining a faster current switching by using different type current source cells which are alternately arranged, thus being well adaptable to a high frequency digital/analog converter. First current source cells receive a first bias voltage, a second bias voltage, and an inverted second voltage, respectively, and are enabled when the second bias voltage is a low level signal. A plurality of second current source cells are connected alternatingly with the first current source cells, and also receive the first bias voltage, the second bias voltage, and the inverted second bias voltage, respectively, and are enabled when the second bias voltage is a high level signal. A load resistor is commonly connected with the output terminals of the first and second current source cells through a common node, for thus obtaining an output voltage drop thereacross as an analog signal.

Abstract: The present invention provides a D/A converter which has a small area in the chip, a linear current output and a high-speed operation. Each of resistors R.sub.11 -R.sub.n1 in a resistor train 11a is composed of four MOS transistors which are connected in parallel with each other and each of resistors R.sub.12 -R.sub.n2 in a resistor train 11b is composed of four MOS transistors which are connected in parallel with each other. Between the connecting nodes of the resistor trains 11a, 11b, MOS transistors ST.sub.11, ST.sub.12, ST.sub.13, ST.sub.14 -ST.sub.n1, ST.sub.n2, ST.sub.n3 and ST.sub.n4 which serve as switches and resistors are connected. All the MOS transistors have the same conductive type and size. Gate control signals C.sub.11 -C.sub.n1 ; C.sub.12 -C.sub.n2 turn MOS transistors ON but each of them has a different voltage value. A current difference between the output terminals Za and Zb is converted into a voltage difference by an operational amplifier or the like.

Abstract: A D/A converter implemented by an integrated circuit has a first section for conversion of higher-order N1 bits of an input digital signal to output a first current signal I.sub.1, a second section for conversion of lower-order N2 bits of the input digital signal to output a second current signal I.sub.2, a dividing section for dividing the second current signal to output a third current signal I.sub.2 .times.1/2.sup.N2, and an adding section for adding the first and third current signal. The D/A converter can be implemented by a reduced number of MOSFETs and has a reduced occupied area.

Abstract: A multiplying digital-to-analog converter produces first and second output currents that have a magnitude difference equal to a gain value multiplied by a magnitude difference between first and second input currents. The multiplying digital-to-analog converter has first and second input nodes for carrying the first and second input currents and first and second output nodes for carrying the first and second output currents. A first input transistor has a first terminal coupled to the first input node, a second terminal with voltage that increases with increases in the first input current, and a third terminal for carrying a first input bias current. A second input transistor has a first terminal coupled to the second input node, a second terminal with a voltage that increases with increases in the second input current, and a third terminal for carrying a second input bias current.

Abstract: The output of an analog to digital converter is selectively controlled to provide a non-linear response by addition or removal of current from resistors in the ADC reference level resistor ladder so that voltage drops are reduced or increased across selected resistors. In one embodiment a current mirror is employed to remove current at selected nodes of the resistor ladder. Span current and current mirror current can be controlled so that span and the desired non-linearity will track when span is altered.

Abstract: A digital-to-analog converter that includes pairs of positive and negative current sources that are connected through switches to two differential output lines. The switches are controlled as a function of a digital data. Each pair of current sources includes a pair of transistors of an output stage of a transconductance amplifier. The transconductance amplifier receives a reference voltage at a non-inverting input, and receives at an inverting input, the voltage at the middle node of a bridge of resistors that is connected between the two differential out-put lines. The output of the converter is the voltage between the two differential output lines.

Abstract: An output current unit comprises a cascode circuit having a first transistor connected between a voltage supply line and complementary outputs. Second and third transistors are controlled by inverter circuitry having parallel conducting paths between an output node and a ground line, the parallel conducting paths having different current carrying capacity with control circuitry to switch the stronger of the current carrying paths.

Abstract: A digital to analog (D/A) converter which has good monotonicity and is small in scale of circuitry, wherein a coarse D/A converter is separated from the fine D/A converter, and the output from the coarse D/A converter is added to the output from the fine D/A converter, and wherein the coarse D/A converter converts an upper bit digital input signal to an analog output signal, and the fine D/A converter converts a lower bit digital input signal to an analog output signal, wherein differential pairs are provided having different weighted transconductances based on the lower bit digital input signal, and are controlled to add at the same time the converted analog output signal from the fine D/A converter to the converted analog output signal from the coarse D/A converter, whereby resolution is substantially improved.

Abstract: A current cell for converting a digital signal to an analog current signal is disclosed. The current cell includes a first PMOS transistor which receives the digital signal from a pre-stage processor by the gate. A drain of the first PMOS transistor is grounded. A second PMOS transistor has a source which is connected to the source of the first PMOS transistor, a gate which receives an inverse signal of the digital signal from the pre-stage processor, and a drain for providing the analog current signal. A third PMOS transistor is connected between a voltage source and the source of the first PMOS transistor. The third PMOS transistor has a gate to which a first reference voltage is applied.

Abstract: An operational amplifier in a bias voltage generator of a MOS current summing digital to analog converter corrects deviations in output current due to variations in drain to source voltages in current slaves caused by differing output resistances and supply voltages. Matching of MOS current sources uses an operational amplifier feedback circuit to create a controlled turn-on reference voltage used for biasing selected differential current paths so as to eliminate drain to source voltage variations in precisely ratioed current slave MOS transistors. One transistor of each differential current pair is enabled by a corresponding switch coupled to the turn-on reference voltage produced by the operational amplifier. In the preferred embodiment, the switches are CMOS transmission gates enabled by the binary digital input and its complement. Low voltage (3 volts) operation is achieved by having minimum number of stacked transistors between power supply voltages.

Abstract: A current memory cell comprises a first bipolar transistor providing a current source and coupled to the emitters of a second and a third bipolar transistor, the latter forming the storage elements of the memory cell. The memory cell is calibrated, to avoid mismatch between the second and third transistors, by adjustment of the current source via a parallel arrangement of a resistor and a field effect transistor in the emitter circuit of the first transistor.

Abstract: The invention provides a semiconductor circuit which can fetch and store analog and multilevel data by using a simple circuit. The invention also provides a multilevel memory which can freely change the number of quantizing levels by using external signals. This semiconductor circuit comprises a first circuit which converts first signals into a group of quantized signals, a second circuit which converts the signal group into second multilevel signals, and structure which feeds back the second signals to the first circuit as first signals. The semiconductor circuit further has a structure to electrically separates at least one signal included in the signal group from the input of the second circuit, and structure which feeds back the second signals to the input of the second circuit instead of the signal previously separated.

Abstract: A switch architecture for a digital-to-analog converter provides improved linearity. A first switch for one leg of the R/2R resistance ladder includes a unit resistor coupled between the MOSFET devices of the switch and the respective leg of the R/2R ladder. The on resistances of the MOSFET devices of the first switch are controlled in response to a reference value, such as the resistance of a reference resistor, which may have a resistance and other characteristics similar to the unit resistor. Other switches for other legs of the R/2R ladder also have a unit resistor, or other MOSFET devices having an on resistance controlled in relation to the reference value. Additional switches for other legs of the R/2R ladder may also have MOSFET devices of varying width to channel (W/L) ratios. Each of these approaches may be combined to achieve a binary weighting or an alternate weighting between legs of the R/2R ladder, in order to provide low linearity error.

Abstract: A precise current cell for a digital-to-analog (D/A) convertor circuit is designed to compensate for manufacturing process variations. The cell uses a cascoded transistor chain to control the output voltage and isolate voltage supply noise. An external (off-chip) bias current is fed into a cascoded biasing string of eight transistors, which are further mirrored to the current cell itself. The biasing scheme accounts for manufacturing process variations in the chip, which leads to very precise current being replicated at the output of the D/A circuit. Current steering and an improved shunt path within the current cell minimizes voltage swings during switching of the current cell. This allows for faster switching of the cell while minimizing noise coupling due to the voltage swings. The current cell also has an associated biasing stage. This biasing stage allows for improved matching within the current cell, resulting in improved accuracy of conversion.

Abstract: Disclosed is a delay interpolator (DI) circuit (or mixer) that can be driven by digital signals. This DI circuit may be incorporated in the loop of a delay interpolator voltage controlled oscillator (DIVCO) circuit. In turn, the digital DIVCO circuit may be inserted in the loop of a phase-locked loop (PLL) circuit for total digitalization thereof. The novel digital delay interpolator circuit (23) has the base structure of the conventional analog delay interpolator circuit except in that, at the first (bottom) level, the two standard NFET input devices which are normally controlled by an analog signal (typically generated by a preceding DAC) are respectively replaced by two arrays (24A, 24B) of smaller NFET devices connected in parallel. The gate of each NFET device of the first array is driven by a bit (c0, c1, . . . ) of the true phase of the digital signal. The gate of each NFET device of the second array is driven by a bit (c0, c1, . . . ) of the complementary phase of the digital signal.

Abstract: A priority encoder for encoding input data by scanning the input data in a predetermined direction, includes: a first voltage section for charging a plurality of output lines to a first voltage level; a plurality of switching elements connected to the plurality of the output lines, each of the plurality of switching elements being turned on in accordance with a value of the input data; and a second voltage section for charging a selected one of the plurality of output lines to a second voltage level different from the first voltage level, through the switching elements which are turned on.

Abstract: A D/A converter of a current output type desirably compensates for changes in the switching characteristic that arise in each constant current circuit. The D/A converter generates an analog output current that is in response to the level of input digital data and outputs it from an output side by switching each of output currents of a plurality of constant current circuits either to the output side or to a non-output side, in response to the input digital data. The D/A converter performs feedback control, for values of the output currents for the constant current circuits, based on an analog output current at the non-output side during a period when the output currents of all of the constant current circuits are connected to the non-output sides.

Abstract: The D/A converting device disclosed includes a decoder, and a plurality of unit current generating circuits each having a differential switching circuit and a reference voltage generating circuit. The decoder receives a digital input value of n bits and outputs a plurality of complementary pairs of digital signals corresponding to the n bits of the digital input value. Each unit current generating circuit receives a complementary pair of digital signals from the decoder. The differential switching circuit has two complementary current output terminals, a bias voltage input and a reference voltage input. The two complementary current output terminals of the differential switching circuit are interconnected between corresponding ones of the unit current generating circuits with the interconnected points being made two complementary analog output terminals.

Abstract: A digital-analog converter has unit current source cells each having a differential switch circuit and a constant current source. The differential switch circuit made of two switches is driven by a pair of complementary driving circuits controlled by a bit signal and the inverted bit signal corresponding to that signal and entered simultaneously. The constant current source outputs a constant current to a first and a second current output terminal via the switch circuit. The signals for controlling the driving circuits that drive the switches are such that the delay time for the switch closing operation will be longer than the delay time for the switch opening operation. As a result, the cross point of the two signals to open and close the switches in a complementary manner becomes greater than the median between the maximum and minimum signal levels.

Abstract: A semiconductor memory circuit which realizes a source follower having a voltage gain equal to one, a decrease in the time necessary for the source follower to reach its full output voltage. Furthermore, the multiple-valued or analog output voltage can be easily converted to a binary-digital form with this memory circuit. This semiconductor circuit comprises at least an MOS transistor. A multiple-valued or analog data line is connected to the inputs of multiple-valued comparators, the outputs of said comparators are coupled capacitively to the input gate of a source-follower circuit, and the output of said source-follower circuit is fed back to the data line.

Abstract: The disclosure concerns a so-called "auto-zeroing" comparator of two analog input voltages to be compared, and an analog-to-digital converter using a set of auto-zeroing comparators enabling the number of comparators required for an analog-to-digital conversion to be reduced. The main originality of the invention is that this comparator includes a second stage constituted by an inverter function provided in such a way that only a first transistor is controlled on its gate by the previous stage, a second transistor having its gate and drain short-circuited by a switch during the auto-zeroing phase, and a third transistor used as a capacitor and connected to the gate of said second transistor and also to the supply voltage. The present invention is applicable in particular to all types of CMOS multi-comparison ADCs using at least one "auto-zeroing" comparator.

Abstract: The present invention relates to a power reduction digital-to-analog (DA) converter current source cell. The power reduction DA converter current source cell is comprised of a DA current source cell for sending a current to a current steering matrix and a switching means coupled to the DA current source cell for dynamically controlling the power dissipation of the DA converter current source cell when the current is not required.

Abstract: A video DAC for driving video displays with reduced power dissipation is presented. This is accomplished using a dual driver circuit connected to a current mirror, the dual driver comprising a strong driver and a weak driver. The dual driver permits switching current between the video load and a dummy load. The current to the dummy load is disabled during periods when the video signal remains steady for a predetermined period of time. The dual driver, using the weak driver, disables the current to the dummy load during video blanking and synchronization periods. This scheme substantially reduces the power dissipation in the DAC.

Abstract: An input cell circuit for an integrated circuit for use in a mixed signal mode where an input pin may receive either digital or analog signals. The circuit solves the problem where several such pins are used in a mixed signal mode and share a common internal bus. Such input signals will cause erratic values on the common analog bus, if any given input pin is used as a digital input signal and the voltage on that input pin exceeds the supply voltage by the base-emitter voltage of the parasitic transistor in the P-channel transistor in a pass gate in the associated input cell. This problem is solved by adding a second P-channel transistor to the pass gate and also adding an N-channel transistor connected to a node between the two P-channel transistors, as well as adding an input resistor.

Abstract: An improved digital/analog converter circuit of the analog multiplying type for providing an adjustment for a DC voltage offset. The digital/analog converter circuit generally comprises a code converter, an analog multiplying current source and a bridge output circuit. The code converter converts the values of the tone data into 2's complement numbers. The numbers are then sent into an analog multiplying current source where positive and negative signals are produced to control the current path of a bridge-type output.

Abstract: A digital-to-analog converter including a plurality of binarily-weighted stages each incorporating a differential switch-pair circuit which includes two matched bipolar switch transistors the bases of which are driven by a corresponding pair of complementarry signal sources. Two additional switches are included in this circuit, with each such switch being connected between a respective signal source and its corresponding transistor control electrode. These two switches are both opened before the clock-controlled activation of the complementary signal sources. A short time after such activation, sufficient to assure that the complementary signal voltages have stabilized at their new values, the two additional switches are reclosed simultaneously by a single control signal so as to effect synchronized switchover of the two switch transistors at that instant.

Abstract: A digital-to-analog (D/A) converter of current segmentation is disclosed. A plurality of current sources are connected in parallel to one another and connected to a load resistance through a plurality of first switches. A second switch is connected in parallel to the first switches and operates oppositely to the first switches. An output impedance compensation resistance is connected in series to the second switch.

Abstract: A converter is provided having a layout which can be easily designed and which requires a small chip area. Four MOS transistors having the same layout are disposed on the same substrate, and a polycrystalline silicon layer extends under the MOS transistors in the substrate. A predetermined voltage is applied to the polycrystalline silicon layer. This applied voltage continuously controls threshold voltages of the MOS transistors. An analog signal is input to gate terminals of the MOS transistors and is digitized in accordance with on and off states of the MOS transistors.

Abstract: A digital-analog converter incorporates an array of current source cells connected at the output to a load as a function of an input code subdivided into H and V values, which are most significant bit (MSB) and least significant bit (LSB), respectively. The input code is converted into thermometric codes, respectively HT and VT, whose logic inverses are respectively horizontally and vertically routed to the array. Each position cell (h, v) in the array comprises a first and a second P type metal oxide semiconductor field effect transistor connected in series, and the series is in parallel with at least one third P type metal oxide semiconductor field effect transistor.

Abstract: A D/A converter having a bias circuit that supplies a well-compensated gate voltage to a weighted current source part of the D/A converter, so that any changes in component characteristics due to the manufacturing of the components making up the D/A converter or due to temperature variations in the D/A converter are compensated for to output a correct analog voltage. The bias circuit comprises an amplifier and a p-type FET, where the drain of the p-type FET is fed back to a non-inverting input of the amplifier, and a reference voltage is applied to an inverting input of the amplifier. The bias circuit operates in a negative feedback condition, such that the non-inverting input is kept as close to the reference voltage as possible. A first resistor is connected to the drain of the p-type FET, to determine the current at the drain of the p-type FET. The weighted current source is made up of FETs having similar operating characteristics as the p-type FET of the bias circuit.

Abstract: A current driven span voltage source for use in an analog to digital converter includes a zero reference resistor serially connected with a resistor ladder. A first current source selectively passes a part of a first current through the resistor ladder to establish a span (gain) voltage range, and a second current source selectively passes a part of a second current through the zero reference resistor to establish a zero reference voltage for the span voltage range. The controlled current sources increase speed, reduce power and thermal noise, and improve temperature related performance as compared with voltage driven span and reference sources using operational amplifiers.

Abstract: A signal processing device comprises a charge transfer device and a driving circuit, which includes a reference signal generating circuit for generating a reference signal, a transfer clock generating circuit receiving the reference signal for generating a transfer clock to a charge transfer section of the charge transfer device, a digital counter of N bits receiving and counting the reference signal, a D/A converter receiving the output of said counter for converting it into an analog voltage signal, which is applied to a final transfer gate of the charge transfer device, and a latch for latching an output of the counter when an output of a electric charge detection circuit of the charge transfer device reaches a predetermined level, whereby the latch outputs a digital signal of N bits corresponding to a signal electric charge outputted from the charge transfer section.

Abstract: The offset associated with mismatch of a pair of input devices in comparators used in applications such as flash converters is eliminated by using only one input device or transconductance circuit, time-shared between the input and reference signals. The input device converts each signal in succession into a current. A current copier stores one of these currents while the input device produces the other current, and the two currents are then compared by connecting them to a common node. The comparator includes a first switch for switching between an input and reference nodes, and an input device which receives a reference signal from the reference node during a first comparison cycle, receives an input signal from the input node during a second comparison cycle, and converts the input signal and the reference signal to input and reference currents, respectively.

Abstract: An integrated-circuit (IC) chip formed with a D/A converter (DAC) having a digitally-programmable circuit for setting the full-scale output range of the DAC by controlling its gain. The IC chip further includes analog sync level generator circuitry for driving computer graphics CRTs. The sync level generator circuitry is integrated with the DAC circuitry in such a way that the sync signal levels track changes made to the full-scale operating output range of the DAC and also track with changes in operating conditions such as varying temperature, supply voltage and RSET resistance in the DAC current control circuitry.

Abstract: A complementary metal oxide silicon (CMOS) data to emitter coupled logic (ECL) data translator system comprised of translator apparatus for receiving data signals from a CMOS circuit powered from a CMOS voltage power source, apparatus for powering an ECL circuit from the power source, a transmission line carrying output signals from the translator apparatus to the ECL circuit, having a predetermined characteristic, a load having the characteristic impedance connecting the transmission line to the power source, and the translator apparatus comprising apparatus for outputting a data signal on the transmission line which corresponds to the received data signals but having an amplitude compatible with the ECL circuit and referenced to a voltage of the power source.

Abstract: An improved current cell and current switch is described for use in digital-to-analog converters and other current mode circuits. The current switch is implemented using BiCMOS circuitry which is characterized by an absence of base current error and a switching speed which is approximately twice as fast as the switching speed of prior art MOS-based switches. According to one embodiment, the current cell is implemented in BiCMOS which offers higher output resistance, smaller minimum voltage, and improved accuracy over prior art MOS-based self-calibrated current cells. According to another embodiment, the current cell is implemented in CMOS and is characterized by a significant reduction in charge injection, leakage current and error due to coupling of the cell output voltage back to the storage node, as compared with prior art MOS-based current cells.

Abstract: A random access memory (RAM) having an array of memory cells the signal lines to which are activatable by corresponding current sources. The memory is divided into "pages", and control pulses are produced to turn on the current sources involved in activating the signal lines to any page of memory cells being accessed and to turn off the remainder. The control pulses are directed through a pipelined pair of registers, and a look-ahead logic circuit examines the two pipelined control pulses identified as the "present" and "next" pulses. This logic circuitry serves to turn on the current sources for the page of memory to be accessed during the next clock time, and to maintain in an on state the current sources for the page of memory presently being accessed.

Abstract: A hybrid monolithic IC that is standardized for controlling various types of electrical equipment, such as circuit breakers, motor controllers and the like. The IC is a hybrid monolithic IC, fabricated in CMOS technology. The shortcomings of utilizing CMOS technology for linear or analog circuitry is overcome by the implementation of the IC to provide a hybrid monolithic IC that is relatively less expensive than using multiple IC's or a single IC fabricated from biCMOS technology. Also, by utilizing a single IC, such control and monitoring circuitry can be located in existing electrical equipment. The IC includes an on-board microprocessor, an A/D subsystem and various input/output devices which make it adaptable for use in various types of electrical equipment.

Abstract: An intrinsic R2R resistance ladder digital to analog converter (DAC) includes a plurality of matched semiconductor ladder switches, one in each of the R and 2R legs of the R2R ladder. The ON resistance of each semiconductor switch being matched to constitute the resistance ladder of the DAC; the ladder switches being operated in response to the digital signal input to the DAC; a reference circuit including a reference semiconductor switch matched with the ladder switches responsive to a reference current to generate a reference voltage; and a voltage follower circuit for monitoring the reference voltage and adjusting the current through the ladder switches to match the voltage at each ladder switch with the reference voltage for precisely fixing the DAC analog output current as a proportion of the reference current in dependence upon the operation of the ladder switches by the digital input signal.

Abstract: A random access memory (RAM) having an array of memory cells the signal lines to which are activatable by corresponding current sources. The memory is divided into "pages", and control pulses are produced to turn on the current sources involved in activating the signal lines to any page of memory cells being accessed and to turn off the remainder. The control pulses are directed through a pipelined pair of registers, and a look-ahead logic circuit examines the two pipelined control pulses identified as the "present" and "next" pulses. This logic circuitry serves to turn on the current sources for the page of memory to be accessed during the next clock time, and to maintain in an on state the current sources for the page of memory presently being accessed.

Abstract: A digital-to-analog conversion device that has one or more conversion cells, each cell coupled to a master voltage source and to a specific binary input element. The conversion cells include binary-weighted or binary-sized output transistors such that each output transistor, when called upon, delivers a unique analog output current corresponding to a particular binary signal. The master potential provided by a stable source is supplied to the control nodes of the output transistors so that the potential at those control nodes remains constant. Switching on and off of the output transistors is achieved by regulating the sources of those transistors rather than their gates. By regulating the operation of the output transistors at their sources, the present invention provides a digital-to-analog converter and a conversion method with little switching noise and minimal switching delay.