Abstract: While a current of a constant current source 503 is equally divided to a plurality of current paths so as to produce a unit current, switches which are series-connected to the respective current paths are controlled by a switch circuit 504 in response to a digital input signal. As a result, since both output currents 505 and 506 whose unit currents are variable can be obtained, a total number of circuit components is reduced, so that not only an occupied area may be reduced, but also resolution in the vicinity of a center may be improved.

Abstract: A DAC stage having a ground offset switch driver control signal generator, provides greater linearity by preventing rail-to-rail voltage swings of the switch driver signals. In one embodiment of the present invention, a pair of inverting logic gates, coupled between a power rail and a node positively offset from ground, are used to drive the current switches in a DAC stage.

Abstract: A signal processor circuit that buffers a ground-referred, signal-dependent, current. A ground-referred node in the circuit is preferably maintained at a ground level. The ground-referred, signal-dependent, current is preferably buffered such that the ground-referred node is preferably maintained at a ground level independent of changes to the ground-referred, signal-dependent, current.

Abstract: Digital-to-analog converters (DACs) are used to convert digital signals to analog signals. DAC's are typically made of transistors, linked in one of several ways, to quickly convert large amounts of digital information to useful analog signals. Sample applications may include compact disc players and DVD players. DACs with transistors having more uniform outputs result from better control of the source-to-gate voltage. This control may be achieved by using a current source for the gate voltages, or in other embodiments, by designing and manufacturing the bus bar for the source voltage and the gate voltage so as to achieve uniform source-to-source and gate-to-source voltages. With this control, uniform voltage drops, linear within 0.1%, may be achieved in transistors used in 5-bit to 15-bit DACs, leading to better conversion.

Abstract: A D/A conversion circuit is described which comprises a n switching, n capacitors and a coupling circuit. Upper n bit of the digital signal control n switches respectively and control charging and discharging of electric charge into the n capacitors, and the n capacitors are connected to the output line in an upper bit writing period. Lower n bit of the digital signal control the n switches and control charging and discharging of electric charge into the n capacitors, and the capacitors are connected to the output line through the coupling capacitor in a lower bit writing period.

Abstract: A converter system for a temperature sensor includes a programmable current source, a digital-to-analog converter, a summer, and an analog-to-digital converter. The temperature sensor provides a measurement voltage in response to application of a bias current. The programmable current source selectively provides two different currents to the temperature sensor such that the temperature sensor provides two measurement voltages during a given temperature measurement. The digital-to-analog converter (DAC) provides an intermediate voltage that corresponds to an approximation of a voltage between the two voltages. A summer is configured to produce an offset measurement in response to the intermediate voltage and the measurement voltage. The analog-to-digital converter (ADC) receives the offset measurement voltage and produces a conversion code. Offsetting the measurement voltage reduces the dynamic range requirements of the ADC such that substantially a full input range of the ADC is utilized.

Abstract: The present invention refers to a method for using a current-steering N-bit D/A converter and to the D/A converter, said converter comprising N binary weighted current sources SIk, k=0, 1, . . . , N−1, connectable to a common output, each current source SIk comprising 2k unit current sources, SIunit, of equal strength connected in parallel, wherein digital input bits bi, i=0, 1, . . . , N−1, bN−1 being the most significant bit (MSB), determine which respective current source, SIk, k=0, 1, . . . , N−1, to be connected to the output.

Abstract: A D/A converter includes a triangular unit weight array. A decoder transforms digital samples into control signals having a linearly weighted binary representation. These control signal are used for activation/deactivation of entire rows or columns of the triangular unit weight array. Finally, the unit weights are combined into an analog output signal.

Abstract: A digital-to-analog converter includes a number of current steering cells. In each current steering cell, a current source is biased by a differential amplifier to provide a high output impedance. The high output impedance in the current steering cell allows the digital-to-analog converter to operate under low supply voltage conditions.

Abstract: A digital to analog converter (40) includes a pulse width modulator (14) and a class-D amplifier (16). The class-D amplifier (16) includes a low pass filter (34). A differential signal is available from two nodes (outp, outm) on the amplifier. Common mode compensation circuitry (42) generates a compensation signal during periods where a PWM signal is not being generated to maintain a common mode average value of (Avdd +Avss)/2 from the nodes, without affecting the differential signal.

Abstract: A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

Abstract: High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes is disclosed. Encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number are thermometer encoded and complemented to provide signals to drive analog conversion circuitry. The analog conversion circuitry includes sets of current cells, with each cell in a set contributing an equal amount to one or the other of the complementary legs of the analog output of the converter. Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance.

Abstract: Digital/analog converter with programmable gain for converting a digital input signal (Dn) into an analog output signal, the digital/analog converter (1) having:

Abstract: A digital to analog converter having low power consumption is provided. The digital to analog converter includes a reference bias voltage generator and a conversion current generator. The reference bias voltage generator generates a predetermined bias voltage, and the conversion current generator includes a plurality of current generators and supplies current which correspond to the bias voltage and a plurality of digital signals to an output terminal. The current generators which correspond to activated digital signals of the plurality of digital signals among the plurality of current generators supply current to the output terminal, but the other current generators which correspond to deactivated digital signals of the plurality of digital signals do not supply current to the output terminal.

Abstract: A mixed signal CODEC including an improved sigma-delta ADC (20) which limits input signals into a switched capacitor configuration and avoids adding circuit overhead in the signal path is disclosed herein. Additionally, it avoids overshoot and settling problems. This sigma-delta analog-to-digital converter (20), having an input signal and an output signal, includes a switch (sw1), a clipping circuit (21), and a known sigma-delta ADC (34). It solves the clipping signal problem by limiting the signal right at the input of the sigma-delta ADC (34). The clipping circuit (21) couples to the switch (sw1) and the sigma-delta ADC (34) for switching the voltage applied to the sigma-delta ADC between the input signal (vin) and at least one threshold voltage (Vn and Vp).

Abstract: A DAC stage having a ground offset switch driver control signal generator, provides greater linearity by preventing rail-to-rail voltage swings of the switch driver signals.

Abstract: A current mode digital to analog converter (DAC) that can provide an output signal having reduced glitch energy over a wide range of manufacturing tolerances and operating conditions includes a cross-over voltage controller with feedback, disposed between the current switch and the input data source. In a further aspect of the present invention, circuitry operable to generate a synchronized differential pair of digital signals as input to the cross-over voltage controller is included. In a still further aspect of the present invention, load matching circuitry is coupled to the cross-over voltage controller output terminals to reduce timing differences between various stages of the DAC.

Abstract: High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes is disclosed. Encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number are thermometer encoded and complemented to provide signals to drive analog conversion circuitry. The analog conversion circuitry includes sets of current cells, with each cell in a set contributing an equal amount to one or the other of the complementary legs of the analog output of the converter. Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance.

Abstract: The present invention relates to an analog-to-digital converter having the following features:

Abstract: A differential digital/analog converter for the conversion of a digital input value into an analog output voltage with a first current source group, which has a plurality of current sources comprising at least one p-MOS transistor, which can be switched to at least one current collecting line (11, 12) in dependence on the digital input value, the first current source group having a binary current source switching segment (4) comprising binary current sources (6), with a second current source group, which has a plurality of current sources comprising at least one n-MOS transistor, which can be switched to the current collecting line (11, 12) in dependence on the digital input value, the second current source group having a binary current source switching segment (5) comprising binary current sources (13), and with an output buffer (3) for the conversion of the current flowing on the at least one current collecting line (11, 12) into the analog output voltage.

Abstract: A method for upsampling a digital audio signal is described. The method includes receiving a first digital audio signal including samples and having a first sampling rate. The method also includes outputting at least one sample from the first digital audio signal as part of a second digital audio signal, the second digital audio signal having a desired second sampling rate, the second sampling rate being higher than the first sampling rate. The method also includes incrementing a counter for each sample from the first digital audio signal that is output as part of the second digital audio signal. The method also includes, when the counter exceeds a threshold number, inserting at least one synthetic sample as part of the second digital audio signal. The method also includes repeating the outputting, incrementing, and inserting until all the samples in the first digital audio signal have been output.

Abstract: The present invention relates to digital to analog conversion. According to an embodiment of the present invention, an exponential transfer characteristic may be produced by adding a fraction of the output current to a reference current in a recursive equation.

Abstract: A multislope, continuously integrating analog-to-digital converter includes a first switch coupled to a first reference voltage, a second switch coupled to a second reference voltage, a third switch coupled to an input voltage, and an integrator operably coupled to the first, second, and third switches. The analog-to-digital converter utilizes a primary discharge current of opposite polarity to a secondary discharge current. The analog-to-digital converter has a high resolution due to a small reference voltage, and a high dynamic range due to a large reference voltage. The analog-to-digital converter can operate in either a conversion mode or a calibration mode. During the calibration mode, a calibration factor is calculated for use during the conversion mode. When applied to the conversion mode, the calibration factor corrects for errors in the conversion process.

Abstract: Considering that MOS transistors on a common integrated circuit can be controlled in resistance ratio between them with a relatively high accuracy, a DA converter is improved in accuracy by replacing resistors required to be accurate with MOS transistors without inviting an increase of the chip area. That is, between a high potential reference voltage (VrefH) and a low potential reference voltage (VrefL), a plurality of MOS transistors (M1-MN) are connected in series such that they normally operate in a linear region and at least one turns OFF during power-down periods of the DA converter. One of partial voltages (V1-VN) of these MOS transistors (M1-MN) is selected by switches (SW1-SWN) controlled in ON-OFF motion by a control signal obtained by decoding a digital input (12) in a decoder (11), and delivered to an analog output (13), such that an analog value corresponding to the digital data given from the digital input (12) is sent out from the analog output 13.

Abstract: The present invention discloses a current-steering digital-to-analog converter and unit cells. The present invention proposes an n-well bias control circuit for generating a bias voltage whose magnitude is less than the power voltage, therefore the body effect of the transistors could be reduced. Relatively, the threshold voltage and VGS would be reduced. Therefore, even in a low-voltage operation, each transistor could be operated normally in the saturation region. Besides, the plurality of pairs of current switches could be implemented in the same n-well region, instead of being implemented in different n-well regions with leaving a space among each other. Finally, the chip area would be reduced.

Abstract: An OTA circuit is disposed between a differential pair composed of NMOS transistors and an NMOS follower transistor that composes an output buffer circuit. The OTA circuit generates a compensation current that is equal to a current that flows in a capacitance formed between the gate and the drain of each of the differential pair transistors and that flows in the reverse direction thereof. The compensation current cancels the current that flows in the capacitance formed between the gate and the drain of each of the differential pair transistors. Thus, a differential amplifier that has a high accuracy and, high gain, and a wide frequency band and that operates at a low power voltage can be accomplished. Using a differential amplifier having a high gain and a wide frequency band, a comparator that operates at high speed and an A/D converter using such a comparator can be accomplished.

Abstract: A current mode digital to analog converter (DAC) that can provide an output signal having reduced glitch energy over a wide range of manufacturing tolerances and operating conditions includes a cross-over voltage controller with feedback, disposed between the current switch and the input data source. In a further aspect of the present invention, circuitry operable to generate a synchronized differential pair of digital signals as input to the cross-over voltage controller is included. In a still further aspect of the present invention, load matching circuitry is coupled to the cross-over voltage controller output terminals to reduce timing differences between various stages of the DAC.

Abstract: The performance of a single-bit cell in a DAC is improved by decoupling the voltage swing across the load resistors from the output of the current steering device. This can be achieved by providing for a single-bit cell having a first load resistor R1 and a second load resistor R2, a current steering circuit, and a decoupling circuit operably coupled between the current steering circuit and the resistors R1, R2. The current steering circuit steers at least part of a current I1 through a circuit path towards either the first resistor R1 or the second resistor R2. The decoupling circuit decouples voltage swings across the load resistors R1, R2 from the current steering circuit.

Abstract: An arrangement for generating an error signal representing the differences between an input signal voltage level (xpk, xnk) and an estimated value (rp, rn) for the input signal voltage level comprises first (T1, T2) and second (T5, T6) transconductors and a differencing circuit (T3, T4, T7, T8) which forms the modulus of the difference between the outputs of the transconductors. The error signal is converted into a probability signal by subtracting the error signal from a constant signal (408) to produce a signal at the output (407) which is a maximum when the input voltage level and estimated voltage level are equal.

Abstract: High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes is disclosed. Encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number are thermometer encoded and complemented to provide signals to drive analog conversion circuitry. The analog conversion circuitry includes sets of current cells, with each cell in a set contributing an equal amount to one or the other of the complementary legs of the analog output of the converter. Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance.

Abstract: A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

Abstract: A signal aliasing circuit that can be used especially to make a series interpolation cell of an interpolation analog-digital converter comprises two pairs of differential arms powered by one and the same current source connected to a first power supply terminal, each pair comprising two transistors, the transistors of one pair being parallel-connected with the transistors of the other pair. Each group of two parallel-connected transistors is connected by a respective common resistor to a second power supply terminal, the two outputs of the aliasing circuit being the combined collectors of the two groups of parallel-connected transistors. The disclosed device can be applied especially to converters whose architecture comprises what is known as a series interpolation part requiring high precision.

Abstract: In a digital/analog converter, a digital-to-analog converting section includes a constant current source circuit having a plurality of binary-coding weighted current output terminals and including a plurality of MOS transistor type current switches driven by digital input signals. Each of the MOS transistor type current switches is connected between one of the binary-coding weighted current terminals and an analog output current terminal. A reference voltage generating section generates at least one reference voltage and supplies it to the constant current source circuit. A current-to-voltage converting section converts an analog output current flowing through the analog output current terminal into an analog output voltage in response to the analog output current and supplies the analog output voltage to an analog output voltage terminal.

Abstract: Switch driver circuity having first and second output nodes with a current-voltage converter connected therebetween and providing current paths of first and second directions between the nodes, switching circuity connected therewith being switchable between first and second states respectively permitting current flow of a common preselected magnitude in respective first and second opposite directions producing potential differences between the first and second output nodes of a common magnitude but respective, opposite polarities.

Abstract: A constant-current generating circuit for implementing high-precision analog output is disclosed in an image processing apparatus that includes a digital-to-analog conversion circuit (DAC) for converting a digital data image signal into analog data. For stably generating a constant current, current-generating transistors formed of basic-capacitance transistors are regularly disposed in the form of a SEA OF GATES (SOG). With this arrangement, uniform pattern formation based on the basic-capacitance transistors can be achieved, so that all the factors of the constant-current generating circuit, such as the drain resistance, the source resistance, etc., can be made uniform, thereby stably generating a constant current. The whole constant-current generating circuit group forming the digital-to-analog conversion circuit becomes totally independent due to the above-described arrangement, thereby stabilizing a constant current within one channel.

Abstract: A self-trimming current source for used in a switched current source DAC is made from a fixed current source and a variable current source, which are connected in parallel to provide a total output current. The total output current is automatically calibrated by temporarily switching one side of the self-trimming current source to a measurement circuit. Based on the measured value, the variable current source is adjusted to make the total output current equal to a predetermined value. The fixed current source is implemented with a complementary pair of field-effect transistors (FETs) connected in a cascode connection, with the two drain terminals presenting high impedances to the circuitry to which they are connected. A DAC typically includes a plurality of self-trimming current sources, each of which is calibrated during each DAC conversion cycle.

Abstract: A switched capacitor type digital-analog converter is provided with an input capacitor group, a first switch group (3-1 to 3-n) a second switch group, a reference voltage switch (6) , a comparator (9), an output capacitor (2) and a short-circuit switch (7). The input capacitor group is composed of an input capacitor (1-0) and a plurality of shared input capacitors (1-1 to 1-n). The first switch group (3-1 to 3-n) applies a first voltage (V1) to the plurality of shared input capacitors (1-1 to 1-n). The second switch group applies a second voltage (V2) to the input capacitor group. The reference voltage switch (6) applies a reference voltage (Vr) to the input capacitor group. The comparator (9) compares an output of the input capacitor group with the reference voltage. An input of the output capacitor (2) is connected to an output of the input capacitor group, and an output thereof is connected to an output of the comparator (9). The short-circuit switch (7) is coupled to the output capacitor (2) in parallel.

Abstract: A skewless differential switching circuit uses skewless switching elements to convert complementary signals with skew into complementary output signals with minimal time skew between the output signals and with equalized rise and fall times of the output signals for minimum harmonic distortion.

Abstract: An apparatus and method for A/D conversion is provided. The apparatus provides for multi-path multi-channel (MPMC) pipelined A/D conversion. Unlike prior art designs in which the handling of multiple channels requires a linear increase in the associated circuitry and components, the current design scales for multiple channel A/D conversion with less than linear scalability. The A/D converter comprises a plurality of stages and interfaces between adjacent columns of the stages. The stages each include an input, a first output, and a second output. Each of the stages is responsive to an input signal applied to the input to output at the first output a bit signal corresponding to at least one significant bit of the input signal and to output at the second output a residue signal corresponding to a difference between the input signal and the bit signal. The stages are arranged in columns.

Abstract: High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes is disclosed. Encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number are thermometer encoded and complemented to provide signals to drive analog conversion circuitry. The analog conversion circuitry includes sets of current cells, with each cell in a set contributing an equal amount to one or the other of the complementary legs of the analog output of the converter. Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance.

Abstract: A signal processing apparatus is formed on a single semiconductor substrate and includes in a mixed relation an analog signal processing section and a digital signal processing section. A plurality of buffers are included on the substrate to buffer the sections from one another for preventing an abnormalities such as circuit malfunctions, circuit failures, noise and excess current flow between the sections at power-on. The buffers are of different types according to the abnormality they are designed to prevent.

Abstract: An output unit includes a constant current source, a switching transistor that dumps the constant current when a first signal is low, and a switching transistor that outputs the constant current when a second signal is low. A drive unit includes an inverter that generates the first signal responsive to a digital signal, and an inverter that generates the second signal responsive to the digital signal inverted. Power supply terminals of the inverters are connected to an output of the current source, and the high-level voltage of the digital signal is higher than the high-level voltage at the power supply terminals. Accordingly, operation timing of the inverters is slower when changing from high level to low level, than when changing from low level to high level, so that the switching transistors do not both turn off simultaneously. This suppresses current fluctuations of the current source.

Abstract: A segmented digital-to-analog converter includes a string DAC (210) and an interpolation DAC (211). The string DAC includes 2M series-connected string resistors (Ri) and 2M pairs of switches (Sia,b). The switch pairs couple a first (201) and second (202) conductor across each resister responsive to the MSB subword decoder (212). The interpolation DAC (211), responsive to the LSB subword decoder (215), connects an input of a plurality of differential stages to the first conductor (201) and second (202) conductor. Each differential stage includes a first transistor (QjA) and a second (QjB) transistor differentially coupled to a corresponding tail current source (In). The drains of the first (QjA) and second (QjB) transistors are connected to a first load device (QL1) and second (QL2) load device and the inverting and non-inverting inputs of the output amplifier (205) via third (203) and forth (204) conductors, respectively.

Abstract: A current-switching method and circuit is provided for use with digital-to-analog converters (DACs) to provide improved compliance and linearity in the output current characteristic. In the current-switching circuit, an additional transistor that is set to a permanently-on state is connected at the output port of the current-switching circuit, which can help increase the output impedance of the current-switching circuit. Moreover, the problem of simultaneous switching-off of two control transistors can be eliminated by connecting the gate of one transistor to a reference voltage whose magnitude is set between the logic-high and logic-low voltage states of the input digital signal. The current-switching method and circuit can therefore meet the requirements of 3 V working voltage with 1.2 V output compliance and the requirements of 10 bits linearity in the output current characteristic.

Abstract: Analog to digital conversion circuitry (800) is disclosed, comprising multiple quantization circuits (802), having a quantization resistor (814, 816, 818, 820) coupled between inputs of adjacent quantization circuits, wherein each quantization circuit comprises an input source follower circuit (804) having an input coupled to an analog voltage input and an output, an output source follower circuit (812) having an input and an output coupled to a digital voltage output (822, 824, 826, 828), a base transistor (836) having a first terminal coupled to the output of said input source follower circuit, a reset transistor circuit (806) coupled to said first terminal and adapted to selectively ground said first terminal responsive to an external signal, a resonant tunneling diode structure (810) coupled at a first end to a second terminal of said base transistor and at a second end to ground, and a dynamic hysteresis loading circuit (808) coupled to a third terminal of said base transistor and to the input of said ou

Abstract: One embodiment of the present invention provides a flash analog-to-digital converter (ADC) based on a feedforward perceptron. The ADC includes a plurality of N stages to provide N digital signals. The plurality of N stages includes a first stage to provide a sum of an input current, related to a voltage to be converted, and of a reference current. The first stage provides a first digital signal in one of first and second states if the sum has one of first and second signs, respectively. The plurality of N stages further includes i stages, with i=2 . . . N. Each stage i includes an output circuit and 2(i−2) sub-stages coupled to the output circuit. Each sub-stage includes an input and a hidden circuit coupled therebetween. The input circuit is configured to provide a first sum of the input current and of a first reference current. Each hidden circuit provides to the output circuit a second reference current when the first sum has a first sign.

Abstract: Converters such as digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) use conversion arrays containing non-volatile memory cells to provide references that depend on the threshold voltages of the memory cells. The array contains sets (for example, rows) of the memory cells where each memory cell in a set corresponds to a digital value and has a threshold voltage that is equal to the analog voltage mapped to the digital value. An ADC applies an analog input signal to the gates of reference cells in a set and generates a digital signal according to which of the memory cells conduct. The ADC does not require comparators and has a low circuit area, low power consumption, and high speed. A DAC selects a memory cell corresponding to a digital input value and reads the memory cell to generate an analog output signal equal to the threshold voltage of the memory cell. An ADC and a DAC can use the same conversion array to ensure that the ADC inverts the conversion that the DAC performs.

Abstract: A self calibrating current mirror circuit has a curent mirror input for receiving an input current, and a current mirror output for providing an output current. The circuit utilizes a comparator, a charge pump and a MOS transistor having a drain connected to pair of transfer gates. In a first mode of operation, the current of the MOS transistor is switched to the current mirror input for calibration. The comparator provides a signal to the charge pump to increase or to decrease the gate voltage of the MOS transistor. In a second mode of operation the current of the MOS transistor is switched to the current mirror output. A plurality of self calibrating current mirror stages are used to obtain a current mirror that provides an output with multiple current levels, for use as a switched current digital to analog converter (DAC).

Abstract: Coding circuitry (34), for use for example in selecting cells of a cell array in a digital-to-analog converter, produces first and second sets of thermometer-coded output signals in dependence upon a binary input signal. As the input signal increases progressively in value from a first value to a second value, the first-set output signals (COLA) are activated in a predetermined sequence and the second-set output signals (COLB) are deactivated in a predetermined sequence. As the input signal increases progressively in value from the second value to a third value, the first-set output signals are deactivated in a predetermined sequence and the second-set output signals are activated in a predetermined sequence.Such coding circuitry reduces the numbers of output signals that change in response to changes in the input-signal value.In another embodiment (FIG. 12) the coding circuitry includes respective row, column and depth decoders (58, 56, 54).

Abstract: Current bit cell having a current source (P1), a transistor (P6) for detecting the presence of a digital signal bit (Bit) and a plurality of transistors (P2, P5, P7) for detecting at least one command signal (L, Lc) so as to command, on a first output (S1) of the cell, the appearance of a current delivered by the current source (P1) as a function of the digital signal (Bit) applied to the cell and of the at least one command signal (L, Lc), a transistor (P9) for detecting the presence of a bit (Bitz) complementary to the bit of the digital signal (Bit) and a plurality of transistors (P3, P4, P8) for detecting the complement (Lz, Lcz) of the at least one command signal (L, Lc), so as to command on a second output (S2) of the cell the appearance of a current delivered by the current source (P1) which is the complement of the current delivered on the first output (S1), the transistors for detecting the presence of bits and of the at least one command signal, the transistors for detecting the presence of compleme