Abstract: A system for processing signals may be configured to apply digital conversion to analog signals, and to apply, prior to the analog-to-digital conversion, a gain to at least a portion of the analog signals. The gain may be controlled and/or adjusted based on processing of digital output generated based on the analog-to-digital conversion. The system may comprise a plurality of sampling slices, which may be configured to provide the analog-to-digital conversion in interleaved (e.g., time-interleaved) manner. Each of the sampling slices may comprise a dedicated gain element, for applying gain to signals handled by the corresponding slice. The gain applied by the gain elements of the sampling slices may be controlled, independently, collectively, and/or in based on grouping into subsets. The gain may be controlled based on application of a particular gain control algorithm, which may be selected from a plurality of predefined algorithms.

Abstract: Sequential digital audio signals are received to calculate a difference between each currently sampled digital audio signal and another digital audio signal sampled at one sampling period before each currently sampled digital audio signal. Differences for the sequential digital audio signals are stored. The number of digital audio signals consecutively clipped is counted in the received sequential digital audio signals. A specific difference is retrieved, from the stored differences, for a digital audio signal sampled at a specific number of sampling periods before each clipped digital audio signal. The specific number of sampling periods is determined based on the counted number of digital audio signals consecutively clipped. Each clipped digital audio signal is corrected based on the specific difference.

Abstract: A comparator tracking scheme for an analog-to-digital converter (ADC) may implement a dynamic window size by varying, over time, a number of comparators powered up to convert an analog input signal to a digital output signal. A comparator-tracking scheme may be implemented, for example, in a controller coupled to a plurality of comparators in an ADC. For example, the controller may determine a window size for the ADC and determine a window position for the ADC. The controller may then activate comparators of the ADC within a window centered at the window position and having a width of the window size. The controller may determine a window size by analyzing an output of a filter. When the filter output indicates a rapidly changing analog input signal, the controller may dynamically increase a window size of the ADC, which may increase a number of comparators powered on.

Abstract: A method delaying a pulse domain signal using a time encoder circuit and a time encoder based beamformer method and apparatus for use in receiving and/or transmitting applications.

Abstract: An airborne, gas, or liquid particle sensor with an on-board data acquisition system that can be used to capture detailed particle pulse information. The information can be used both for on-board analysis and reporting as well as off-line analysis and reporting.

Abstract: A servo processor for an optical disk drive is provided that includes: an analog-to-digital converter for converting versions of photodetector output signals into digital signals; and a digital signal processor configured to receive the digital signals, the digital signal processor being further configured to determine a focus error signal (FES) and a tracking error signal (TES) from the digital signals, the digital signal processor being further configured to process TES and FES through servo algorithms to produce tracking and focus control signals.

Abstract: An integrated circuit device comprises at least one digital to analogue converter module. The DAC module includes at least one current replicator component having a first channel terminal, a second channel terminal and a reference voltage terminal arranged to receive a reference voltage signal; the at least one current replicator component being arranged to moderate a current flowing between the first and second channel terminals based at least partly on the received reference voltage signal. The DAC module also includes at least one filter component coupled to the reference voltage terminal to perform filtering of the reference voltage signal.

Abstract: An A/D converter circuit includes a comparison circuit that performs a process to compare an added signal of a sampled signal of an input signal and a code signal with a D/A output signal, or a process to compare the sampled signal with an added signal of the D/A output signal and the code signal, a control circuit that outputs output data obtained based on successive approximation result data and the code data as A/D conversion data of the input signal, a first D/A converter circuit that D/A converts the data for successive approximation, a second D/A converter circuit that D/A converts code data that changes over time, and a correction section that performs a correction process, to correct the successive approximation result data so as not to overflow due to code shifting using the code data.

Abstract: Several circuits and methods for input offset control are disclosed. In an embodiment, a input offset control circuit includes a first input circuit and a second input circuit. The first input circuit is configured to operate within first common mode voltage range, configured to provide first input current, and configured to vary the first input current upon or subsequent to a variation of a voltage level in the first common mode voltage range. The second input circuit is coupled to the first input circuit and is configured to operate within second common mode voltage range, configured to provide a second input current, and configured to vary the second input current based on variation of the voltage level in the second common mode voltage range. Upon or subsequent to increasing the common mode voltage, the first input current is reduced and the second input current is increased.

Abstract: The present invention relates to an audio signal controller adapted to receiving first and second digital audio signals and estimating a signal feature of the first or second digital audio signal. The estimated signal feature is compared with a predetermined feature criterion and the audio signal controller switches from conveying the first digital audio signal to conveying the second digital audio signal to a controller output, or vice versa, at a zero-crossing of the first digital audio signal or the second digital audio signal based on the comparison between the estimated signal feature and the predetermined feature criterion.

Abstract: An apparatus includes a member configured to form an acoustic seal around a portion of an acoustic environment, and active noise reduction circuitry. The active noise reduction circuitry includes: detection circuitry configured to detect a change in pressure within the acoustic environment caused by movement of the member, and gain compensation circuitry configured to change a loop gain of a feedback loop in response to the detected change in pressure.

Abstract: A protection circuit includes: a first gain module, configured to receive a first input signal, scale the first input signal according to a first scaling factor, to obtain a first analog signal, receive a third scaling factor from a processing module, and scale the second input signal according to the third scaling factor, to obtain a second analog signal; an analog-to-digital converter, configured to convert the first analog signal into a first digital signal, and convert the second analog signal into a second digital signal; the processing module, configured to determine, according to a voltage value of the first digital signal and a preset scaling factor determining rule, the third scaling factor and a fourth scaling factor; and a second gain module, configured to scale the first digital signal according to a second scaling factor, and scale the second digital signal according to the fourth scaling factor.

Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

Abstract: In accordance with an embodiment, a method for operating a signal converter includes converting an analog input signal to a digital output signal, comprising by comparing the analog input signal to an analog comparison signal, and detecting whether the analog input signal exceeds a predetermined maximum or minimum threshold by comparing the analog input signal to an analog threshold signal. The analog comparison signal and the analog threshold signal are generated by a same digital-to-analog converter.

Abstract: A system and method for low-power digital signal processing, for example, comprising adjusting a digital representation of an input signal.

Abstract: In AD conversion of a voltage, data continuity is ensured between the results of conversion after amplification and of direct conversion without amplification. In AD conversion operation, an analog signal output from a DA converter circuit is directly converted by an AD converter circuit, and the analog signal is converted after amplification with an expected gain of 2?. Based on resultant data, a gain of an amplifier circuit and an offset thereof are calculated. An analog signal to be enhanced in bit precision is amplified by the amplifier circuit and converted by the AD converter circuit, the offset is subtracted from the resultant conversion, and the result is multiplied by a ratio of the expected gain to the calculated gain to cancel gain error. Based on data with gain error canceled, acquisition of bit-extended conversion result data is performed to ensure continuity between data having different degrees of bit precision.

Abstract: An A/D converter has an analog multiplexer stage which selects one of a plurality of first analog signals as a second analog signal, an amplifier stage which amplifies the second analog signal to generate a third analog signal, an A/D conversion stage which converts the third analog signal into a digital signal, and a sequencer which controls those stages. The sequencer performs input switching processing in the analog multiplexer stage on completion of sample hold processing by the A/D conversion stage, when performing a plurality of times of A/D conversion processing sequentially, without waiting for completion of the A/D conversion processing.

Abstract: An analog-to-digital conversion device has: an analog-to-digital converter configured to receive an input signal via an input signal node, and convert the input signal to a digital signal; and a control circuit configured to receive the digital signal when the input signal is set to have a fixed value, and change, when a deviation amount of the digital signal with the respect to an expected value is equal to or larger than a threshold value, a value of a capacitor between a power supply potential node and a reference potential node of the analog-to-digital converter and/or values of resistors connected to the power supply potential node and the reference potential node of the analog-to-digital converter.

Abstract: A wireless LAN communication device includes an amplifying circuit, an interference detection circuit, a false alarm counting circuit, and a control circuit. The amplifying circuit is configured to operably provide a gain to wireless signals. The interference detection circuit is configured to operably detect adjacent channel interference signals to generate a detection result. The false alarm counting circuit is configured to operably calculate a number of false alarms incurred by the adjacent channel interference signals. The control circuit is configured to operably configure the gain of the amplifying circuit according to the detection result and the number of false alarms.

Abstract: Imbalance and distortion cancellation for composite analog to digital converter (ADC). Such an ‘ADC’ is implemented using two or more ADCs may be employed for sampling (e.g., quantizing, digitizing, etc.) of an analog (e.g., continuous time) signal in accordance with generating a digital (e.g., discrete time) signal. Using at least two ADCs allows for the accommodation and sampling of various signals having a much broader dynamic range without suffering degradation in signal to noise ratio (SNR). Generally, the signal provided via at least one of the paths corresponding to at least one of the respective ADCs is scaled (e.g., attenuated), so that the various ADCs effectively sample signals of different magnitudes. The ADCs may respectively correspond to different magnitude and/or power levels (e.g., high power, lower power, any intermediary power level, etc.). Various implementations of compensation may be performed along the various paths corresponding to the respective ADCs.

Abstract: A signal receiving device and an electronic apparatus using the same are provided. The signal receiving device includes a signal conversion unit, a signal analysis unit, and an impedance unit. The signal conversion unit receives an analog input signal and converts the analog input signal into a digital input signal. The signal analysis unit receives the digital input signal and analyzes a signal characteristic thereof to generate an impedance adjustment signal. The impedance unit coupled to the signal analysis unit and a signal input terminal of the signal receiving device receives the impedance adjustment signal to dynamically adjust an input impedance of the signal input terminal. Thereby, the signal receiving device analyzes an input signal to dynamically adjust the input impedance of the signal receiving device, so as to maintain an amplitude gain of the input signal to be within a limited input range of the signal receiving device.

Abstract: A reception device and corresponding method for maintaining a high dynamic range of an AD converter circuit and preventing excessive input to the AD converter circuit is disclosed. For example, a reception device includes a variable gain amplifier circuit that amplifies an input analog signal with a gain controlled by a predetermined control signal, an analog-to-digital converter circuit an overload detector circuit with the same frequency characteristic as the analog-to-digital converter circuit. The overload detector circuit outputs a signal according to a comparison between a level of a signal input to the analog-to-digital converter circuit and a predetermined threshold. The signal that lowers the gain of the variable gain amplifier circuit more greatly is selected out of the signal from the overload detector circuit and another signal, and the gain of the variable gain amplifier circuit is controlled on the basis of the selected signal.

Abstract: Improved systems and methods for processing and recording audio received from one or more wired or wireless devices. In one aspect, the dynamic range of an analog-to-digital conversion system is extended. In another aspect, processes for generating a timecode, displaying and/or freezing a timecode display, and displaying an electronic timecode slate. Displaying a timecode slate may include rotating the orientation of the timecode display one hundred and eighty degrees to allow the timecode display to appear upright to individuals and/or equipment viewing and/or recording same. Displaying a timecode slate may also include an audible tone for synchronization of audio and video recordings.

Abstract: The present invention provides a data processing system which can increase resolution and which has excellent tracking with respect to the switching of a conversion range and is small in conversion error.

Abstract: The present invention relates to an audio amplification circuit comprising a first preamplifier for receipt of an audio input signal and a second preamplifier comprising a first differential input for receipt of an attenuated audio input signal. The attenuated audio input signal is generated by an attenuator coupled to the audio input signal. A non-linear element is coupled to a first input of the first preamplifier thereby distorting the audio input signal at the first input at large signal levels. A distortion compensation network is adapted to supply a distortion compensation signal from the first input of the first preamplifier to a second differential input of the second preamplifier such that distortion in the output signal of the second preamplifier is cancelled or attenuated. The invention further relates to a corresponding method of compensating an audio amplification circuit for distortion induced by a non-linear element.

Abstract: A threshold estimate system includes a level quantizer, a correlation mechanism, and a threshold adaptation component. The level quantizer is configured to receive an input signal and to generate a quantization signal from the input signal according to one or more threshold levels. The correlation mechanism is configured to correlate the quantization signal with reference symbols to generate an output signal. The threshold adaptation component is configured to modify the one or more threshold levels according to the output signal and the input signal.

Abstract: An analog-to-digital converter stage includes: a comparator and logic circuit having first upper and lower unscaled voltage trip points that are different than upper and lower residue voltage trip points; and a switched capacitor circuit. The comparator and logic circuit is configured prior to an initial residue calculation cycle to compare a magnitude of an unscaled input voltage to the first upper and lower unscaled voltage trip points, to generate an initial output bit, and to generate a voltage scaling and gain control signal. The switched capacitor circuit is configured to sample the unscaled input voltage, to receive a reference voltage, and to receive the voltage scaling and gain control signal for selectively controlling a subset of switches of the switched capacitor circuit to scale the unscaled input voltage sample and reference voltage and generate an initial residue voltage during a single operation of the initial residue calculation cycle.

Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

Abstract: A method and apparatus for controlling the effective gain of an ADC when the ADC is occasionally or continuously calibrated using the statistics of the input signal and when the statistics are not stationary.

Abstract: An audio downlink path is provided including a Dynamic Range Boost (DRB), a modified Digital-to-Analog Converter (DAC), and a modified audio driver gain control to produce a very high Dynamic Range (DR) while maintaining a limited scale and complexity of the components within the audio downlink path.

Abstract: An apparatus is provided. A comparison circuit is configured to receive an analog signal. A reference circuit is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC) is coupled to the comparison circuit. A timer is coupled to the comparison circuit. A rate control circuit is coupled to the conversion circuit. An output circuit is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal.

Abstract: A semiconductor device includes an analog front-end unit that performs analog front-end processing of a measurement signal input from a sensor, where circuit configuration and circuit characteristics for performing the analog front-end processing are changeable, and an MCU unit that converts the measurement signal after the analog front-end processing from analog to digital and sets circuit configuration and circuit characteristics to the analog front-end unit.

Abstract: A volume adjusting circuit which converts a digital audio signal to an analog signal by a D/A converter and outputs the analog signal includes: a first gain variable circuit unit which controls a gain of the digital audio signal; a second gain variable circuit unit which controls a gain of the analog signal output from the D/A converter; a storage unit which stores gain setting value; and a control unit which controls the gain of the first gain variable circuit unit and the gain of the second gain variable circuit unit based on the gain setting value stored in the storage unit, wherein the storage unit and the control unit are shared in controlling the first gain variable circuit unit and in controlling the second gain variable circuit unit.

Abstract: An analog-to-digital converter arrangement may include an analog amplifier with variable gain; an analog-to-digital converter; a digital reconstruction element including elements to reduce an influence of transients during a change of the variable gain of the analog amplifier.

Abstract: A stair-step voltage ramp module includes a stair-step voltage ramp generator circuit including at least one clocked first digital to analog converter (DAC) configured to receive digital data signals (codes) and a first clock signal and provide a first stair-step voltage ramp waveform. A programmable gain operational amplifier (op amp) has an input coupled to receive the first stair-step voltage ramp waveform. A second DAC being a current output, multiplying DAC is positioned to provide a gain setting resistance for the op amp. The second DAC and op amp configuration can be changed to provide gain or attenuation, or both. The output of the op amp provides a stair-step voltage ramp output suitable for applications including testing analog to digital converters (ADCs) having 10 or more bits.

Abstract: Techniques for adaptive gain adjustment in a signal processing path to achieve greater dynamic range. In an exemplary embodiment, a digital gain is applied to a digital input signal based on a detected level of the digital input signal. A corresponding analog gain is applied to the output of a digital-to-analog converter for converting the digital input signal to an analog signal, the product of the digital gain and the analog gain being kept constant. In an exemplary embodiment, a zero cross detector is employed to update the digital and analog gains only in the vicinity of zero crossings detected in the signal. In a further exemplary embodiment, a peak detector is employed to instantaneously adjust the digital and analog gains to avoid clipping in the signal path.

Abstract: A system and method for converting an analog detection signal of a magnetic resonance detection coil into a digital detection signal and for transmitting the detection signal to an evaluating device. In an embodiment, the detection signal is digitized by an analog-to-digital converter, decimated by a decimation filter, transmitted through a transmission route, then equalized by an equalizing filter.

Abstract: A DA converter includes a first DA conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second DA conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the DA converter, the gain control of the analog output signal generated by the first DA conversion section is performed on the basis of the gain control output signal generated by the second DA conversion section.

Abstract: Various embodiments of the present invention provide circuits, systems and methods for data processing. For example, a data processing circuit is discussed that includes: an analog to digital converter circuit, a target response circuit, and a timing circuit. The analog to digital converter circuit is operable to receive a data input and to provide corresponding digital samples synchronous to a sampling phase. The sampling phase corresponds to a phase feedback. The target response circuit is operable to provide an expected output corresponding to a known input. The timing circuit is operable to generate the phase feedback based at least in part on values derived from the expected output.

Abstract: Disclosed herein is a receiver, including: an amplifier for amplifying a received signal; a strain compensator for having a function of compensating for a strain generated in an output signal from the amplifier in accordance with a stain compensation amount which is controlled based on a bias signal from the output signal from the amplifier; and a stain compensation amount controlling portion for generating the bias signal and outputting the bias signal to the strain compensator so that the strain compensation is carried out with a compensation amount corresponding to a strength of the received signal.

Abstract: In accordance with an embodiment, a method includes determining an amplitude of an input signal provided by a capacitive signal source, compressing the input signal in an analog domain to form a compressed analog signal based on the determined amplitude, converting the compressed analog signal to a compressed digital signal, and decompressing the digital signal in a digital domain to form a decompressed digital signal. In an embodiment, compressing the analog signal includes adjusting a first gain of an amplifier coupled to the capacitive signal source, and decompressing the digital signal comprises adjusting a second gain of a digital processing block.

Abstract: A signal processing device includes amplifiers that are capable of amplifying detected signals using amplification factors that are different from each other; A/D converters that sample plural signals amplified by the amplifiers using the different amplification factors and output from the amplifiers; calculators that perform, on the basis of the amplification factors of the plural amplifiers, calculation on plural data pieces converted by the A/D converters; and a selector that selects one or more of output data pieces from among plural data pieces output from the calculators.

Abstract: Embodiments of the present disclosure provide a method and system for an auto-ranging analog-to-digital converter (ADC) for dynamically scaling inputs to an ADC. The auto-ranging ADC includes a dynamically configurable transistor arrangement for delivering a load current and a replica device for replicating the load current. A current sense resistor generates a replicated load voltage based on the replicated current. The ADC generates a digital value based on the replicated load voltage. The auto-ranging ADC also includes an auto-ranging controller for dynamically configuring the transistor arrangement based on the digital value to scale the inputs to the ADC.

Abstract: Examples are provided for converting an analog signal to a digital signal by processing more than one bit per cycle in a number of successive approximation cycles. A system may include capacitive sub-DAC circuits and comparators. Switches may isolate the capacitive sub-DAC circuits during one or more first cycles, and merge the sub-DAC circuits during one or more last cycles. A successive approximation register (SAR) may generate digital output signals or DAC digital signals. In another example, a system may include a DAC circuit. An input capacitor may be pre-charged to at least one of an analog input signal and a DAC analog signal. A programmable gain amplifier may amplify an error signal. A multi-bit ADC may convert the amplified error signal to a multi-bit digital signal. An SAR may use the multi-bit digital signal to generate a DAC digital signal or a digital output signal.

Abstract: In AD conversion of a voltage, data continuity is ensured between the results of conversion after amplification and of direct conversion without amplification. In AD conversion operation, an analog signal output from a DA converter circuit is directly converted by an AD converter circuit, and the analog signal is converted after amplification with an expected gain of 2n. Based on resultant data, a gain of an amplifier circuit and an offset thereof are calculated. An analog signal to be enhanced in bit precision is amplified by the amplifier circuit and converted by the AD converter circuit, the offset is subtracted from the resultant conversion, and the result is multiplied by a ratio of the expected gain to the calculated gain to cancel gain error. Based on data with gain error canceled, acquisition of bit-extended conversion result data is performed to ensure continuity between data having different degrees of bit precision.

Abstract: A precision charge dump circuit configured to transfer preset quanta of charge to or from a first capacitor (for example, an integration capacitor in an in-pixel ADC circuit). In one example, the charge dump circuit uses a second capacitor that is pre-charged with the preset quanta of charge to determine the preset value of the quanta of charge, and an amplifier in a voltage-follower mode to cause the charge subtraction or addition.

Abstract: Automatic gain control device for satellite positioning receivers characterized in that it comprises means for estimating the temporal occupancy rate of the pulses within the useful band, closed-loop control of the automatic gain control being applied in an optimal manner as a function of the said temporal occupancy rate, in such a manner as to reduce the influence of the pulsed interference within the band and out-of-band; notably, an AGC decision module returns a control signal for the attention of a non-linear function module applying a given weighting to the signals resulting from a comparison between the power or the amplitude of digitized input signals and a setpoint threshold value CAGC.

Abstract: An analog-to-digital conversion apparatus includes: a first analog-to-digital converter configured to convert an input analog signal into a digital signal; a second analog-to-digital converter configured to convert an analog signal generated by multiplying the input analog signal by ? times with a coefficient ? into a digital signal; a first non-linear compensation part configured to compensate a non-linear distortion of a first output signal of the first analog-to-digital converter; a second non-linear compensation part configured to compensate a non-linear distortion of a second output signal of the second analog-to-digital converter; and a non-linear detection part configured to estimate how much the non-linear distortions of the first and second analog-to-digital converters are compensated by the first and second non-linear compensation parts depending on first and second signals by the first and second non-linear compensation parts.

Abstract: It is possible to reduce a noise component mixed in an analog signal while suppressing increase of power consumption. An amplification unit amplifies the inputted analog signal and converts the amplified signal into a digital signal of a predetermined format for output. The amplification unit includes: an analog circuit unit for processing an analog signal; and a digital circuit unit for processing a digital signal; wherein the circuits are arranged on a substrate. The analog circuit unit includes: an amplification circuit for amplifying the inputted analog signal; and an LPF for cutting off a high frequency component of the amplified analog signal. The digital circuit unit includes: a rectification circuit which rectifies a waveform of the signal whose high-frequency component is cut off; and digital output circuit which converts the waveform-rectified signal into a digital signal of a predetermined format for output.

Abstract: An apparatus, protocol and methods for reducing vehicle energy consumption and for precise electronic event control, by implementing full CPU off-loading, using pulse-width modulation (PWM) with analog feedback diagnosis enabling real-time operation. Accordingly, analog feedback is used for external integrated circuits (IC) controlled by a PWM output, for processes to be analyzed. The apparatus includes a microprocessor that integrates an autonomous PWM module and an analog-to-digital converter (ADC) group manager, each including register modules for enabling analog-to-digital signal conversion comparisons of PWM feedback data, and generating of an interrupt command when required, and more specifically to automatically initiate transfer of data from the ADC to memory responsive of an interrupt trigger. As may be necessary the output of the ADC is calibrated or otherwise scaled to enable proper operation.