Abstract: A time to digital circuit may provide a time measurement of an event, or a time measurement of a duration between multiple events. Various electronic devices may include one or more time to digital circuits. A time to digital circuit may include circuitry to use Thermometer Code for measuring the duration of the time. For example, the time to digital circuit may generate alternating signals using a ring oscillator when receiving an indication of an event. Moreover, the time to digital circuit may convert the alternating signals to a consistent signal with only one transition between high and low signals in multiple consecutive signals. Furthermore, the time to digital circuit may correct erroneous signal values of the consistent signals when multiple transitions between high and low signals in multiple consecutive signals occurs.

Abstract: Disclosed herein are devices and methods to reduce unwanted CIM3 emission in a wireless communication device, such that the transmit (TX) power level applied in a RU can be increased without exceeding a regulatory emission requirement. In some aspects, unwanted emission may be reduced by shifting or changing local oscillator (LO) frequencies during TX operation. Some embodiments are directed to a fast-locking PLL with adjustable bandwidth that can be controlled to increase the PLL bandwidth during the RX to TX transition to provide a fast locking to a new LO frequency. Some aspects are directed to configuring an LO frequency shift amount for different RUs when multiple RUs are allocated within a frequency band.

Abstract: A multi-channel digital to analog converter, DAC, comprising: a DAC configured to provide an analog signal comprising a plurality of time division multiplexed sub-signals, each provided for one of a plurality of output channels; wherein each of the output channels include: a sampling capacitor; a selector switch configured to couple the sampling capacitor of the respective output channel to the output terminal of the DAC such that the sampling capacitor samples the analog signal over a plurality of discrete sampling periods; a comparator configured to provide a comparator output signal, wherein the sampling capacitor is coupled to an input terminal of the comparator; and an output control gate configured to control whether or not the comparator output signal is output from the respective output channel at a predetermined time later than a first of the respective plurality of discrete sampling periods.

Abstract: An apparatus for providing a supply voltage to a device under test includes a controlled source configured to provide a voltage in dependence on one or more control signals; a switchable resistor circuited between the output of the controlled source and a DUT port, having first and second resistances in first and second switch states, respectively, the second resistance being smaller than the first resistance; a regulator configured to provide a control signal to the controlled source, to regulate a voltage to be provided to the DUT in dependence on information about a desired voltage; a capacitor circuited in parallel to the switchable resistor at least during switching of the switchable resistor and configured to slow a voltage change across the switchable resistor which is caused by changing a switch state of the switchable resistor; the apparatus being configured to change a switch state of the switchable resistor while a voltage is provided to the DUT via the switchable resistor.

Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1141.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1141.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1141.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1141.1 circuitry in the interposer with 1141.1 circuitry in the die of the stack.

Abstract: A method and apparatus for simultaneously testing a component at multiple frequencies is disclosed. A digital processing circuit may generate a digital representation of a signal having a plurality of sine waves, each having a unique frequency. The digital representation may be converted into an analog signal, and applied to a device under test (DUT). A first analog-to-digital converter (ADC) may be coupled to measure voltages across the DUT, while a second ADC may be coupled to measure currents through the DUT. Voltage and current signals received by the first and second ADCs, respectively, may be converted into first and second digital values. Voltage and current values at each unique frequency are determined from the first and second digital values. Using the voltage and current values for each unique frequency, a frequency response of the component (e.g., an impedance) over a range of frequencies may be determined.

Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry. The DAC circuitry includes a first DAC circuit and a second DAC circuit. The first DAC circuit is configured to generate a first signal according to a plurality of least significant bits of an input signal. The second DAC circuit is configured to output a second signal according to a plurality of most significant bits of the input signal. A first turn-on time of at least one current source circuit in the first DAC circuit is configured to set the first signal.

Abstract: A circuit and a method for supplying a regulated voltage to a target circuit characterized by fast changes in current loading are described. A voltage regulator supplies the regulated voltage to an output node. A current loading circuit is connected to the output node of the voltage regulator. Logic causes the current loading circuit to apply a current load to the output node during a pre-loading interval starting in advance of an event that increases current loading in the target circuit and ending upon occurrence of the event. Logic is included to cause the current loading circuit to apply a current load to the output node during a post-loading interval starting upon occurrence of an event that decreases current loading in the target circuit.

Abstract: The embodiments of the present disclosure disclose a low dropout regulator and a method for controlling the same. The low dropout regulator comprises a control circuit configured to compare a output voltage with a first threshold voltage and a second threshold voltage, generate a first control signal when the output voltage is less than the first threshold voltage or greater than the second threshold voltage and a second control signal when the output voltage is greater than the first threshold voltage and less than the second threshold voltage; a digital regulator circuit configured to adjust the output voltage according to the first control signal and maintain the output voltage according to the second control signal; and an analog regulator circuit configured to output feedback current to the output terminal according to the output voltage and the reference voltage under the trigger of the second control signal.

Abstract: A body worn patient monitoring device includes a flexible substrate having a plurality of electrical connections adapted to be coupled to a skin surface to measure physiological signals. The flexible substrate is adapted to be directly and non-permanently affixed to a skin surface of a patient and configured for single patient use. A communication-computation module, removably attached to an upper surface of the flexible substrate, is configured to receive physiological signals from the flexible substrate and includes a microprocessor that is configured to process and analyze the physiological signals. A series of resistive traces screened onto the flexible substrate are configured as at least one series current-limiting resistor to protect the communication-computation module.

Abstract: A body worn patient monitoring device includes a flexible substrate having a plurality of electrical connections adapted to be coupled to a skin surface to measure physiological signals. The flexible substrate is adapted to be directly and non-permanently affixed to a skin surface of a patient and configured for single patient use. A communication-computation module, removably attached to an upper surface of the flexible substrate, is configured to receive physiological signals from the flexible substrate and includes a microprocessor that is configured to process and analyze the physiological signals. A series of resistive traces screened onto the flexible substrate are configured as at least one series current-limiting resistor to protect the communication-computation module.

Abstract: A data transmission method for a data transmission system including a first device and a second device is disclosed. The method comprises the steps of transmitting a clock signal to synchronize the first device and the second device; transmitting a mode signal from the first device to the second device, wherein the mode signal indicates a transmission mode between the first device and the second device; and transmitting a serial data between the first device and the second device based on the clock signal, wherein the length of the serial data is determined based on the transmission mode.

Abstract: A body worn patient monitoring device includes a flexible substrate having a plurality of electrical connections adapted to be coupled to a skin surface to measure physiological signals. The flexible substrate is adapted to be directly and non-permanently affixed to a skin surface of a patient and configured for single patient use. A communication-computation module, removably attached to an upper surface of the flexible substrate, is configured to receive physiological signals from the flexible substrate and includes a microprocessor that is configured to process and analyze the physiological signals. A series of resistive traces screened onto the flexible substrate are configured as at least one series current-limiting resistor to protect the communication-computation module.

Abstract: The detecting apparatus comprises: a monochromator, for Bragg-diffracting the incident beam; an analyzer, on which the beam diffracted by the monochromator is incident, an analyzer Bragg-diffracting the incident beam; a controller, for controlling the driver connected to the monochromator and the analyzer, so as to rotate the analyzer or the monochromator in a first direction and in a second direction opposite to the first direction; and a detector, for detecting the beam diffracted by the analyzer or transmitted through the analyzer while the analyzer or the monochromator is rotating and measuring a backlash and/or a slip of the driver by using the detected beam. The backlash detecting apparatus can measure a backlash and/or a slip in the unit of sub-arcsecond or sub-nanometer by using the radiation beam such as a neutron beam, an X-ray beam or the like.

Abstract: A body-worn physiological sensor includes a computation-communication module, and a flexible circuit layer configured to be coupled to a skin surface of a subject to measure physiological signals. An adhesive covers at least a portion of the flexible circuit layer and a protective covering protects the adhesive. The computation-communication module can be releasably attached to the sensor using electrical traces provided on the flexible circuit layer.

Abstract: A method, comprising: receiving an analog input; determining an upper outer rail and a lower outer rail as polling values to be used by voltage comparators; blanking at least three comparators; determining which two of the at least three comparators are closest to the input analog voltage levels; defining the two comparators which are closest to the analog input signal to be the next comparators of the next sampling process; assigning a remaining comparator at a voltage level in between the new top and bottom voltage levels; enabling the outer rails, but blanking the inner rail; progressively narrowing down the voltage range spanned by the two outer comparators; and generating a 2-tuple value of an asynchronous voltage comparator crossing.

Abstract: A driver for a switch includes a primary side having a trigger input and a secondary side comprising an analog-to-digital converter (ADC). The primary side and the secondary side are separated by a galvanic isolation barrier and communicate via a communication circuit. The primary side is configured to receive a trigger signal at the trigger input and forward the trigger signal to the ADC of the secondary side of the driver via the communication circuit. The ADC is configured to start a measurement upon receiving the trigger signal.

Abstract: A method for testing the material of a test object (8) in a nondestructive manner, said test object being moved relative to a probe (1) at a variable relative speed, comprises the following steps: detecting a probe signal (US) by means of the probe (1), subjecting the probe signal (US) to analog-to-digital conversion in order to generate a digitized probe signal (USD) in the form of a sequence of digital words with a predefined, in particular constant, word repetition rate, n-stage decimation of the word repetition rate of the digitized probe signal (USD) or of a digital demodulation signal (UM) derived from the digitized probe signal by means of n cascaded decimation stages (5_1 to 5_n), where n?2, selecting an output signal (UA_1 to UA_n) of one of the n decimation stages (5_1 to 5_n) depending on the instantaneous relative speed and filtering the selected output signal by means of a digital filter (7), which is clocked with the word repetition rate of the selected output signal.

Abstract: There is provided a delta-sigma A/D converter including a first integrator, a second integrator located on an output side of the first integrator, a quantizer located on an output side of the second integrator, and a first current D/A converter receiving an output of the quantizer and providing a negative feedback signal to an input side of the quantizer.

Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.

Abstract: Within a mechanical control system, continuous adaptive digital to analog control may control an analog actuated device by comparing a current value for a process variable to a setpoint value to obtain an error value, wherein the process variable may represent a monitored condition controlled by an analog actuated device. Continuous adaptive digital to analog control may also include converting the error value into a digital pulse time value representing a correction to compensate for the error value. The error value may be converted using a gain factor derived from timing characteristics for the actuated device. An analog value may be output based on a previously output value and the digital pulse time value. Continuous adaptive digital to analog control may repeatedly adjust the actuated device according to the changing values for the process variable.

Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. If the comparison result remains substantially the same for a predetermined interval, an ADC is enabled to generate a second comparison result at a sampling instant. A second time stamp that corresponds to the sampling instant is generated. The second comparison result and a second time stamp corresponding to the first comparison result are registered, and a second portion of the digital signal is generated from the second comparison result.

Abstract: An apparatus is provided. A comparison circuit is configured to receive an analog signal. A reference circuit is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC) is coupled to the comparison circuit. A timer is coupled to the comparison circuit. A rate control circuit is coupled to the conversion circuit. An output circuit is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal.

Abstract: An analog to digital converter includes: a first pulse delay circuit forming a multi-stage delay unit of which each delay unit have a pulse signal delayed with a delay time responding to an input voltage; a first encoding circuit that detects the number of delay units in the first pulse delay circuit through which the pulse signal passes during a predetermined measurement period, and outputs the AD conversion data based on the number of delay units; and a timing generation circuit which, in response to receiving the start signal, generates an end signal when the input voltage of the first pulse delay circuit is a specified voltage within an allowable input voltage range, in order to determine the measurement period which is a time required for the pulse signal to pass through a predetermined number of the delay units which is specified in advance.

Abstract: A digital receiver includes: an analog-to-digital (AD) converter (102) for setting discrimination levels in accordance with a discrimination level control signal and converting an analog input signal into a digital signal based on the set discrimination levels; a discrimination level adjusting circuit (104) for generating the discrimination level control signal and outputting the discrimination level control signal to the AD converter; a signal quality monitoring portion (108) for generating a transfer function correction control signal, which is information about a transfer function of the AD converter; and a transfer function correcting circuit (106) for performing signal processing on the digital signal so as to cancel a gap between the transfer function of the AD converter and an initial transfer function based on the transfer function correction control signal.

Abstract: Various embodiments of the present invention provide circuits, systems and methods for data processing. For example, a data processing circuit is discussed that includes: an analog to digital converter circuit, a target response circuit, and a timing circuit. The analog to digital converter circuit is operable to receive a data input and to provide corresponding digital samples synchronous to a sampling phase. The sampling phase corresponds to a phase feedback. The target response circuit is operable to provide an expected output corresponding to a known input. The timing circuit is operable to generate the phase feedback based at least in part on values derived from the expected output.

Abstract: An controller for use in a power supply includes a variable oscillator and a digital-to-analog converter (DAC). The variable oscillator generates a switching signal to control a first switch of the power supply to regulate an output current of the power supply. The variable oscillator sets a duration of an on-time of the switching signal to be inversely proportional to a magnitude of a first analog signal. The variable oscillator also sets a switching period of the switching signal to be inversely proportional to a magnitude of a second analog signal. The digital-to-analog converter (DAC) converts binary digits into the first and second analog signals, such that a sum of the magnitude of the first analog signal and the magnitude of the second analog signal is a fixed value.

Abstract: A system including a sample-and-hold circuit for receiving a plurality of analog input signals; an analog-to-digital converter for converting each of the analog inputs to a digital signal; and a processor configured for implementing fractional delay recovery for the analog-to-digital converter. In some embodiments, the fractional delay recovery includes converting each of the plurality of analog input signals to a digital version in the predetermined order; upsampling each digital version in the predetermined order; digitally filtering each upsampled value in the predetermined order; and downsampling each filtered value in the predetermined order.

Abstract: For calculating a fingerprint of an audio signal, the audio signal is divided into subsequent blocks of samples. For the subsequent blocks, one fingerprint value each is calculated, wherein fingerprint samples of subsequent blocks are compared. Based on whether the fingerprint value of a block is higher than the fingerprint value of a subsequent block or not, a binary value is assigned, wherein information about a sequence of binary values is output as fingerprint for the audio signal.

Abstract: Embodiments of the present disclosure provide a method and system for an auto-ranging analog-to-digital converter (ADC) for dynamically scaling inputs to an ADC. The auto-ranging ADC includes a dynamically configurable transistor arrangement for delivering a load current and a replica device for replicating the load current. A current sense resistor generates a replicated load voltage based on the replicated current. The ADC generates a digital value based on the replicated load voltage. The auto-ranging ADC also includes an auto-ranging controller for dynamically configuring the transistor arrangement based on the digital value to scale the inputs to the ADC.

Abstract: A source-measure unit (SMU) may be implemented with digital control loops. The output voltage and output current may be measured with dedicated ADCs (analog-to-digital converters), and the readings obtained by the ADCs may be compared to a setpoint in a digital loop controller, which may produce an output to drive a DAC (digital-to-analog converter) to maintain the output voltage and/or output current at a desired setpoint. The digital loop controller may also digitally implement simulated resistance with high resolution, accuracy, and range, using Thévenin and Norton power supply models. Simulated resistor values may range from 10? to 10? for output currents in the 100 mA range, with a sub-200?? resolution. The range may be expanded up to 100 k? for output currents in the 10 ?A range. The Norton and Thévenin implementations may be combined, and a “pure resistance” mode may be created for simulating any desired resistance value.

Abstract: In order to suppress the enlargement of the circuit layout area of an LSI together with the cost, even at the time when the variation width of the filter characteristic is narrow within a wide range, a filter varies an element value of at least one kind of elements (3), which determine a filter characteristic of the filter circuit, according to an output of the sigma-delta modulator (1), which sigma-delta modulates a digital code input (Code), according to an operation clock (CLK), or according to a signal through a decoder (4), which performs a code-conversion to an output of the sigma-delta modulator (1).

Abstract: An controller for use in a power supply includes a variable oscillator and a digital-to-analog converter (DAC). The variable oscillator generates a switching signal having an on-time and a switching period to control a first switch to regulate an output of the power supply. The DAC provides the variable oscillator with a first analog signal and a second analog signal, where the on-time of the switching signal is responsive to the first analog signal and where the switching period is responsive to the second analog signal. The DAC includes a current source and a second switch that is configured to couple the current source to provide current to the first analog signal in response to a binary digit received by the DAC, and to couple the current source to provide current to the second analog signal in response to a complement of the binary digit.

Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

Abstract: A power supply apparatus is provided for a test apparatus configured to supply a power supply signal to a DUT. An A/D converter performs analog/digital conversion of an analog observed value that corresponds to a power supply signal so as to generate a digital observed value. A digital signal processing circuit generates, by means of digital processing, a control value adjusted such that the digital observed value received from the A/D converter matches a predetermined reference value. A D/A converter performs digital/analog conversion of the control value, and supplies the resulting value to the DUT as the power supply signal. A digital signal processing circuit is configured to be capable of changing the content of its signal processing.

Abstract: A non-linear amplifier is linearized using interpolation-based digital pre-distortion (DPD). In one embodiment, the digital input signal is interpolated to generate a higher-sample-rate signal that is then pre-distorted. The resulting higher-sample-rate pre-distorted signal is then decimated to generate a final pre-distorted digital signal that is converted into an analog pre-distorted signal by a digital-to-analog converter (DAC) before being applied to the amplifier. In a polyphase embodiment, different versions of the original input digital signal are generated, where each version is then pre-distorted using a different DPD module to generate a different intermediate pre-distorted digital signal. The intermediate pre-distorted signals are filtered and combined to generate the final pre-distorted digital signal. In both embodiments, better linearization (e.g.

Abstract: A signal-linearization system and method reduces nonlinear distortions in a digitized signal generated by an analog-to-digital converter (ADC) when converting an analog input signal from analog to digital form. A signal adder adds a dither waveform to the analog input signal. An ADC includes sample-and-hold (S/H) circuitry and quantizer circuitry. The ADC converts the analog input signal with the added dither waveform into a digitized signal. The dither waveform operates to suppress nonlinear distortions attributed to the quantizer circuitry. A linearizer processor performs nonlinear equalization (NLEQ) on the digitized signal to suppress nonlinear distortions attributed to the S/H circuitry. A dither waveform removal module removes a digital counterpart of the dither waveform from the digitized signal.

Abstract: A radio apparatus capable of correcting a direct current offset with high accuracy in a short time is provided. A radio apparatus according to an embodiment includes a first amplifier amplifying a signal inputted to an input terminal with amplification gain determined by a variable resistor to generate a first amplified signal, and a second amplifier amplifying the first amplified signal to generate a second amplified signal. Further, the radio apparatus includes a first correcting unit correcting a direct current offset of the first amplifier, and a second correcting unit correcting a direct current offset of the second amplifier.

Abstract: An electronic device and a method for driving an internal function block of a processor of the electric device to operate in a linear region. The electronic device comprises a processor having two multiple purpose pins (MPP1 and MPP2), an external device connection port, and two resistance elements. The external device connection port is further connected to the MPP1 and at a tested voltage. The first resistance element is connected between a high level voltage and the external device connection port. The second resistance element is connected between the external device connection port and the MPP2. The processor is configured to output the high or low level voltage at MPP2 when the tested voltage is in a non-linear operating region, to guarantee the tested voltage to a linear operating region of the function block which is coupled to the MPP1 by a multiplexing design.

Abstract: A source-measure unit (SMU) may be implemented with respective digital control loops for output voltage and output current. The digital control loop associated with the output that is being regulated may be the setpoint control loop while the digital control loop associated with the other output may be the compliance control loop. The digital loop controller may switch between the setpoint control loop and the compliance control loop without generating a mode-change glitch, by maintaining a single integrator. The compliance methods may differ in how and when the decision is made to select which of the measured signals provides the error signal to the integrator. Thus, there may be no issue with integrator wind-up, which might be the case if there were two complete control loops operating continuously.

Abstract: A voltage reference circuit provides a precision voltage reference output without requiring a filter capacitor. The voltage reference output is generated by a digitally-controlled source, which has a value set by the output of a digital filter that filters the output of a comparison circuit that compares the voltage reference output to another reference. A selectable mode can be provided to provide a fast response during a startup/reset period and an optional hold or narrowband response after startup. The mode selection may also offer selection of an externally-supplied digital control value and/or a resistor divider type voltage reference as an alternative to the digitally-controlled source.

Abstract: A heater controller for controlling a heater precisely in the equi-power mode is disclosed. The controller includes a current source, a voltage monitor to detect a voltage drop caused in the heater, and a controller. The voltage drop may be converted to the digital form as refereeing to the first reference, while, the heater current is converted from the digital form as referring to the second reference. The second reference shows substantial temperature dependence, while, the first reference has lesser temperature dependence. The control corrects the temperature dependence of the second reference as referring to the first reference.

Abstract: A detecting device has: a detecting element to which a first constant voltage is applied; a resistance element connected to the detecting element; a switching element having a first terminal to the resistance element, a second terminal controlled to a second constant voltage lower than the first constant voltage, and a control terminal sets the first terminal and the second terminal in a conducting state; a control unit, according to a conducting/non-conducting state, controls voltage to the control terminal to maintain a potential difference between the detecting element and the resistance element; and an AD converter converting, into a digital value, a potential of a potential difference between the first constant voltage and the first terminal being voltage-divided at the detecting element and the resistance element to the detecting element, a first reference potential is the first constant voltage, and a second reference potential is voltage to the first terminal.

Abstract: A 4× over-sampling data recovery system consists of a charge pump PLL, a 4× over-sampler, a data regenerator and a digital PLL. The charge pump PLL receives a clock signal and generates a plurality of multiplicative clock signals in response to the clock signal. The 4× over-sampler samples a serial data to generate a M-bit signal according to the plurality of multiplicative clock signals, wherein each bit in the serial data is sampled for four times. The data regenerator sequentially receives and combines two M-bit signals to generate a (M+N)-bit signal. The digital PLL divides the (M+N)-bit signal into (N+1) groups of M-bit data and selects a designated M-bit data from the (N+1) groups of M-bit data to generate a P-bit recovery data.

Abstract: An electronic circuit for correcting at least one digital measurement signal (??n, ??1, ??2) comprising at least one measurement channel having a sigma-delta modulator and a correction circuit. The sigma-delta modulator changes an analog measurement signal into a digital measurement signal in the form of a binary value sequence. The correction circuit corrects the digital measurement signal (??n, ??1, ??2) as a function of at least one correction datum (trim), wherein the correction circuit comprises at least one adding element and at least one multiplexer. The digital measurement signal is corrected in that the correction datum (trim) is weighted by means of the multiplexer and the adding element as a function of the digital measurement signal (??n, ??1, ??2).

Abstract: A video encoding apparatus receives a digital video data signal, converts the digital video data signal into an analog video signal and outputs the analog video signal to an externally connected image device. An encoding processor converts the digital video data signal into the analog video signal. A resolution determination unit compares the resolution of an image represented by the digital video data signal with an externally defined resolution. An output controller refers to a result of comparison by the resolution determination unit and, if the externally defined resolution matches the resolution of the image represented by the digital video data signal, outputs the analog video signal. If the resolutions do not match, the output controller restricts the output of the analog video signal.

Abstract: An analog-digital converter for converting an analog signal into a digital signal includes a first configuration register for configuring a first group of channels and a second configuration register for configuring a second group of channels. The conversion result of the channels of the first group is transferred to a memory via a direct memory access. Each channel of the second group of channels has an associated respective data register and the conversion results of the channels of the second group are stored in the respective data registers.

Abstract: An apparatus, protocol and methods for reducing vehicle energy consumption and for precise electronic event control, by implementing full CPU off-loading, using pulse-width modulation (PWM) with analog feedback diagnosis enabling real-time operation. Accordingly, analog feedback is used for external integrated circuits (IC) controlled by a PWM output, for processes to be analyzed. The apparatus includes a microprocessor that integrates an autonomous PWM module and an analog-to-digital converter (ADC) group manager, each including register modules for enabling analog-to-digital signal conversion comparisons of PWM feedback data, and generating of an interrupt commands when required.

Abstract: This disclosure provides power supply control methods and apparatus. According to one aspect of the disclosure, a method of operating a power supply operatively connected to a developer unit associated with a printing apparatus is disclosed. The method includes generating a modified output control signal as a function of stored gain and offset values associated with the power supply to generate a desired output voltage to drive the developer unit.

Abstract: According to an embodiment, an analog-to-digital converter (ADC) including an ADC unit, a clock-phase control unit, a multiplexer, and a digital-output processing unit is provided. The digital-output processing unit inputs digital outputs of the ADC unit to either an averaging circuit or the multiplexer depending on the specified conversion speed and the specified conversion accuracy, or inputs the digital outputs of the ADC unit to the averaging circuit and the multiplexer in this order, and outputs ADC digital signals with the specified conversion speed and the specified conversion accuracy.