Abstract: An apparatus and method are described to increase the control resolution of an electronic device. In one embodiment, the invention includes a spread pulse modulation module to generate a first set of bits based on a second set of bits that is larger than the first set of bits. The spread pulse modulation module modulates the least significant bit (LSB) of the first set of bits based on information including the LSB modulation period and the LSB modulation duty cycle. The spread pulse modulation module also modulates the least significant bit of the first set of bits so that the least significant bit transitions at least twice from a high value to a low value during the modulation period. This embodiment of the invention also includes a digital-to-analog conversion module to generate an analog input signal to the electronic device based on the first set of bits.

Abstract: An optically sampling device optically samples an optical analog signal using a sampled signal having a predetermined sampling frequency, and outputs control light having a pulse train of an optically sampled optical analog signal. A signal generating device generates a pulse train of signal light which is synchronized with the sampled signal. An optical encoding device optically encodes the pulse train of the signal light according to the control light, by using optical encoders each including nonlinear optical loop mirrors, and outputs pulse trains of optically encoded signal light from said optical encoders, respectively. An optically quantizing device performs optical threshold processing on the pulse trains of optically-encoded signal light to optically quantize them, by using at least one of optical threshold processors each of which is connected to each of said optical encoders and includes a nonlinear optical device, and outputs optically quantized pulse trains as optical digital signals.

Abstract: A signal selecting circuit is disclosed which outputs a first and a second digital signals by converting a first and a second analog signals into digital signals, the first and the second analog signals being the same or different signals selected from a plurality of analog signals, the signal selecting circuit comprising: an analog signal selection circuit that, based on an analog selection signal, selects the first and the second analog signals from the plurality of analog signals; a first AD converter that converts the first analog signal outputted from the analog signal selection circuit into a third digital signal to output the third digital signal; a second AD converter that converts the second analog signal outputted from the analog signal selection circuit into a fourth digital signal to output the fourth digital signal; a digital signal selection circuit that, based on a digital signal, selectively outputs one or both of the third and the fourth digital signals as the first and the second digital sig

Abstract: A voltage conversion device having non-linear gain and changeable gain polarity includes a switch module, a gain decision module, a first voltage selection module, a second voltage selection module, a first switch unit, a second switch unit and a voltage output module. The switch module is used for outputting analog voltage provided by the analog voltage source or voltage corresponding to the system ground end. The gain decision module is used for determining a gain. The first voltage selection module is used for outputting a first DC voltage. The second voltage selection module is used for outputting a second DC voltage. The first switch unit is used for outputting the first DC voltage. The second switch unit is used for outputting the second DC voltage. The voltage output module is used for outputting an amplified result of a DC voltage according to the gain.

Abstract: The present system provides a method for varying the value of passive components in electronic circuits. Passive components can range from basic resistors, capacitors, and inductors to complex, structures such as transmission lines and resonant cavities. Value selection and variation can either be dynamically performed during circuit operation or as a one-time part of the manufacturing process as determined by the requirements of the specific application. A digital-to-analog converter (DAC) circuit is used to input value selection data digitally, and control value selection with value resolution dependent on the resolution of the DAC. An alternate embodiment is provided for high frequency operation.

Abstract: A phase detection apparatus and method, a PLL circuit and a control method thereof, and a signal reproducing apparatus and method which can provide anti-noise and anti-ISI characteristics while reducing the scale of hardware used in an optical disc reproducing system having high-ISI conditions include a pulse forming unit to detect binary data of an input signal, an ideal input signal generating unit to generate an ideal input signal based on the detected binary data, and a phase error signal generating unit to generate a phase error signal based on the input signal and the ideal input signal.

Abstract: An integrator circuit (110) is provided including an amplifier element (170) configured to receive an input signal at an input node, amplify the input signal, and provide an amplified input signal at an output node; a feedback capacitor element (175) connected between the output node and the input node; and a current matching circuit (120) connected to the output node, and configured to sense an output voltage of the amplifier element and to provide a supplemental current (IM) to the input node that is less than or equal to a feedback current (IF) charging the feedback capacitor element. This supplemental current is substantially equal and opposite in polarity to a feedback current when the output voltage satisfies a set criterion.

Abstract: A system and method implement very high data rate baseband DACs suitable for wireless applications related to new standards (e.g. Ultra-Wide Band) using CMOS processes allowing an integrated solution with the deep-submicron CMOS digital baseband. A single CMOS block working at full speed is discarded in favor of several blocks, each working at a fraction of the original data rate.

Abstract: A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each sample-and-hold circuit in a first group of N sample-and-hold (S/H) circuits is connected to a corresponding output of the analog demultiplexer. Similarly, each S/H circuit in a second group of N S/H circuits is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the S/H circuits in the first group and a second input connected to an output of a corresponding one of the S/H circuits in the second group.

Abstract: An output voltage of a VDC circuit is subjected to A/D conversion with an on-chip A/D converter. Accordingly, an output voltage VDCout of the VDC circuit can be observed as a digital value, which facilitates measurement. Reduction in the number of terminals leads to reduction in chip size. In addition, the terminal that has been used for providing voltage VDCout can be used for other purposes. Therefore, a semiconductor integrated circuit allowing for easy mass production test and reduced number of man-hours in the mass production test can be provided.

Abstract: A system-on-a-chip (SOC) in CMOS technology capable to support high voltage applications has been achieved. The single chip system of the present invention comprises high-voltage circuitry, a complete micro-controller system including all timing control, interrupt logic, flash EEPROM program memory, RAM, flash EEPROM data memory and I/O necessary to implement dedicated control functions, and a core and system peripheral bus. A preferred embodiment of the invention is shown driving a DC-motor in a H-bridge configuration, having an AMR-position detection and control. A pulse width modulation (PWM) is applied to high-voltage (30 to 60 Volts or in lower ranges less than 30 Volts) CMOS buffers for steering CMOS-FETs or relays of the motor H-bridge.

Abstract: A servo system comprising an analog sigma delta modulator for generating a normalized digital error correction signal from first and second analog control signals. The sigma delta modulator comprises an analog low-pass filter, a quantizer delivering the digital error correction signal and a multiplying DA-converter in feedback arrangement between the output of the quantizer and the input of the low-pass filter for multiplying the feedback signals with the sum of the analog control signals.

Abstract: A filter using analog to digital conversion, digital filtering and oversampling noise reshaping is disclosed. Application of such a filter to a frequency locked oscillator is disclosed. Application of such a filter to an oscillator having a capability to synchronize with an external stimulus is disclosed.

Abstract: An integrated circuit for generating a bandgap reference voltage (VBG) includes a first circuit and a second circuit. The first circuit includes an op-amp for equalizing emitter currents of a first bandgap transistor and a second bandgap transistor. The second circuit trims out error in at least one emitter current to achieve a desired frequency tolerance. The second circuit includes at least a single transistor digital to analog converter (DAC).

Abstract: An A/D converter includes a first DC bias circuit and a second DC bias circuit with the same configuration and characteristic, the first and second DC bias circuits generate first and second common voltages with the same voltage level independently in response to a feedback control voltage supplied from an operational amplifier. The operational amplifier controls the first and second DC bias circuits in such a manner that the second common voltage fed from the second DC bias circuit via a second input buffer matches to the common voltage of the reference voltages of an AD core. This enables the first common voltage, which is generated by the first bias circuit and superimposed onto the analog input signal through the first input buffer, to be matched to the common voltage of the reference voltages of the A/D core.

Abstract: In a sigma-delta modulator the feedback circuit (4, 5) has an adjustable feedback factor controlled by an adjusting member (6) for adjusting the feedback factor of the feedback circuit.

Abstract: An apparatus including a plurality of quantizers each configured to compare a selected threshold signal with an input signal and generate an output, a multiplexer, coupled to the plurality of quantizers, that selects one of the plurality of quantizer outputs according to a frequency response, and a multiplication-accumulation (MAC) unit, coupled to the multiplexer, the MAC to generate an output based on a previously selected one of the quantizer outputs according to the frequency response.

Abstract: A serial-deserializer converts a high speed serial data input to a lower speed parallel output. By including this circuit on a chip, connections to the chip are made more easily. A gated voltage controlled oscillator provides clock signals to sample the data input at a high rate. The output signals are thus provided at a slower rate.

Abstract: A reference generator includes a memory that stores reference data which, when clocked out of the memory, produces an ATSC compliant VSB reference signal substantially free of sub-harmonics of the clock signal. A digital-to-analog converter converts the clocked out reference data to an analog signal. The analog signal may be at low IF. An up converter is arranged to upconvert the output of the digital-to-analog converter to an RF reference signal. The RF reference signal can be used, for example, to calibrate a VSB demodulator.

Abstract: A fail-safe fluid transfer control apparatus has full redundancy in the response to various inputs such as overfill probe signals, ground detection signals, and the like. Independent microprocessor controllers independently evaluate the inputs and each output control signals to close a respective relay when the inputs indicate that fluid transfer may commence. The relays are arranged in series such that both must be closed for a fluid transfer to commence. The control signals from each controller include a static signal and an alternating signal, both of which must be properly output to close its respective relay. Each controller monitors the state of each relay, and discontinues its control signals if either relay appears to be malfunctioning. Each controller runs an different, independently written firmware program to process the detected inputs to prevent a common firmware error.

Abstract: A clock-to-clock auto-ranging ADC operates directly on an analog signal in the IF band or higher to track its gain range on a clock-to-clock basis and produce a digital signal that maintains high resolution of the analog signal without clipping or loss of signal sensitivity. This is accomplished by sampling an analog signal of sufficiently high frequency that a peak detector can accurately determine the maximum signal level over at least one-half a signal period and then reset the signal gain going into the ADC prior to the beginning of the next sampling period. This insures that the analog signal will always be within the range of the ADC. In accordance with the well known principles of sampling theory, the sampled analog signal is aliased into the frequency region between DC and one half the sampling frequency.

Abstract: This analog-digital conversion device comprises switching means (CS) having two close and centered triggering thresholds; a NOR logic gate (PL) which, when the conversion device is not being used, receives a standby command signal and delivers a zero digital output signal (NOUT) imposed on the input (NIN) of the switching means (CS); preamplification means (PS); and amplification means (AS) receiving a standby command signal and delivering either the digital output signal (NOUT), in the absence of a standby command, or a zero-value signal in the event of a standby command.

Abstract: In a semiconductor integrated circuit device having an A/D converter incorporated therein, a plurality of input channels are provided and input analog signals supplied therefrom are respectively held by a plurality of sample-to-hold circuits. The analog signals are simultaneously sampled by using such a pipeline operation that a first sampling is performed so that an analog signal held by the first sampling is A/D-converted and a second sampling is performed so that an analog signal held by the second sampling is A/D-converted, and the plurality of sample-to-hold circuits.

Abstract: An apparatus and a method for controlling a mode of operation of a data converter is based on a length of an input word signal to the data converter. The apparatus includes a bit counter that counts the number of bits in the word received by the data converter and provides a word length signal corresponding to the number of bits in the word, and a mode selector that receives the word length signal and selects an operational mode of the data converter based on the word length signal. The method includes steps of counting the number of bits in the word, and selecting a mode of operation of the data converter based on the number of bits in the word.

Abstract: A trigger system for a digital oscilloscope operating in external clock mode. Every n pulses, the trigger system generates a trigger signal. The trigger system therefore provides a trigger every n samples of the input signal waveform.

Abstract: A circuit for balancing an error signal delivered by an apparatus. When the apparatus is switched on initially, the error signal may be large and thereafter change only slowly with time. The error signal may be a signal which is delivered by a measuring sensor and which is independent of the quantity to be measured. The circuit includes a negative feedback loop 7, 11 which, immediately upon activating or starting the apparatus, feeds back a balancing signal which rapidly compensates the error signal. The circuit also includes components 12-16 for changing the feedback loop when the error signal has been substantially compensated, so that only slow changes in the error signal with a frequency below a selected upper limit frequency are fed back.

Abstract: A semiconductor microcontroller includes the capability to perform analog to digital conversions of an analog signal representative of a variable parameter indicative of the need to exercise a control function. While the analog to digital conversions are being performed, the microcontroller processor can be powered down to eliminate noise arising from switching activities of the processor as a source of inaccuracy in the conversion process. At the end of the conversion, the analog to digital converter can either shut itself down or wake up the processor. The powering down is achieved by simply disabling the clock input to the microcontroller so that the processor is still activated but incapable of undergoing switching functions.

Abstract: A semiconductor microcontroller includes the capability to perform analog to digital conversions of an analog signal representative of a variable parameter indicative of the need to exercise a control function. While the analog to digital conversions are being performed, the microcontroller processor can be placed in a sleep mode which eliminates noise arising from switching activities of the processor as a source of inaccuracy in the conversion process. At the end of the conversion, the analog to digital converter can either shut itself down or wake up the processor. Alternatively, the converter may shut itself down in response to a different user selected control signal.

Abstract: A method for operating an apparatus for facilitating communications between an analog device and a digital device, which apparatus includes a plurality of signal processing circuits and a control circuit for controlling the signal processing circuits. Each of the signal processing circuits includes signal attenuators and signal burst discrimination circuitry. The apparatus is operable in a plurality of stable states, preferably in an idle stable state, a transmit stable state, and a receive stable state. The apparatus also is operable in a plurality of transitional states, including up-transition states and down-transition states.

Abstract: The invention relates to a phase-locked loop comprising a phase detector (PD), an analog-to-digital converter (ADC), a loop filter (LF), a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO). The phase jitter that occurs in such a hybrid phase-locked loop is reduced without enhancing the requirements as to the resolution of the digital-to-analog converter (DAC), in that a fractionizer (FR) is inserted after the loop filter (LF) that is operating at a first clock (TL), which fractionizer produces a main value (HW) and a residual value (RW), and the sum (SW) of the main value (HW) and a correction bit (KB) derived from the residual value (RW) is applied to the digital-to-analog converter (DAC) that is operating at a second clock (TA).

Abstract: A digital-to-analog converter system includes a logic system which receives input signals, receives an increment/decrement signal, and provides a digital word composed of most significant bits and least significant bits. The system includes two DACs haaving separate data rates and ranges for converting the most significant bits and the least significant bits, respectively, the data rate of the second DAC being greater than the data rate of the first DAC. Combining circuitry produces an analog signal representative of the digital word from the first and second analog outputs. The data rate of the combined output may be as fast as the data rate of the second DAC, and the range of the combined output may be as large as the range of the first DAC. The system also includes track and hold circuitry which holds the value of the output of the first DAC until glitches are settled.

Abstract: An arrangement for generating mean-value-free binary signals includes a binarizing circuit which receives an analog signal to be binarized and binarizes said signal with respect to a binarizing threshold. Connected to the output of the binarizing circuit is a closed-loop control circuit which includes a differential integrator which receives at the one input the binary signal from the output of the binarizing circuit. Applied to the second input of the differential integrator is a desired value signal which corresponds to the mean value between the two signal levels of the binary signal. The differential integrator integrates the deviation between the binary signal and the desired value signal and furnishes a signal corresponding to the integrated deviation. By the signal corresponding to the integrated deviation the position of the analog signal relatively to the binarizing threshold is shifted in a sense such that the mean value of the deviation is regulated to zero.

Abstract: A programmable logic and analogic integrated device comprises a programmable logic section capable of constituting by programming a state machine which beside producing outpout logic signals in function of input logic signals may drive a digital-analog converter (DAC), the analog signal generated by which is managed as well as other analog signals which may be respectively fed to a number of analog input pins of the integrated device by the said programmable state machine by means of a plurality of integrated analog switches which also permit the output of the analog signal generated by the DAC through a buffered analog output pin of the device. An integrated comparator (zero-crossing detector) provides a comparison between two distinct external analog signals or between an external analog signal and the analog signal generated by the DAC for producing an output logic signal which may be fed to an input of the state machine for implementing a certain interaction function.

Abstract: A multiple channel data acquisition system for the transfer of large amounts of data from a multiplicity of data channels has a plurality of modules which operate in parallel to convert analog signals to digital data and transfer that data to a communications host via a FASTBUS. Each module has a plurality of submodules which include a front end buffer (FEB) connected to input circuitry having an analog to digital converter with cache memory for each of a plurality of channels. The submodules are interfaced with the FASTBUS via a FASTBUS coupler which controls a module bus and a module memory. The system is triggered to effect rapid parallel data samplings which are stored to the cache memories. The cache memories are uploaded to the FEBs during which zero suppression occurs. The data in the FEBs is reformatted and compressed by a local processor during transfer to the module memory. The FASTBUS coupler is used by the communications host to upload the compressed and formatted data from the module memory.

Abstract: An arrangement for setting an analog resistor to a value which is digitally predetermined. The arrangement contains a resistor (2) which is variable by a control voltage as setting member of a control circuit, in series with a measurement resistor (3) and a rotary-magnet ratio meter (26). This series connection is fed from an operating voltage. The voltage at the measurement resistor (3) and the digital value are each fed to inputs of a multiplier (5) the outputs of which are connected via a digital/analog converter (6) to an input of a subtraction circuit (7). The other input of the subtraction circuit (7) is acted on by a reference voltage. The output of the subtraction circuit (7) produces the control voltage for the adjustable resistor (2).

Abstract: An addressable transducer interface which may be associated with a particular electrical transducer, comprises means (107) for storing correction data for the correction of errors as herein defined relating to that transducer so that on addressing of the interface by external control means, the correction data may be transmitted to the control means together with measurement data from the transducer. The storing means is arranged to store said correction data in digital form.