Abstract: A digital direct conversion receiving apparatus, including: a phase conversion unit to down-convert a Radio Frequency (RF) signal into a plurality of sample signals, and generate a certain phase difference among the plurality of sample signals when the RF signal is down-converted; and a variable complex gain unit to remove an image component from the plurality of sample signals using the generated phase difference.

Abstract: A control circuit for a multi-phase converter including an analog front-end circuit for receiving and processing an output voltage and current of the converter circuits and an average output current; a digital circuit for producing an output voltage reference for setting a desired output voltage of the converter; and an error circuit for comparing the output voltage reference and a parameter related to said output voltage and current for generating control signals for controlling the converter circuits, said error circuit including an Analog to Digital Converter circuit, further comprising a digital PWM generation circuit controlled by said Analog to Digital converter circuit for generating digital control signals for controlling the converter circuits.

Abstract: A voltage regulator uses a digital feedback technique to regulate the voltage at an output of the regulator. The voltage level of an output signal is measured. The voltage level of the output signal is compared to a first reference voltage. A programmable digital control logic block regulates the voltage level of the output signal and operates in a first mode if the voltage level of the output signal is above a first reference voltage and in a second mode if the voltage level of the output signal is below the first reference voltage. Depending on the mode of operation, the programmable digital control logic block provides digital control signals to other elements of the feedback loop.

Abstract: A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.

Abstract: An example digital-to-analog converter (DAC) for a power supply controller includes a first node, a second node, a current source, and a switch. The first node is to be coupled to provide a first analog signal to a variable oscillator of the power supply controller. The second node is to be coupled to provide a second analog signal to the variable oscillator of the power supply controller. The switch is coupled to the current source and configured to couple the current source to the first node to provide current to the first analog signal in response to a binary digit received by the DAC, where the switch is further configured to couple the current source to the second node to provide current to the second analog signal in response to a complement of the binary digit.

Abstract: A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of “L” in synchronous with the output control clock.

Abstract: A controller receives an M-bit input and generates, in response, an S-bit upper range binary data feeding S-bit high range DAC and an R-bit lower range data feeding an R-bit low range DAC. The controller detects transition points in the M-bit input and in response, adds a transition data to the S-bit data equal to at least one least significant bit of the S-bit data and subtracts a value from the R-bit data equal to the transition data. The transition points and the transition data are detected and added at points avoiding such transitions at a full scale value of the R-bit data.

Abstract: A switched capacitor measurement circuit is provided for measuring the capacitance of an input capacitor with a parallel parasitic resistor. The circuit comprises a switching arrangement, a reference capacitor, a steered current sink and an operational amplifier with an output, a non-inverting input connected to a reference voltage source and an inverting input connected to a first terminal of the input capacitor. The current sink is steered to compensate for a charge current due to the parasitic resistor. Still further, the circuit comprises a digital adder and an analog-to-digital converter with an analog input connected to the output of the operational amplifier and a digital output connected to a first input of the digital adder.

Abstract: The present system provides a method for varying the value of passive components in electronic circuits. Passive components can range from basic resistors, capacitors, and inductors to complex, structures such as transmission lines and resonant cavities. Value selection and variation can either be dynamically performed during circuit operation or as a one-time part of the manufacturing process as determined by the requirements of the specific application. A digital-to-analog converter (DAC) circuit is used to input value selection data digitally, and control value selection with value resolution dependent on the resolution of the DAC. An alternate embodiment is provided for high frequency operation.

Abstract: A method of converting a plurality of input signals on first and second converters, such that the first and second converters are both used when the plurality of signals comprises two signals, characterised in that said method comprises: selecting more than two input signals; determining the type of each selected signal; combining any signals having the same type to form a combined signal; converting one type of signal with the first converter; converting a second type of signal with the second converter wherein the first or second type signals is a combined signal.

Abstract: A source-measure unit (SMU) may be implemented with a control loop configured in the digital domain. The output voltage and output current may be measured with dedicated ADCs (analog-to-digital converters). The readings obtained by the ADCs may be compared to a setpoint, which may be set in an FPGA (field programmable gate array) or DSP (digital signal processing) chip. The FPGA or DSP chip may then be used to produce an output to drive a DAC (digital-to-analog converter) until the output voltage and/or output current reach the respective desired levels. The readback values may be obtained by averaging the voltage and/or current readings provided by the ADCs. The averaging may be weighted to improve noise rejection. The digital control loop provides added flexibility to the SMU and a decrease in the accuracy requirements on the DAC, while also for solving potential range-switching issues that may arise within the SMU.

Abstract: A mixed-signal control apparatus of a modulation system is provided. The mixed-signal control apparatus includes a digital-to-analog converter (DAC) unit, an analog-to-digital converter (ADC) unit, and a processing unit. When a quantization step of the ADC unit is qADC, a quantization step of the DAC unit is qDAC, and a transfer function of the modulation system is G0, qADC?G0qDAC. A controlled variable is finely converted by using the ADC unit having a very high resolution. In such a way, it can be ensured that data in an analog domain can be transmitted to a discrete domain with the least distortion, thus achieving a robust and simple control.

Abstract: A method adjusts driving ability of an output buffer. The output buffer has multiple driving ability classes. The method includes the following steps. First, the driving ability of the output buffer is initialized as an initial class among the driving ability classes. Next, a voltage at an output terminal of the output buffer is initialized to an initial voltage. Then, an input voltage is inputted via the input terminal at a first time instant. Next, an output voltage outputted from the output terminal is sampled to obtain a voltage value at a second time instant. Then, whether the voltage value satisfies a predetermined condition is judged. Next, if the voltage value satisfies the predetermined condition, the driving ability class of the output buffer is recorded and set.

Abstract: A serial communication circuit for performing full duplex serial communication with a microcomputer includes a counter and a timer. The counter is incremented by each pulse of a serial clock signal output from the microcomputer. When the counter reaches the number of bits of serial data output from the microcomputer, the counter outputs a load signal to a receiving register. The timer starts to count after the counter outputs the receiving load signal for the first time and continues to count during the serial communication. The timer expires at a predetermined time interval. Each time the timer expires, the timer outputs a timer signal. In response to the timer signal, a synchronous signal is output to the microcomputer, the counter is cleared to zero, and data to be output to the microcomputer is loaded into a sending register.

Abstract: Low-cost switching converter systems are provided which combine analog generation of a current signal with digital generation of a loop error signal that is realized with a control loop that includes a high-resolution, low-bandwidth sigma-delta modulator and a low-resolution digital-to-analog converter. The current signal and error signal are differenced to provide a control signal to the switching converter. This economical system structure facilitates quick and easy digital alteration of system parameters (e.g., loop compensation and voltage reference). System embodiments add a high-frequency analog feedback path in parallel with the control loop to supplement and enhance its control performance.

Abstract: A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of “L” in synchronous with the output control clock.

Abstract: A pipelined analog-to-digital converter includes at least one multiplying digital-to-analog converter and at least one sub-ADC. The multiplying digital-to-analog converter includes at least one first capacitor, at least one second capacitor, an amplifier, and a plurality of switches. The amplifier is coupled to the first and the second capacitors. The switches control a connection between the first and the second capacitors according to a first control signal, a second control signal and a digital signal. In a first period, the first capacitor is connected to the second capacitor in parallel. In a second period, the first capacitor is connected to the second capacitor in series. At least one switch among the switches is composed of a transistor. The sub-ADC provides a digital signal according to the first and second control signals.

Abstract: A voltage conversion device has a non-linear gain, for converting analog voltage provided by an analog voltage source. The voltage conversion device comprises a gain decision module, a voltage selection module, and a voltage output module. The gain decision module comprises an analog to digital (A/D) converter and a gain selector. The A/D converter is used for converting analog voltage provided by the analog voltage source into digital signals. The gain selector is used for determining a gain. The voltage selection module is used for outputting a direct-current (DC) voltage. The voltage output module has a first input end coupled to the gain selector, an output end coupled to the gain selector, and a second input end coupled to the voltage selection module, for outputting an amplified result of the DC voltage outputted from the voltage selection module.

Abstract: A mixed-signal control apparatus of a modulation system is provided. The mixed-signal control apparatus includes a digital-to-analog converter (DAC) unit, an analog-to-digital converter (ADC) unit, and a processing unit. When a quantization step of the ADC unit is qADC, a quantization step of the DAC unit is qDAC, and a transfer function of the modulation system is G0, qADC?G0qDAC. A controlled variable is finely converted by using the ADC unit having a very high resolution. In such a way, it can be ensured that data in an analog domain can be transmitted to a discrete domain with the least distortion, thus achieving a robust and simple control.

Abstract: A switching voltage regulator includes, in part, N output stages, a loop ADC, a multiplexer, a current ADC, and an interrupt block. The loop analog-to-digital converter receives the N output voltages each of which is associated with one of N channels. The loop ADC is adapted to vary a duty cycle of N signals each applied to one of the N output stages that generate the N output voltages. The interrupt block is adapted to enable the multiplexer to couple an output stage to the current ADC if a difference between voltages sensed at an output stage during at least two sampling times exceeds a predefined threshold value. The interrupt block may also be adapted to enable the multiplexer to couple an output stage to the current ADC block if a difference between a voltage sensed at the output stage and a reference voltage exceeds a predefined threshold value.

Abstract: Low-cost switching converter systems are provided which combine analog generation of a current signal with digital generation of a loop error signal that is realized with a control loop that includes a high-resolution, low-bandwidth sigma-delta modulator and a low-resolution digital-to-analog converter. The current signal and error signal are differenced to provide a control signal to the switching converter. This economical system structure facilitates quick and easy digital alteration of system parameters (e.g., loop compensation and voltage reference). System embodiments add a high-frequency analog feedback path in parallel with the control loop to supplement and enhance its control performance.

Abstract: An electronic measurement system for extracting a small AC signal from a dominant DC background signal, which can be changing at a rate similar to that at which the desired signal changes. The invention is particularly useful for pulse rate measurement of a subject even while undergoing vigorous motion such as running, by means of pulse oximetry. The measurement technique utilizes a moving window for selecting a part of the input signal, and processing in an A/D converter, an offset part of the signal which falls within a range which covers the window. The method is also more generally employable to any measurement task, where the signal to be extracted is a small AC signal buried within a dominant DC or quasi-DC background, which itself can be changing, and even at a rate similar to that expected of the sought-after AC signal.

Abstract: A selection circuit is used for detecting analogue signals from different inputs. For the detection of a signal switched through by means of the selection circuit, a delay time during the detection of the switched-through signal is set depending on the occurrence of a setting operation in the selection circuit. The selection circuit can have a plurality of switches each having an assigned delay time and the detection can be controlled in such a way that it does not take place until after the elapsing of the delay times of all the involved in switching through the analogue signal to be detected.

Abstract: In order to convert a complex analog signal into a complex digital signal in an analog-digital conversion device having two channels, I and Q respectively, in quadrature, each comprising an input and an associated output, each output being fed back onto said associated input so as to form a first and a second feedback loops each comprising a digital-analog converter, the device comprising a complex filter with a first stage and a last stage, after sampling (508), a signal integration is performed in a first stage (501) of the filter without introducing any substantial delay. Then, an integration is performed in the last stage (502) of the filter. A substantial delay (507) is then introduced and the output signal of the last stage is converted into a digital signal over several bits. The digital signal is injected into the feedback loop (108) of said channel and the digital signal is converted into a feedback signal.

Abstract: In one embodiment, at least one parameter set for at least one harmonic of a continuous wave (CW) signal is digitally generated in response to a parameter set for the CW signal. In response to the parameter set for the CW signal, the CW signal is synthesized; and in response to the at least one parameter set for the at least one harmonic of the CW signal, at least one nulling tone is synthesized. The CW signal and the at least one nulling tone are amplified; and the amplified CW signal and the at least one amplified nulling tone are summed to produce a linearized amplified CW signal. Other embodiments are also described.

Abstract: An A/D conversion apparatus performs motor current detection in an A/D conversion period corresponding to two phases out of three phases of a sinusoidal drive motor, using reduced register resources while minimizing the number of A/D converters. The A/D conversion apparatus includes: a selection unit selecting one of a plurality of input channels; an A/D converter converting an analog signal from the selected input channel to a digital signal; a start register holding a start channel number of sequential conversion; an end register holding an end channel number of the sequential conversion; a prohibition information holding unit holding prohibition information indicating an input channel to be excluded from the sequential conversion; and a control unit causing the selection unit to select, in channel number order, input channels corresponding to channel numbers from the start channel number to the end channel number except the input channel indicated by the prohibition information.

Abstract: An embodiment of the invention relates to a controller that includes a delta-sigma modulator to produce a one-bit, oversampled signal representing a measured characteristic of a process, and a delta-sigma modulator to produce a one-bit, oversampled signal representing a set-point value for the characteristic. A multiplexer selects a partial sum based on a difference of the oversampled signals to produce a control signal for the process. The controller that produces the control signal for the process can be a PID controller.

Abstract: A ??-type AD converter includes a subtractor which receives an analogue input signal and a feedback signal and which outputs a signal pertaining to a difference between the signals, an integrator which integrates a signal output from the subtractor, a comparator which binarizes a signal output from the integrator by comparing with a predetermined threshold value, a counter which measures respective pulse widths of a signal output from the comparator, and a PWM circuit which outputs a pulse signal of a predetermined period having a duty cycle responsive to a count value output from the counter and which feeds back the pulse signal as the feedback signal to the subtractor. The counter measures the respective pulse widths in each PWM frame period in synchronism with the PWM circuit, and the PWM circuit feeds back to the subtractor a pulse signal whose duty cycle is set in accordance with a value of the measured pulse width in a next PWM frame.

Abstract: A signal processing device which outputs a discrete signal composed of a string of the sampling values and parameters m signal. The signal processing device includes a sampling circuit which samples an input signal and outputs a discrete signal, multiple function generators which generate multiple sampling functions with parameters m different from each other, plural inner product operating units for each of parameters m that take an inner product between the input signal and each of plural sampling functions and output an inner product operating value, and a judging unit which determines parameter m providing a minimum error out of multiple errors composed of differences between the sampling value and inner product operating values output from the multiple inner product operating units and outputs the parameters m signal.

Abstract: Various systems and methods for analog to digital conversion are disclosed. For example, some embodiments of the present invention provide analog to digital conversion systems. The analog to digital conversion systems include a first integrator and a second integrator, and a first summation element and a second summation element. An output of the first summation element is electrically coupled to the first integrator, and an output of the first integrator is electrically coupled to the second integrator. An output of the second integrator is electrically coupled to the second summation element. The analog to digital conversion systems further include an analog to digital converter that is electrically coupled to the first summation element via a digital to analog converter. An input to the analog to digital conversion system is electrically coupled to the first summation element, and the input is electrically coupled to the second summation element via a kickback filter.

Abstract: A digital-to-analogue converting circuit includes a driver leg having a plurality of resistance elements between a power supply voltage terminal and a ground voltage terminal, wherein at least one of the plurality of resistance elements is a variable resistor, and a code level changing unit for outputting a level-changed code to a control terminal of the variable resistor based on an activation of a digital code, wherein the level-changed code is produced by converting a level of the digital code.

Abstract: An AD output average computation circuit 103 computes an average value of output values of 16 pixels from an AD converter 102. A subtractor 105 computes a difference value between the average value and a first AD output reference value. A clip circuit 106 selects analog offset correction or digital offset correction depending on the difference value. In the analog offset correction, a digital integrating circuit composed of a data hold circuit 108 and a subtractor 109 integrates the difference value to obtain an offset correction value, from which an offset correction voltage is generated by a DA converter 111 and an offset voltage generation circuit 112, to be used for correcting the offset of an amplifier 101. In the digital offset correction, a predetermined value is added to the output value of the AD converter 102 by an adder 113b to correct an offset amount.

Abstract: Systems, methods, and devices for obtaining data from a data location. The method may include generating a first value by sensing a data location under a first condition and generating a second value by sensing the data location under a second condition. The method may further include combining the first value with the second value to identify data conveyed by the data location.

Abstract: An integrated circuit device includes an amplifier circuit that includes first to Nth amplifiers, an A/D converter, first to Nth offset adjustment registers that are provided corresponding to the first to Nth amplifiers and store first to Nth offset adjustment data, first to Nth D/A converters provided corresponding to the first to Nth amplifiers, first to Nth offset value storage sections that store first to Nth offset value data, and a control circuit that calculates the first to Nth offset adjustment data based on the first to Nth offset value data, and sets the first to Nth offset adjustment data in the first to Nth offset adjustment registers.

Abstract: A system and a method are provided for receiving analog and digital audio input via a single audio input connector. The method includes receiving an input signal from a single audio input connector, splitting the received input signal into a first input signal and a second input signal, filtering the first input signal to pass a digital signal, filtering the second input signal to pass an analog signal, digitizing the filtered analog signal, and multiplexing the filtered digital signal and the filtered digitized analog signal.

Abstract: The sensor has only a first contact (1) and a second contact (2). In the first step of the method, current is passed through the sensor element (3) while simultaneously measuring the measured variable using a closed switch (4). In a second step, the measured value is then converted into a digital signal in an analogue/digital converter (5) and the digital signal is transformed into a digital output value in a digital switching mechanism (6) which is connected downstream of the analogue/digital converter (5). In a third step, the digital output value is serially sent via the first contact (1) and the second contact (2) with the switch (4) open or closed depending on the binary structure of the digital output value.

Abstract: An electronic filter device for the reception of TV-signals, comprising a plurality of frequency determining elements settable by means of an analog setting voltage, a memory (2) for storing digital values representative of the analog setting voltages and conversion circuitry (11-14) for converting the digital values into the analog setting voltages. The conversion circuitry comprises a first part (11-13) for generating a digitally modulated signal for each digital value, the digitally modulated signal having a modulated characteristic representative of the digital value, and a second part (14) for converting each of the digitally modulated signals into the analog setting voltages.

Abstract: Systems, methods, and devices, such as a device including a floating-gate transistor, a quantizing circuit coupled to the floating-gate transistor, and a controller configured to vary a voltage of a gate of the floating-gate transistor when reading data from the floating-gate transistor. The floating-gate transistor, the quantizing circuit, and the controller device may form a memory device that may utilize the quantizing circuit to retrieve data stored via variable reference signals.

Abstract: A method for adjusting a phase of a sampling frequency of ADC is disclosed. The method includes converting an analog signal into a first digital signal according to a first phase of the sampling frequency during a first time interval; calculating a first value according to the first digital signal; converting the analog signal into a second digital signal according to a second phase of the sampling frequency during a second time interval; calculating a second value according to the second digital signal; and adjusting the phase of the sampling frequency according to the first value and the second value.

Abstract: A source-measure unit (SMU) may be implemented with a control loop configured in the digital domain. The output voltage and output current may be measured with dedicated ADCs (analog-to-digital converters). The readings obtained by the ADCs may be compared to a setpoint, which may be set in an FPGA (field programmable gate array) or DSP (digital signal processing) chip. The FPGA or DSP chip may then be used to produce an output to drive a DAC (digital-to-analog converter) until the output voltage and/or output current reach the respective desired levels. The readback values may be obtained by averaging the voltage and/or current readings provided by the ADCs. The averaging may be weighted to improve noise rejection. The digital control loop provides added flexibility to the SMU and a decrease in the accuracy requirements on the DAC, while also for solving potential range-switching issues that may arise within the SMU.

Abstract: An object of the present invention is to reduce spurious generation due to a malfunction of an A/D converter in a device performing digital processing by converting an analog signal high in cyclic characteristics to a digital signal with the A/D converter. As a concrete solving means, for instance, in a frequency synthesizer of a certain system, the A/D converter is provided on an output side of a voltage controlled oscillator, and its output signal is given to a device performing digital processing to feed back the processing result to the voltage controlled oscillator through D/A conversion. In this case, the noise generated in the band noise generator is added to an input signal of the above-described analog/digital converter. This band noise is a band not affecting the digital signal processing performed by the device.

Abstract: The present system provides a method for varying the value of passive components in electronic circuits. Passive components can range from basic resistors, capacitors, and inductors to complex, structures such as transmission lines and resonant cavities. Value selection and variation can either be dynamically performed during circuit operation or as a one-time part of the manufacturing process as determined by the requirements of the specific application. A digital-to-analog converter (DAC) circuit is used to input value selection data digitally, and control value selection with value resolution dependent on the resolution of the DAC. An alternate embodiment is provided for high frequency operation.

Abstract: A circuit for converting from an input serial pulse code modulated (PCM) digital signal to an output pulse width modulated (PWM) digital signal for driving a switching audio amplifier requiring a pulse width modulated input signal, the circuit comprising a sample rate converter receiving the input serial PCM digital signal at a first sampling frequency and converting the input serial PCM digital signal to a second serial PCM digital signal at a second frequency if the first sampling frequency is lower than the second frequency, a digital filter stage for up-sampling the second serial PCM digital signal to a third frequency and converting the second serial PCM digital signal to a parallel digital signal, a volume control stage receiving the parallel digital signal and generating a volume adjusted parallel digital signal in accordance with a digital volume command control signal, a digital cross-point estimator stage for calculating a cross-point between the volume adjusted parallel digital signal and a digital

Abstract: This invention relates to a method and apparatus for output current control. The invention provides an output module slice for controlling an output current comprising: an output field interface controller for controlling an input voltage to a first field effect transistor; an analogue to digital converter connected to read the current flowing through said first field effect transistor and to provide a digital signal dependent thereon to said output field interface controller.

Abstract: A digital-to-analog converter (DAC) includes a decoder unit for receiving an external digital data signal operating over a first predefined voltage range (i.e., 0-5V); a resistor array for generating a plurality of gray voltages defined across a second voltage range that is substantially wider than the first predefined voltage range, and a voltage selecting unit for selecting one of the gray voltages based on an output of the decoder unit, wherein the decoder unit includes a plurality of decoder stages and first and second boost circuits for generating output signals operating over a third voltage range (i.e., 0-7V) that is substantially wider than the first predefined voltage range while not requiring an additional power supply for producing voltages of the third voltage range (i.e., 0-7V).

Abstract: A method and apparatus for compensating for gain offset, bias offset, and skew in a parallel processing environment is disclosed. The method and apparatus may be configured to compensate for mismatches between the sub-channel signals in a parallel ADC. This allows for accurate combination of the signals on the sub-channels. The method and apparatus may be utilized in a high speed data communication system having two or more channels, each of which are interleaved into two or more sub-channels. In one embodiment a DC loop processes signals on two or more sub-channels to account for and remove unwanted bias offset. In one embodiment a sub-channel gain mismatch compensation system (SCGMC) processes signals on two or more sub-channels to account for and remove unwanted gain offset. In one embodiment a skew compensation system, such as a parallel interpolator, processes signals on two or more sub-channels to remove unwanted skew across sub-channels.

Abstract: A power-to-digital converter (PDC) converting a signal power to digital code. The PDC comprises a power detector, an analog-to-digital converter (ADC), and a timing and logic control circuit. The power detector receives the signal power and generates a DC output and a first determined number of bits. The ADC is coupled to the power detector and receives and converts the DC output to a second determined number of bits. The timing control logic circuit is coupled to the power detector and the ADC and sequentially enables the power detector and the ADC. The first and second predetermined numbers of bits are respectively most significant bits (MSBs) and least significant bits (LSBs) of the digital code. The bit resolution of the digital code is the sum of the first and second numbers.

Abstract: The present invention provides a read channel and a drive capable of suppressing deterioration in performance of a PLL and a Viterbi decoder by using a DC component eliminating means capable of higher-speed operation than hitherto. The location of an edge is determined by using differential of a read signal, and a DC component is detected from the midpoint level of the edge. Detection of a pseudo-edge due to a long mark or space signal is prevented by limiting the absolute value of a maximum or minimum of a differential coefficient when the location of the edge is determined from the differential coefficient of the read signal. Internal operation of a DC component detector is controlled according to the state of the PLL and the magnitude of the DC component.

Abstract: An apparatus and method for providing an analog-to-digital converter (ADC) in programmable logic devices is disclosed. A plurality of multi-purpose input/output (I/O) blocks is configured to provide analog-to-digital conversion and other I/O functionality. The plurality of multi-purpose I/O blocks is also configured to save power when ADC mode is disabled.

Abstract: An integrator circuit (110) is provided including an amplifier element (170) configured to receive an input signal at an input node, amplify the input signal, and provide an amplified input signal at an output node; a feedback capacitor element (175) connected between the output node and the input node; and a current matching circuit (120) connected to the output node, and configured to sense an output voltage of the amplifier element and to provide a supplemental current (IM) to the input node that is less than or equal to a feedback current (IF) charging the feedback capacitor element. This supplemental current is substantially equal and opposite in polarity to a feedback current when the output voltage satisfies a set criterion.