Capacitor And Resistor Patents (Class 361/766)
  • Patent number: 8023277
    Abstract: The electronic component integrated module includes a wiring board; an electronic component provided on the wiring board; solder for electrically connecting the electronic component onto the wiring substrate; and an encapsulating resin for encapsulating the electronic component and the solder. The average linear thermal expansion coefficient ? of the encapsulating resin, which is calculated by using the glass transition temperature of the encapsulating resin, a linear thermal expansion coefficient ?1 obtained at a temperature lower than the glass transition temperature, a linear thermal expansion coefficient ?2 obtained at a temperature exceeding the glass transition temperature, room temperature, and a peak temperature of reflow packaging of the electronic component integrated module, is not less than 17×10?6/° C. and not more than 110×10?6/° C.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: September 20, 2011
    Assignee: Panasonic Corporation
    Inventors: Yoshiyuki Arai, Hideki Takehara
  • Patent number: 7986532
    Abstract: An apparatus includes a split thin film capacitor for providing multiple power and reference supply voltage levels to electrical devices such as integrated circuits. Such capacitor may be useful in space restricted applications, and in applications that require very close electrical connections between the power consumer and the power supply. An example of both a space restricted application and a close coupling application may be an integrated circuit (IC) such as a microprocessor. The capacitor supplying and moderating power to the microprocessor needs to be closely coupled in order to respond to instantaneous power demands that may be found in high clock rate microprocessors, and the space inside a microprocessor package is very restricted.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: July 26, 2011
    Assignee: Intel Corporation
    Inventors: Cengiz A. Palanduz, Larry E. Mosley
  • Patent number: 7978478
    Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 id constituted by provided a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: July 12, 2011
    Assignee: IBIDEN Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 7957154
    Abstract: A multilayer printed circuit board, wherein, on a resin-insulating layer that houses a semiconductor element, another resin-insulating layer and a conductor circuit are formed with conductor circuits electrically connected through a via hole, wherein a electromagnetic shielding layer is formed on a resin-insulating layer surrounding a concave portion for housing a semiconductor element or on the inner wall surface of the concave portion, and the semiconductor element is embedded in the concave portion.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: June 7, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Sotaro Ito, Michimasa Takahashi, Yukinobu Mikado
  • Patent number: 7936567
    Abstract: A method for manufacturing a wiring board with built-in component. The method provides a secure connection between a component and interlayer insulating layers so that the wiring board with built-in component has excellent reliability. The wiring board is manufactured through a core board preparation step, a component preparation step, an accommodation step and a height alignment step. In the core board preparation step, a core board having an accommodation hole therein is prepared. In the component preparation step, a ceramic capacitor having therein a plurality of protruding conductors which protrudes from a capacitor rear surface is prepared. In the accommodation step, the ceramic capacitor is accommodated in the accommodation hole with the core rear surface facing the same side as the capacitor rear surface. In the height alignment step, a surface of a top portion of the protruding conductor and a surface of a conductor layer formed on the core rear surface are aligned to the same height.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: May 3, 2011
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Tsuneaki Takashima, Jun Otsuka, Makoto Origuchi, Yukinobu Nagao, Chy Narith, Kozo Yamasaki
  • Patent number: 7936568
    Abstract: A capacitor built-in substrate of the present invention includes; a base resin layer; a plurality of capacitors arranged side by side in a lateral direction in a state that the capacitors are passed through the base resin layer, each of the capacitors constructed by a first electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively such that the projection portion on one surface side of the base resin layer serves as a connection portion, a dielectric layer for covering the projection portion of the first electrode on other surface side of the base resin layer, and a second electrode for covering the dielectric layer; a through electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively; and a built-up wiring formed on the other surface side of the base resin layer and connected to the second electrodes of the capac
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: May 3, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Naohiro Mashino
  • Patent number: 7929316
    Abstract: A composite electronic component includes a multilayer wiring block having a plurality of insulating layers and a wiring pattern, and a chip-type electronic component built-in multilayer block having a plurality of insulating payers and a wiring pattern and including a first chip-type electronic component. The multilayer wiring block and the chip-type electronic component built-in multilayer block are electrically interconnected and arranged on substantially the same plane.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: April 19, 2011
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Satoru Noda, Jun Harada
  • Patent number: 7916495
    Abstract: A universal solder pad is used with a plurality of SMD components having different sizes. Each SMD component includes a first conductive part and a second conductive part. The universal solder pad includes a first pad unit and a second pad unit. The first and second pad units are electrically connected to the first and second conductive parts of the SMD component, respectively. Each of the first and second pad units includes a main portion and a first extension portion. The first extension portion is extended from a first sidewall of the main portion and includes a first border, a second border and a third border. The second border and the third border of the first extension portion are parallel with each other for facilitating alignment of the first and second conductive parts of the SMD component with respect to the first pad unit and the second pad unit.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: March 29, 2011
    Assignee: Delta Electronics, Inc.
    Inventor: Chun-Line Huang
  • Patent number: 7911802
    Abstract: An interposer including: a substrate including a first layer and second layer, wherein the first layer and second layer are positioned parallel to each other; electrodes each having a concave-convex structure formed on each facing surface of the first layer and second layer of the substrate; a dielectric layer sandwiched between the electrodes which are formed on each facing surface of the first layer and second layer of the substrate; a first conductive part which vertically passes through the first layer of the substrate from a first outer surface of the substrate and is electrically connected to an electrode formed on a surface of the second layer of the substrate that faces the first layer of the substrate; and a second conductive part which vertically passes through the second layer of the substrate from a second outer surface of the substrate and is electrically connected to an electrode formed on a surface of the first layer of the substrate that faces the second layer of the substrate.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: March 22, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Shuichi Kawano, Liyi Chen
  • Patent number: 7903427
    Abstract: A semiconductor device structure includes a semiconductor substrate, a resistor layer, and a capacitor layer. The resistor layer is configured to overlie the semiconductor substrate. The resistor layer has a resistor disposed therewithin. The capacitor layer is configured to overlie the resistor layer. The capacitor layer has a capacitor disposed over and electrically connected with the resistor. Further, a semiconductor device that generates a constant output voltage from an input voltage includes a semiconductor substrate, a resistor layer, and a capacitor layer. The resistor layer is configured to overlie the semiconductor substrate. The resistor layer has a resistor disposed therewithin. The capacitor layer is configured to overlie the resistor layer. The capacitor layer has a capacitor disposed over and electrically connected with the resistor.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: March 8, 2011
    Assignee: Ricoh Company, Ltd.
    Inventors: Kohzoh Itoh, Kazuhiro Kawamoto
  • Patent number: 7898818
    Abstract: Variably oriented capacitive elements for printed circuit boards (PCBs) and method of manufacturing the same. In one form the disclosure, a PCB can include a first multiple-layered capacitor including a first orientation and placed along a surface operable to mount electronic components. The PCB can also include a second multiple-layered capacitor including a second orientation different from the first. The second multiple-layered capacitor can be placed along the surface near the first multiple-layered capacitor.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: March 1, 2011
    Assignee: Dell Products, LP
    Inventor: Daniel W. Kehoe
  • Patent number: 7889510
    Abstract: A component-embedded board device has a wiring board in which an electronic component is embedded, a connection member which is conductive and arranged at a surface of the wiring board, and an inner wiring unit which is arranged in the wiring board and connects an electrode of the electronic component with the connection member. The component-embedded board device is further provided with an inspection connection member for an inspection of a faulty wiring of the inner wiring unit, and an inspection wiring unit which is arranged in the wiring board and connects the inspection connection member with one of the electrode and a predetermined portion of the inner wiring unit. The inspection connection member is conductive and arranged at a surface of the wiring board.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: February 15, 2011
    Assignee: Denso Corporation
    Inventors: Satoshi Takeuchi, Hiroki Kamiya, Katsunori Kubota, Motoki Shimizu
  • Patent number: 7876570
    Abstract: In a module with embedded electronic components, connection electrodes are formed on the component mounting surface of a substrate. The electrode portions of each of the electronic components are placed on the individual connection electrodes and connected in fixed relation thereto by using a solder. The electronic components are encapsulated in an encapsulating resin.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: January 25, 2011
    Assignee: Panasonic Corporation
    Inventors: Masanori Minamio, Hideki Takehara, Yoshiyuki Arai, Toshiyuki Fukuda
  • Patent number: 7869243
    Abstract: A memory module with a module board is disclosed, on the front side of which a plurality of first memory devices are arranged in rows. A plurality of second memory devices are arranged in rows on the back side. The first and second memory devices have a single chip each. Further, a first register device for providing first control signals to first rows of first memory devices and to first rows of second memory devices is provided. A second register device serves to provide first control signals to second rows of first memory devices and to second rows of second memory devices.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: January 11, 2011
    Assignee: Qimonda AG
    Inventor: Abdallah Bacha
  • Patent number: 7869222
    Abstract: An embedded electronic component structure and a method for forming the same are provided, wherein the embedded electronic component structure comprises a lower laminating layer, a first clamping layer, a dielectric layer, a second clamping layer, an electronic component, an upper laminating later and a via interconnection. The first clamping layer is disposed on the lower laminating layer. The dielectric layer is disposed on the first clamping layer. The second clamping layer is located on the dielectric layer. The electronic component is embedded in the dielectric layer, wherein the lower surface of the electronic component contacts the first clamping layer and the upper surface thereof contacts the second clamping layer. The upper laminating layer covers the second clamping layer. The via interconnection is adjacent to the electronic component and penetrate the dielectric layer to respectively connect the first clamping layer and the second clamping layer.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: January 11, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Che-Kun Shih
  • Patent number: 7869221
    Abstract: An apparatus for constructing, repairing and operating modular electronic systems utilizes peripheral half-capacitors (i.e., conductive plates on the outside of the modules) to communicate non-conductively between abutting modules. Such systems provide lower cost, improved testability/reparability and greater density than conventional modular packaging techniques, such as printed circuit boards and multi-chip modules. The non-conductive interconnection technique of the invention can be applied to all levels in the packaging hierarchy, from bare semiconductor dies to complete functional sub-units. Numerous exemplary systems and applications are described.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: January 11, 2011
    Assignee: Oracle America, Inc.
    Inventors: Thomas F. Knight, David B. Salzman
  • Patent number: 7864542
    Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 id constituted by provided a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: January 4, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 7855894
    Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: December 21, 2010
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 7842887
    Abstract: A multilayer printed circuit board has an IC chip (20) included in a core substrate (30) in advance and a transition layer (38) provided on a pad (24) of the IC chip (20). Due to this, it is possible to electronically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the transition layer (38) made of copper on the die pad (24), it is possible to prevent resin residues on the pad (24) and to improve connection characteristics between the pad (24) and a via hole (60) and reliability.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: November 30, 2010
    Assignee: Ibiden Co., Ltd.
    Inventors: Hajime Sakamoto, Tadashi Sugiyama, Dongdong Wang, Takashi Kariya
  • Patent number: 7835160
    Abstract: First sheet-like substrate is arranged at a region surrounded by first terminals of male connector and first circuit substrate, and second sheet-like substrate is arranged at a region surrounded by second terminals of female connector and second circuit substrate, and male connector and female connector are fitted together so that a first passive element of first sheet-like substrate and a second passive element of second sheet-like substrate configure a filter circuit.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: November 16, 2010
    Assignee: Panasonic Corporation
    Inventors: Kenichi Yamamoto, Daisuke Suetsugu, Daido Komyoji, Takashi Imanaka, Hirotaka Hisamura
  • Patent number: 7821795
    Abstract: A multilayered substrate includes a plurality of circuit boards including a plurality of wiring layers including a grounding layer and a power layer, a solid electrolytic capacitor having an insulative oxide film layer, an electrolytic layer, and a conductor layer sequentially formed on one surface or both surfaces of a foil-like metal substrate, and a conductive substance passing through the circuit board across a thickness thereof. The solid electrolytic capacitor is disposed to be held between the plurality of circuit boards. The conductor layer is connected to a grounding electrode formed on the grounding layer, the foil-like metal substrate being connected to a power electrode formed on the power layer.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: October 26, 2010
    Assignee: Panasonic Corporation
    Inventors: Yasuhiro Sugaya, Yoshiyuki Yamamoto, Toshiyuki Asahi, Katsumasa Miki, Masaaki Katsumata, Yoshiyuki Saitou, Takeshi Nakayama
  • Patent number: 7817440
    Abstract: A multilayer printed wiring board includes a mounting portion supporting a semiconductor device and a layered capacitor portion including first and second layered electrodes and a ceramic high-dielectric layer therebetween. The first layered electrode is connected to a ground line and the second layered electrode is connected to a power supply line. The ratio of number of via holes, each constituting a conducting path part electrically connecting a ground pad to the ground line of a wiring pattern and passing through the second layered electrode in non-contact, to number of ground pads is 0.05 to 0.7. The ratio of number of second rod-shaped conductors, each constituting a conducting path part electrically connecting a power supply pad to the power supply line of the wiring pattern and passing through the first layered electrode in non-contact, to number of power supply pad is 0.05 to 0.7.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: October 19, 2010
    Assignee: Ibiden Co., Ltd.
    Inventors: Takashi Kariya, Hironori Tanaka
  • Patent number: 7813141
    Abstract: This invention relates to a capacitive/resistive device, which may be embedded within a layer of a printed wiring board. Embedding the device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. More specifically, the device, comprises a first metallic foil; a second metallic foil; a first electrode formed from the first metallic foil; a dielectric disposed over the first electrode; a resistor element formed on and adjacent to the dielectric; a conductive trace; and a second electrode formed from the second metallic foil and disposed over the dielectric and in electrical contact with the resistor element, wherein the dielectric is disposed between the first electrode and the second electrode and wherein said dielectric comprises an unfilled polymer of dielectric constant less than 4.0.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: October 12, 2010
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: William J. Borland, G. Sidney Cox, David Ross McGregor
  • Patent number: 7813140
    Abstract: The present invention describes methods for enhancing the performance of two-capacitor low-pass filters. In certain embodiments of the invention, the capacitors are placed on opposite sides of a PCB board.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: October 12, 2010
    Assignee: Apple Inc.
    Inventor: Cheung-Wei Lam
  • Patent number: 7791897
    Abstract: A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: September 7, 2010
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, John M. Lauffer, Irving Memis, Steven G. Rosser
  • Patent number: 7782629
    Abstract: A pre-drilled hole, providing a passageway between an upper and a lower surface of a printed circuit board layer, receives a passive component, for example a resistor or a capacitor. In one embodiment the component is cylindrical, with an electrically conductive contact point at each end. The hole diameter is approximately the same as the diameter of the cylindrical component. The hole is similar to a via in a printed circuit board, except that the hole is not plated through (such would cause an electrical short). Electrically conductive lines are provided to the openings of the hole on the upper and the lower surfaces of the PCB. The area of the exposed end of the cylindrical component and the termination of the conducting line is less than the area of a surface mounted component equivalent to the cylindrical component.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: August 24, 2010
    Assignee: Flextronics AP, LLC
    Inventors: Bhret Graydon, William Kuang-Hua Shu
  • Patent number: 7778040
    Abstract: A printed circuit board assembly includes: a substrate; a main signal line formed on the substrate to transmit a signal; an SMD mounted on the substrate; a pad interposed between the SMD and the substrate; and a sub signal line provided on the substrate to electrically connect the main signal line with the pad, and having a width different from that of the main signal line. Thus, the printed circuit board assembly transmits a signal at a high speed and enhancing reliability and an economical efficiency of a product using the printed circuit board assembly.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: August 17, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seung-young Ahn
  • Patent number: 7773386
    Abstract: A flexible substrate includes: (i) a film; (ii) an insulating resin layer formed on each of a front face of the film and a rear face of the film, which rear face is opposite to the front face; (iii) a front-sided wiring pattern embedded in the insulating resin layer formed on the front face of the film, and a rear-sided wiring pattern embedded in the insulating resin layer formed on the rear face of the film; and (iv) a via which is located between the front-sided wiring pattern and the rear-sided wiring pattern and serves to electrically interconnect the front-sided wiring pattern and the rear-sided wiring pattern, wherein the insulating resin layer formed on each of the front face and the rear face of the film is thicker than the film.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: August 10, 2010
    Assignee: Panasonic Corporation
    Inventors: Yoshihisa Yamashita, Toshio Fujii, Seiichi Nakatani, Takashi Ichiryu, Satoru Tomekawa, Hiroki Yabe
  • Patent number: 7768795
    Abstract: Electronic circuit device (100) is structured so that a substrate module unit that are formed by stacking substrate modules made of a first resin sheet with electronic component (190) embedded thereinto is inserted into housing (150) including connecting terminal (120), control circuit (130), and first wiring pattern (140), where the substrate modules are connected to each other electrically and mechanically. This electronic circuit device (100) dispenses with a mother substrate. Further, with slimming down of a substrate module, a substrate module unit with a large number of substrate modules stacked can be loaded in a limited packaging space, thus mounting greater storage capacity and higher functionality.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: August 3, 2010
    Assignee: Panasonic Corporation
    Inventors: Daisuke Sakurai, Masahiro Ono, Kazuhiro Nishikawa
  • Patent number: 7764509
    Abstract: An apparatus operable to interface an electronic component with a signal input. The apparatus may generally include a low-ohm resistor and a voltage translator coupled with the low-ohm resistor. The low-ohm resistor is operable to couple with the input to receive an input signal therefrom. The voltage translator is operable to couple with the electronic component and translate the input signal from a first voltage to a second voltage for use by the electronic component. The low-ohm resistor and voltage translator may be positioned by a pick and place assembly machine such that embodiments of the present invention do not require a technician to manually couple and solder the apparatus to the input and electronic component.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: July 27, 2010
    Assignee: Spirit AeroSystems, Inc.
    Inventor: Jerry William Yancey
  • Patent number: 7755910
    Abstract: A capacitor built-in interposer of the present invention, includes a base resin layer, a capacitor first electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively whereby the projection portion on one surface side of the base resin layer serves as a connection portion, a capacitor dielectric layer for covering the projection portion of the first electrode on other surface side of the base resin layer, and a capacitor second electrode for covering the dielectric layer, wherein a plurality of capacitors each constructed by the first electrode, the dielectric layer, and the second electrode are arranged and aligned in a lateral direction in a state that the capacitors are passed through the base resin layer.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: July 13, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Naohiro Mashino
  • Patent number: 7746663
    Abstract: An electronic substrate is disclosed that includes: a substrate having a first face on which an active region is formed, and a second face on an opposite side to the first face and on which a passive element is formed. The substrate may further include: a penetrative conductive portion penetrating through the substrate; and an electrode formed on the first face, wherein the passive element is electrically connected to the electrode via a penetrative conductive portion.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: June 29, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7733662
    Abstract: A process for fabricating a circuit board with an embedded passive component is provided. First, an electrode-patterned layer having electrodes is formed on a surface of a conductive layer. Then, a passive component material is filled in the intervals between the electrodes. Then, the conductive layer and the electrode-patterned layer are laminated to a dielectric layer, wherein the electrode-patterned layer is embedded in the dielectric layer. Next, the conductive layer is patterned to form a circuit layer.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: June 8, 2010
    Assignee: Unimicron Technology Corp.
    Inventor: Tsung-Yuan Chen
  • Patent number: 7719850
    Abstract: A power supply module arrangement with an integrated circuit mounted on a bearing unit and a power supply includes an integrated circuit mounted on a bearing unit and a power supply module arrangement that is placed on the combination of bearing unit and integrated circuit. The power supply module arrangement includes a base extending at least partially over the base of the integrated circuit and/or all around the base of the integrated circuit. The power supply module arrangement allows for greater permissible load jumps, greater permissible current change rates and ever tighter tolerances regarding the constancy of the supply voltage.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: May 18, 2010
    Assignee: NXP B.V.
    Inventors: Thomas Duerbaum, Reinhold Elferich
  • Patent number: 7719852
    Abstract: A high-reliability electronic component without reduction in insulation resistance under high-temperature and high-humidity conditions has satisfactory solderability of external electrodes. The electronic component includes a main body and external electrodes disposed on surfaces of the main body, the external electrodes include underlying electrode layers each containing a metal, alloy layers each disposed on the corresponding underlying electrode layer, Ni plating layers each disposed on the corresponding alloy layer, Ni oxide layers each disposed on the corresponding Ni plating layers, and upper plating layers each disposed on the corresponding Ni oxide layer, each Ni oxide layer having a thickness of about 150 nm or less, and each Ni plating layer having an average particle size of Ni particles of about 2 ?m or more. To form the Ni plating layers having reduced grain boundaries, heat treatment is performed at about 500° C. to about 900° C.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: May 18, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shigeyuki Horie, Yutaka Ota, Jun Nishikawa
  • Publication number: 20100118502
    Abstract: Chip capacitors are provided in a printed circuit board. In this manner, the distance between an IC chip and each chip capacitor is shortened, and the loop inductance is reduced. In addition, the chip capacitors are accommodated in a core substrate having a large thickness. Therefore, the thickness of the printed circuit board does not become large.
    Type: Application
    Filed: January 21, 2010
    Publication date: May 13, 2010
    Applicant: IBIDEN CO., LTD.
    Inventors: Yasushi INAGAKI, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 7684207
    Abstract: A composite electronic component includes a multilayer wiring block having a plurality of insulating layers and a wiring pattern, and a chip-type electronic component built-in multilayer block having a plurality of insulating payers and a wiring pattern and including a first chip-type electronic component. The multilayer wiring block and the chip-type electronic component built-in multilayer block are electrically interconnected and arranged on substantially the same plane.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: March 23, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Satoru Noda, Jun Harada
  • Patent number: 7675756
    Abstract: Disclosed herein is a printed circuit board with an embedded thin-film capacitor, and a method of manufacturing the same. Specifically, the present invention relates to a printed circuit board with an embedded thin-film capacitor, comprising a lower electrode formed on an insulating substrate; an amorphous paraelectric film formed on the lower electrode; a metal seed layer formed on the paraelectric film; and an upper electrode formed on the metal seed layer and having a surface roughness (Ra) of more than 300 nm; and a method of manufacturing a printed circuit board with an embedded thin-film capacitor, comprising forming a lower electrode on an insulating substrate; forming an amorphous paraelectric film on the lower electrode, using a low-temperature film formation process; forming a metal seed layer on the paraelectric film; and forming an upper electrode having a surface roughness (Ra) of more than 300 nm on the metal seed layer, using an electroplating method.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: March 9, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jin Seok Moon, Yul Kyo Chung, Soo Hyun Lyoo, Seung Hyun Sohn
  • Patent number: 7667977
    Abstract: The mounting board has a capacitor-forming sheet made from a valve metal, first and second board-forming structures, first and second electrodes, an extractor electrode, and a conductive polymer. The capacitor-forming sheet has an inner layer and a rough oxide film on at least one face of the inner layer. The first board-forming structure is provided on a face of the capacitor-forming sheet, and the second board-forming structure is provided on another face thereof on a side opposite to the first one. The first and second electrodes are isolated to each other and provided on a surface of at least one of the first and second board-forming structures. The extractor electrode and conductive polymer are provided inside at least one of the first and second board-forming structures. The extractor electrode electrically-connects the first electrode with the inner layer. The conductive polymer electrically-connects the second electrode with the rough oxide film.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: February 23, 2010
    Assignee: Panasonic Corporation
    Inventors: Yasuhiro Sugaya, Toshiyuki Asahi, Katsumasa Miki, Yoshiyuki Yamamoto, Hiroyuki Ishitomi, Tsuyoshi Himori
  • Patent number: 7663892
    Abstract: Disclosed herein is a printed circuit board having an RF module power stage circuit embedded therein. Specifically, this invention relates to a printed circuit board having an RF module power stage circuit embedded therein, in which a terminal pad for a resistor, a bead, or an inductor is defined or formed on a power supply plane of a multilayered wired board to connect the resistor, the bead, or the inductor to the power supply plane, and the resistor, the bead, or the inductor is connected in parallel with a decoupling capacitor by using a via hole or by embedding the resistor, the bead or the inductor perpendicular to the power supply plane, thus decreasing the size of the RF module and improving the performance thereof.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: February 16, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Don Chul Choi, Jae Cheol Ju, Dong Hwan Lee, Sang Soo Park, Hee Soo Yoon
  • Patent number: 7649747
    Abstract: An IC device has a compact design. Capacitors, resistances and inductances are directly integrated in the IC device without packaging in advance. Thus, the IC device obtained has a slim size and an electric apparatus using the IC device has a big space for use.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: January 19, 2010
    Assignee: AFlash Technology Co., Ltd
    Inventor: Sung Chuan Ma
  • Patent number: 7630208
    Abstract: Provided is a multilayer chip capacitor including a capacitor body having first and second capacitor units arranged in a lamination direction; and a plurality of external electrodes formed outside the capacitor body. The first capacitor unit includes at least one pair of first and second internal electrodes disposed alternately in an inner part of the capacitor body, the second capacitor unit includes a plurality of third and fourth internal electrodes disposed alternately in an inner part of the capacitor body, and the first to fourth internal electrodes are coupled to the first to fourth external electrodes. The first capacitor unit has a lower equivalent series inductance (ESL) than the second capacitor unit, and the first capacitor unit has a higher equivalent series resistance (ESR) than the second capacitor unit.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: December 8, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byoung Hwa Lee, Sung Kwon Wi, Hae Suk Chung, Dong Seok Park, Sang Soo Park, Min Cheol Park
  • Patent number: 7626828
    Abstract: A circuit board includes reference plane layers and a dielectric between the reference plane layers. A resistive element is also provided between the reference plane layers to provide a resistive path between the reference plane layers. Optimally, a decoupling capacitor is provided having a first electrode electrically connected to the resistive element, and a second electrode electrically connected to one of the reference plane layers.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: December 1, 2009
    Assignee: Teradata US, Inc.
    Inventors: Arthur R. Alexander, Jun Fan, James L. Knighten, Norman W. Smith
  • Patent number: 7619901
    Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: November 17, 2009
    Assignee: EPIC Technologies, Inc.
    Inventors: Charles W. Eichelberger, James E. Kohl
  • Patent number: 7613007
    Abstract: The present invention relates to a device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said at least one embedded singulated capacitor; and wherein said at least one embedded singulated capacitor is connected in parallel to at least one of the said planar capacitor laminates; and wherein said power core is interconnected to at least one signal layer.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: November 3, 2009
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Daniel Irwin Amey, Jr., Sounak Banerji, William J. Borland, Karl Hartmann Dietz, David Ross McGregor, Attiganal N. Sreeram
  • Patent number: 7609526
    Abstract: A circuit board including a capacitor structure formed on a surface of an insulating substrate, wherein the capacitor structure includes paired linear conductive layers arranged on the surface of the insulating substrate, parallel to each other with a predetermined distance between them, and a dielectric material filled in a groove defined by those surfaces of the paired linear conductive layers which face each other and the surface of the insulating substrate.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: October 27, 2009
    Assignee: Meiko Electronics Co., Ltd.
    Inventor: Shunsuke Eiki
  • Patent number: 7586755
    Abstract: Through an improvement of module size increase due to mounting a single passive element on a substrate and an increase in the mounting cost, to provide a highly reliable, high performance and small sized electronic circuit component which permits to integrate a variety of electronic parts such as capacitors, inductors and resistors in a high density with low cost. The electronic circuit component comprises an insulator substrate, a plurality of electrodes having different areas provided on the insulator substrate, one or more elements selected from a capacitor element of dielectric material sandwiched between the electrodes, an inductor element and resistor element, a metal wiring connecting the elements, a metal terminal part of a part of the metal wiring and an organic insulator material covering the elements and the circumference of the metal wiring portion excluding the metal terminal portion.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: September 8, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Toshiya Satoh, Masahiko Ogino, Takao Miwa, Takashi Naitou, Takashi Namekawa, Toshihide Nabatame, Shigehisa Motowaki
  • Patent number: 7573721
    Abstract: Embedded passive device structure and its manufacturing method for mainly embedding the passive device structure in the printed circuit board are presented. In this structure, both the source electrode and the ground electrode of the passive device belong to the same level, and includes several source branches and several ground branches that are formed vertically on the inside of the dielectric layer of the circuit board which are connected, respectively, to avoid the conducting between the source electrode and the ground electrode during lamination. When it is in the form of the capacitor structure, through the use of the ultra-fine wiring technique, these source branches and ground branches are separated by a small gap between each other. Therefore, the side face area and quantities of the source branches and ground branches are both increased.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: August 11, 2009
    Assignee: Kinsus Interconnect Technology Corp.
    Inventors: Ting-Hao Lin, Chien-Wei Chang
  • Patent number: 7561438
    Abstract: An electronic device. The device comprises a printed circuit board, a multilayered capacitor formed on the printed circuit board, and a conductive strip disposed on a top surface of the printed circuit board. The conductive strip interconnects to the multilayered capacitor. The multilayered capacitor includes a plurality of capacitance plates and a plurality of dielectric layers wherein each dielectric layer is disposed between two of the capacitance plates. The printed circuit board further comprises ground plated sidewalls disposed about the printed circuit board. Each of the ground plated sidewalls extends from a top surface to a bottom surface of the printed circuit board.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: July 14, 2009
    Assignee: Revera Incorporated
    Inventor: Yungman Liu
  • Patent number: 7529102
    Abstract: The invention achieves stable performance, such as low parasitic capacitance generated at conductive components. Components having a low dielectric constant of 4 or less are disposed on a base member. Functional films partitioned by the low-dielectric-constant components are also provided.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: May 5, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Takashi Miyazawa