Abstract: A package structure and an electronic apparatus of the package structure are disclosed. The package structure includes a substrate and a plurality of pins. The plurality of pins is disposed on the substrate. The plurality of pins is interlaced to each other, so that a line along a specific direction will only pass one of the plurality of pins at most.

Abstract: Disclosed is a printed wiring board having signal layers each interposed between a power supply layer and a ground layer, wherein the signal layer includes at least one of a wiring region for a ground potential and a wiring region for a power supply potential.

Abstract: A semiconductor device (20) has a plurality of device-side lands (23) which are disposed asymmetrically in relation to an intersection point (B). The plurality of device-side lands (23) include 45 device-side connection lands and four device-side isolation lands. Each of the device-side connection lands is mechanically connected to a printed board (10) via a connection component (30). Each of the device-side isolation lands is mechanically isolated from the printed board (10).

Abstract: A semiconductor device may include: first and second wiring boards separated from each other via a gap; a semiconductor chip; first and second groups of electrode pads; and first and second groups of connection pads. The semiconductor chip is fixed to upper surfaces of the first and second wiring boards, and has a first portion adjacent to the gap. The first and second groups of electrode pads are disposed on the first portion. The first and second groups of electrode pads are aligned adjacent to side surfaces of the first and second wiring boards, respectively. The side surfaces of the first and second wiring boards face each other. The first and second groups of connection pads are disposed on lower surfaces of the first and second wiring boards, respectively. The first and second groups of connection pads are aligned adjacent to the side surfaces of the first and second wiring boards, respectively.

Abstract: A mounting structure 1 in which an electronic component 5 is surface-mounted with solder 4 to a wiring substrate 2 is disclosed. The solder is Sn—Ag—Bi—In-based solder containing 0.1% by weight or more and 5% by weight or less of Bi, and more than 3% by weight and less than 9% by weight of In, with the balance being made up of Sn, Ag and unavoidable impurities. The wiring substrate has a coefficient of linear expansion of 13 ppm/K or less in all directions. Thus, it is possible to realize a mounting structure using lead-free solder and for which the occurrence of cracks in a solder joint portion due to a 1000-cycle thermal shock test from ?40 to 150° C. has been suppressed.

Abstract: A multichip module includes a package substrate, a first semiconductor device, a second semiconductor device and a conductive bump. The first semiconductor device is flip-chip bonded to the package substrate. The first semiconductor device includes a first chip pad on a surface thereof. The second semiconductor device is mounted on the first semiconductor device. The second semiconductor device includes a second chip pad facing the first chip pad. The conductive bump connects the first chip pad to the second chip pad. The conductive bump includes a first metallic body that has a first diffusion rate and a second metallic body that has a second diffusion rate lower than the first diffusion rate.

Abstract: Provided is a semiconductor device in which misalignment between a semiconductor die and a substrate (e.g., a circuit board) can be prevented or substantially reduced when the semiconductor die is attached to the circuit board. In a non-limiting example, the semiconductor device includes: a semiconductor die comprising at least one bump; and a circuit board comprising at least one circuit pattern to which the bump is electrically connected. In a non-limiting example, the circuit board comprises: an insulation layer comprising a center region and peripheral regions around the center region; a plurality of center circuit patterns formed in the center region of the insulation layer; and a plurality of peripheral circuit patterns formed in the peripheral regions of the insulation layer. The center circuit patterns may be formed wider than the peripheral circuit patterns, formed in a zigzag pattern, and/or may be formed in a crossed shape.

Abstract: A chip-component structure includes an interposer and a multilayer capacitor mounted thereon. The interposer includes a substrate, a component connecting electrode, an external connection electrode, and a side electrode. The component connecting electrode and the external connection electrode are electrically connected by the side electrode. The component connecting electrode is joined to an external electrode of the multilayer capacitor. The substrate includes a communication hole that communicates between opposite spaces opening in both principal surfaces of the substrate.

Abstract: This publication discloses an electronics module comprising an insulating-material layer having two opposite surfaces, and at least one microcircuit embedded to the insulating-material layer. The microcircuit has a first contact surface comprising first contact terminals, from which the microcircuit is electrically connected to first conductor structures in the form of a patterned first conductor layer contained on first surface of the insulating-material layer, and a second contact surface opposite to the first contact surface, in which there is at least one second contact terminal, from which the microcircuit is electrically connected to second conductor structures contained in the form of a patterned second conductor layer on second surface of the insulating-material layer. According to the invention there is provided a local adhesive layer between the component and the first contact surface and first conductor layer, the adhesive layer filling the space between the component and the first conductor layer.

Abstract: A circuit substrate includes an electrically conductive layer having electrically conductive patterns formed therein, an insulating layer having a through hole, and a composite layer positioned between the electrically conductive layer and the insulating layer. The through hole is configured for having an electronic component mounted thereon. The composite layer includes a polymer matrix and at least one carbon nanotube bundle embedded in the polymer matrix. One end of the at least one carbon nanotube bundle contacts the electrically conductive patterns, and the other is exposed in the through hole of the insulation layer.

Abstract: A circuit substrate includes protruding terminals and has a structure that ensures an excellent connection with an electronic component, such as an IC. The circuit substrate on which an IC is to be mounted includes terminals that are to be electrically connected to solder bumps located on the IC. The terminals protrude from the mounting surface of a substrate body on which the IC is to be mounted. The sectional area of the top surface of each of the terminals is about 1.2 times the sectional area of each of the terminals on the mounting surface.

Abstract: A printed board having an input/output terminal that connects with a component in an image formation apparatus through a cable, and a control circuit that controls the component, the printed board which includes a conductive pattern on which a capacitor that suppresses an emission of an electromagnetic wave from the cable is mounted between a grounding surface and a signal line from the input/output terminal, the conductive pattern being formed in the vicinity of the input/output terminal.

Abstract: A package substrate structure includes: a substrate having a first surface and an opposing second surface and characterized by a plurality of wire-bonding pads provided on the first surface of the substrate, a plurality of ball-implanting pads provided on the second surface of the substrate, and at least a cavity formed to penetrate the first and second surfaces of the substrate; a metal board mounted on the second surface of the substrate and covering the cavity, wherein the metal board has a thickness greater than that of the ball-implanting pads and has an area greater than that of the cavity; and solder masks disposed on the first and second surfaces of the substrate respectively and having at least a solder-mask cavity corresponding in position to the cavity of the substrate, the solder masks further having a plurality of openings for exposing the wire-bonding pads, the ball-implanting pads and the metal board.

Abstract: Disclosed is a lead frame and a semiconductor device including the same. The lead frame is provided with a die pad, and first, second and third lands sequentially arranged on an outer circumferential edge. The lead frame can separate the first and second lands or the die pad and the first land using a plating layer formed on the lead frame as a mask, instead of using a separate mask by etching after the application of the encapsulant. As a result thereof, a plurality of lands can be formed at low cost, in comparison with a conventional method. Additionally, the first, second and third lands are exposed to the outside through a lower portion of an encapsulant, and can be surface mounted on an external device through the first, second and third lands.

Abstract: Provided is an electrode pad for mounting an electronic component on a surface of a circuit board. The electrode pad includes first and second electrode parts facing each other, and third and fourth electrode parts facing each other. The third and fourth electrode parts are disposed adjacent to the first and second electrode parts for forming corners of the electrode pad together with the first and second electrode parts. At least one of the first to fourth electrode parts includes a chamfered surface formed by cutting a corner of the at least one of the first to fourth electrode parts forming the corner of the electrode pad. Therefore, when the electrode pad is used for mounting an electronic component, the width of an outer electrode of the electronic component can be sufficiently increased, and thus the shape or size of the outer electrode can be easily adjusted.

Abstract: A cut-edge positioning type soldering structure and a method for preventing a pin deviation can prevent a plurality of pins of an electronic component from being deviated when the pins are soldered onto a printed circuit board by a solder, and each of at least two solder pads includes at least two cut edges, and the solder pads are installed in an alignment direction on the printed circuit board, such that the cut-edge positioning type soldering structure and the method for preventing a pin deviation can improve the efficiency of manufacturing processes and reduce the manufacturing cost.

Abstract: A circuit board surface structure and a fabrication method thereof are proposed. The circuit board surface structure includes: a circuit board having a plurality of electrically connecting pads formed on at least one surface thereof; a first and a second insulating protective layers formed on the surface of the circuit board in sequence; first and a second openings respectively formed in the first and second insulating protective layers to expose the electrically connecting pads on the surface of the circuit board, wherein the first and second openings have narrow top and wide bottom and the diameter of the first openings is bigger than that of the second openings; and conductive elements formed in the first and second openings on surfaces of the electrically connecting pads. The present structure facilitates to strengthen the bonding between the conductive elements and the corresponding electrically connecting pads.

Abstract: A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.

Abstract: A method and system for a FET cell is presented. The FET cell includes multiple individual transistors and interconnect bumps that are configured to flip-chip connect to a substrate. The substrate may have the majority of a matching structure for the FET cell. Furthermore, the FET cell may include a stability circuit in communication with the terminals of the individual transistors and further in communication with the interconnect bumps. Additionally, different materials can be used in combination in the FET cell and the separate substrate having the majority of the matching structure. Various materials may be more efficiency used in a FET cell, while other materials are suitable for the separate substrate.

Abstract: A component built-in wiring board is provided. The component built-in wiring board 10 includes a core substrate 11, a first component 61, a first built-up layer 31 and a capacitor 101. The core substrate 11 has a housing hole 90 and the first component 61 is housed in the housing hole 90. A component mounting region 20 capable of mounting a second component 21 is provided in a surface 39 of the first built-up layer 31. The capacitor 101 has electrode layers 102 and 103 and a dielectric layer 104. The capacitor 101 is embedded in the first built-up layer 31 such that a first front surface 105 and a second front surface 106 in the electrode layer 102 and a first front surface 107 and a second front surface 108 in the electrode layer 103 are disposed in parallel with the surface 39 of the first built-up layer 31.

Abstract: A wiring substrate includes a plurality of electrode terminals, to which external connection terminals of an electronic component are coupled, arranged in a row on one principal surface thereof, wherein the electrode terminals each include: a first linear portion; a second linear portion extending from an end of the first linear portion in a direction different from a direction of the first linear portion; and a bent portion that is a part where the first linear portion and the second linear portion are connected.

Abstract: A mounting structure includes: an electronic component including: a functional element having a predetermined function; a first resin protrusion section having a surface covered by a covering film including a conductive section electrically connected to the functional element; and a second resin protrusion section that is disposed inside an area surrounded by the first resin protrusion section, and has adhesiveness at least on a surface of the second resin protrusion section, and a base member having a connection electrode and adapted to mount the electronic component. In the structure, the second resin protrusion section mounts the electronic component on the base member in a condition in which the conductive section of the covering film has conductive contact with the connection electrode due to elastic deformation of the first resin protrusion section.

Abstract: The invention provides a printed circuit board capable of mounting BGA or other IC package of narrow terminal interval by using through-holes of conventional size. On one principal surface of printed circuit board (1), soldering lands (2a), (2b), (2c), and (2d) for connecting solder balls are disposed in lattice. Central point (B) of through-hole (3) is set eccentric to the side of soldering land (2a) at the same potential as through-hole (3), remote from intersection (A) formed by diagonal line (200ab) linking soldering lands (2a) and (2b) and diagonal line (200cd) linking soldering lands (2c) and (2d).

Abstract: Disclosed is a portable terminal, including a first circuit board coupled to a main body and having a first connection terminal mounted on a surface thereof; a second circuit board coupled to the main body so as to cover at least a portion of the first circuit board, having a first area where an intermediate connection terminal contacting the first connection terminal is mounted on a surface thereof, and a second area where a second connection terminal electrically connected to the intermediate connection terminal is mounted on a surface thereof; and an electronic component having at least a portion thereof contacted by the second connection terminal, and for being electrically connected to the first circuit board.

Abstract: A land pattern, a method of manufacturing a printed circuit board (PCB) and a PCB incorporating a land pattern. In one embodiment, the land pattern includes: (1) a quadrilateral component outline area having diagonally opposed first and second corners and diagonally opposed third and fourth corners, defined according to a body configuration of a particular component type and located on a surface of a substrate and (2) first and second exposed conductive pads located within said area respectively proximate said first and second corners, coupled to respective first and second circuit conductors of said substrate, configured according to a terminal configuration of said type and separated from said third and fourth corners such that a component of said particular component type may be placed on the land pattern in multiple orientations without causing a short circuit.

Abstract: A cut-edge positioning type soldering structure and a method for preventing a pin deviation can prevent a plurality of pins of an electronic component from being deviated when the pins are soldered onto a printed circuit board by a solder, and each of at least two solder pads includes at least two cut edges, and the solder pads are installed in an alignment direction on the printed circuit board, such that the cut-edge positioning type soldering structure and the method for preventing a pin deviation can improve the efficiency of manufacturing processes and reduce the manufacturing cost.

Abstract: A bonding pad structure is disclosed, which is composed of two bonding pad units that are symmetrically disposed with respect to an axial line. Each bonding pad units is further composed of at least two bonding pads, i.e. each bonding pad unit is composed of at least one first bonding pad and at least one second bonding pad. In an embodiment, the first bonding pad is arranged next to the axial line and the second bonding pad is arranged at a side of the corresponding first bonding pad away from the axial line while enabling the first bonding pad and the corresponding second bonding pad to be interconnected to each other by a first neck portion. Thereby, a plurality of solder areas of different sizes can be formed by the interconnecting of the at least two bonding pad units that can be used for soldering electronic components of different sizes.

Abstract: A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate.

Abstract: A surface mountable device includes a ceramic substrate including a first principal surface, a second principal surface, and a side surface connecting the first principal surface to the second principal surface, a terminal electrode disposed on the first principal surface, and a first conductor for appearance inspection extending continuously from the terminal electrode to the side surface and having a width smaller than the width of the terminal electrode.

Abstract: A supporting component (1) adapted for being mounted on a substrate (11) and for serving as a support for a surface mounted device (15) comprises a body (2) having a first surface (3) adapted for being mounted on the substrate (11), and a second surface (4) being adapted for supporting the surface mounted device (15). The second surface (4) is inclined in relation to the first surface (3). The supporting component (1) further comprises a first supporting component conductor (6) adapted for forming an electrical contact between a first substrate conductor (12) of the substrate (11) and a first electrode (16) of the surface mounted device (15). In a method of mounting a surface mounted device (15) in an inclined manner on a substrate (11) the supporting component (1) is mounted on the substrate (11) with the surface mounted device (15) on top of it.

Abstract: A printed wiring board includes a built-in semiconductor element. A protective film is formed on a semiconductor element-mounted surface of a base substrate to which the built-in semiconductor element is connected to protect the semiconductor element-mounted surface excepting a mounting pad. Upper and side surfaces of the built-in semiconductor element are covered with a first insulating film formed by filling a sealing material. The first insulating film is covered with a second insulating film formed of an insulating resin melted from an insulating layer that is provided in side and upper portions of the built-in semiconductor element.

Abstract: The present invention is an electrode 10 so provided as to be soldered to an electronic component 12 and, when the electronic component 12 is mounted on a substrate 13, soldered to the substrate 13. The electrode 10 includes a column-like electrode body 11 soldered to the electronic component 12 and to the substrate 13. The electrode has grooves as an air discharging device discharging the air 15a in air voids 15 generated within the solder 14 between joint surfaces 11a, 11b of the electrode body 11 and the electronic component 12 or the substrate 13 when the electrode body 11 is soldered to the electronic component 12 or the substrate 13.

Abstract: An interposer (20) is used for decoupling a microchip (10) on a circuit board (30). The interposer (20) contains on its upper and lower surfaces structured metal layers (26a-26d) for attachment to the microchip (10) and the circuit board (30), respectively. Inside the interposer, there are two sets of mutually isolated metal structures (21, 22) extending substantially perpendicular to the upper and lower surfaces of said interposer (20). The first set (21) extends closer towards the upper surface than the second set (22), while said second set (22) extends closer towards the lower surface than said first set (21).

Abstract: A connection structure for a chip-on-glass (COG) driver IC and a connection method therefor are provided. The connection structure includes a driver IC having a surface provided with a plurality of polymeric bumps and a plurality of conductive bumps, and the height of the polymeric bumps in relation to the surface is smaller than that of the conductive bumps. When the driver IC is bonded to a glass substrate via an adhesive film by thermal compression bonding, the polymeric bumps are embedded into the adhesive film, and a gap is defined between the polymeric bumps and the glass substrate. Thus, the polymeric bumps can increase the contact area between the driver IC and the adhesive film, and enhance the connection reliability between the conductive bumps and pads of the glass substrate.

Abstract: A mounting structure is provided that can allow gaseous matter generated when performing a heat treatment to escape to outside efficiently. A mounting structure 10 includes a substrate 1 having electrodes 2a and 2b, an electronic component 3 having electrodes 21a and 21b, joints 15a and 15b that electrically connect the electrodes 2a and 2b of the substrate 1 and the electrodes 21a and 21b of the electronic component 3 and also fix the electronic component 3 to the surface of the substrate 1, and a convex portion 4 that abuts against the electrode 2a of the substrate 1 and the electrode 21a of the electronic component 3 and is used as a spacer.

Abstract: An interconnection system with capacitors integrated into a printed circuit board footprint of an electrical connector. One end of each capacitor shares a pad on the printed circuit board with a contact tail of a conductive element in a connector. The shared pads are not connected through vias to internal circuit structures. Rather, a via, such as which would conventionally be formed as part of the connector mounting pad, is formed as part of a separate, adjacent pad. A second end of the capacitor is attached to the adjacent pad, forming an electrical connection between the conductive element and the via through the capacitor. Incorporating capacitors into the footprint reduces the number of vias required, which improves signal integrity. The capacitors may be placed on the printed circuit board separately from the connector or may be incorporated into the connector, allowing the connector and capacitors to be placed in one operation.

Abstract: The present invention relates to a package having an inner shield and a method for making the same. The package includes a substrate, a plurality of electrical elements, a molding compound, an inner shield and a conformal shield. The electrical elements are disposed on the substrate. The molding compound is disposed on a surface of the substrate, encapsulates the electrical elements, and includes at least one groove. The groove penetrates a top surface and a bottom surface of the molding compound and is disposed between the electrical elements, and there is a gap between a short side of the groove and a side surface of the molding compound. The inner shield is disposed in the groove and electrically connected to the substrate. The conformal shield covers the molding compound and a side surface of the substrate, and electrically connects the substrate and the inner shield.

Abstract: A universal solder pad is used with a plurality of SMD components having different sizes. Each SMD component includes a first conductive part and a second conductive part. The universal solder pad includes a first pad unit and a second pad unit. The first and second pad units are electrically connected to the first and second conductive parts of the SMD component, respectively. Each of the first and second pad units includes a main portion and a first extension portion. The first extension portion is extended from a first sidewall of the main portion and includes a first border, a second border and a third border. The second border and the third border of the first extension portion are parallel with each other for facilitating alignment of the first and second conductive parts of the SMD component with respect to the first pad unit and the second pad unit.

Abstract: According to an aspect of the present invention, there is provided a printed circuit board including: a semiconductor package including a parallelepiped body, and solder balls provided on a face of the parallelepiped body; a printed wiring board including a mounting face, the mounting face configured to mount the plurality of solder balls; a first bonding member including a first glass transition temperature, the first bonding member disposed around the parallelepiped body and configured to bond the semiconductor package and the printed wiring board; an electronic component mounted on the mounting face on an opposite side to the semiconductor package with respect to the first bonding member; and a second bonding member including a second glass transition temperature that is higher than the first glass transition temperature, the second bonding member disposed onto the mounting face to cover the electronic component.

Abstract: A multi-layer printed wiring board including a first substrate having an opening and having external terminals positioned to be connected to a package substrate, a second substrate laminated to the first substrate and having external terminals positioned to be connected to a mother board, the second substrate having a metallic layer portion in the opening of the first substrate and non-through holes filled with conductive material and connected to the metallic layer portion, and an IC component having terminals and loaded in the opening of the first substrate such that the terminals of the IC component face an opposite side of the metallic layer portion of the second substrate. The IC chip is accommodated in the opening such that the metallic layer portion and non-through holes of the second substrate irradiate heat generated by the IC chip.

Abstract: The embodiments described herein provide for a packaging configuration that provides leads or connections for a packaging substrate from opposing surfaces of a package. Through silicon vias (TSV) are provided in order to accommodate additional input/output (I/O) pins that smaller dies are supporting. Various combinations of packages are enabled through the embodiments provided.

Abstract: An electronic carrier board is provided, including a carrier, at least two paired bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings corresponding in position to the two bond pads. The openings are aligned in the same direction and expose at least a first sidewall and a second sidewall of each of the two bond pads. The first sidewall is perpendicular to an alignment direction of the bond pads and the second sidewall is parallel to the alignment direction of the bond pads. A distance between the first sidewall of at least one of the bond pads and a corresponding side of a corresponding one of the openings is at least about 50 ?m greater than a distance between the second sidewall of the at least one bond pad and a corresponding side of the corresponding opening.

Abstract: A packaged integrated circuit includes an integrated circuit and a package substrate. A trace in the package substrate includes a first portion and a second, high-inductance, portion. The high-inductance portion of the trace is proximate to a port of the integrated circuit and provides a selected inductance operating in cooperation with the capacitance of the port to reduce return loss from the port. The first portion of the trace is part of a transmission line having a characteristic impedance.

Abstract: A smart card is provided including a body with a cavity, an IC chip inserted into the cavity, and a universal PCB on which the IC chip can be mounted and electrically contacted regardless of its size, type and bonding structure. The universal PCB comprises groups of contact pads suitable for contacting IC chips of different sizes and designs.

Abstract: A low-temperature co-fired ceramics (LTCC) substrate includes a plurality of substrate units and at least one cutting pattern. The cutting pattern is disposed between neighboring two of the substrate units. A semiconductor package including the LTCC substrate is also disclosed.

Abstract: A circuit board device includes a circuit board comprising a mounting area, and first and second power lines and a ground pad formed on the mounting area, and a vertical multilayer chip capacitor (MLCC) comprising a capacitor body, a plurality of first and second polarity inner electrodes, first and second outer electrodes, and a third outer electrode, wherein the first and second power lines are separately disposed on the mounting area, connected to the first and second outer electrodes, and electrically connected to each other only by the vertical MLCC, and the ground pad is disposed between the first and second power lines and connected to the third outer electrode.

Abstract: A solution for mounting decoupling capacitors on a printed wiring board (PWB) used for mounting a high performance ball grid array (BGA) device is described. The via array that connects the BGA device is modified, the modification being that at least a portion of one row of said vias array is missing at least two adjacent vias. The missing vias are replaced by respective shared vias in an adjacent row, and the shared vias are connected to either a power supply or a power return. The shared vias are also provided with via pads on the other side of said PWB, and a decoupling capacitor can be electrically connected across the pair of via pads to decouple the power supply and the power return at the two adjacent vias.

Abstract: This publication discloses an electronics module and a method for manufacturing it. The electronics module includes at least one component (6) embedded in an insulating-material layer (1), which has a first contacting surface, in which there are first contact terminals (7), from which the component (6) is connected electrically to the conductor structures contained in the electronics module. In addition, the component (6) has a second contacting surface opposite to the first contacting surface, in which there is at least one second contact terminal (7?), from which the component (6) is connected electrically to the conductor structures contained in the electronics module. With the aid of the invention, it is possible to achieve an electronic-module construction that saves space compared to the prior art.

Abstract: Venting for component mounting pads of surface mount circuit boards allows the escape of gases from the junction between an electrical component and its associated mounting pad during soldering and facilitates a more complete and effective solder joint between the component base and pad. The venting may be accomplished by either one or more through holes in the board through the pads to allow undesirable gases to escape to the underside of the board, or by one or more solder free channels formed in the pad to allow the gases to escape through the periphery of the pad.

Abstract: A circuit board including: a substrate having a mounting area for mounting a vertical multilayer chip capacitor having first and second external electrodes of a first polarity and a third external electrode of a second polarity; first to third pads arranged on the mounting area, the first and second pads having the first polarity and disposed separately from each other on the mounting area, the third pad having the second polarity and disposed between the first and second pads to be connected to the third external electrode; at least one first via formed in the substrate and connected to the first pad; at least one second via formed in the substrate and connected to the second pad; and a plurality of third vias formed in the substrate and connected to the third pad.