Abstract: An integrated circuit package is provided with a ball landing area having a conductive structure for interlocking a conductive ball to the ball pad. The conductive structure improves the attachment strength between an integrated circuit package and an printed circuit board. In an exemplary embodiment, the locking structure is a conductive material added to the surface of the ball pad to provide a nonplanar interface, such as a dome or a step, which interlocks the conductive ball to the ball pad. The improved package construction increases the area of contact, moves the shear plane to a higher and larger portion on the conductive ball, and/or prevents a crack from propagating along a flat plane across the ball joint. This package construction maintains the small size of the ball land areas and the package, increases the life of the integrated circuit package, while offsetting the problem of package warpage.

Abstract: The present invention provides a high-frequency switch comprising: a high-frequency circuit board 12 including an MIC substrate 16, a microstrip line 24 disposed on a front surface of the MIC substrate 16, and a signal wiring layer 26 and a front surface grounding conductor (I) 20a disposed along the microstrip line 24; a plurality of bumps 28 disposed on the microstrip line 24, the signal wiring layer 26, and the front surface grounding conductor (I) 20a; and a semiconductor chip 14 disposed on the high-frequency circuit board 12 through the plurality of bumps 28; wherein a gate electrode of a transistor of the semiconductor chip 14 is connected to the signal wiring layer 26 of the high-frequency circuit board 12 through one or more of the plurality of bumps 28; a source electrode is connected to the front surface grounding conductor (I) 20a through one or more of the plurality of bumps 28; and a drain electrode is connected to the microstrip line 24 through one or more of the plurality of bumps 28.

Abstract: A plurality of chips are mounted on a substrate, coupling portions between the chips and the substrate are sealed, the chips have rear surfaces thereof collectively polished, and the substrate with the chips thereon are separated into independent semiconductor devices.

Abstract: A single-step bumping/bonding method for forming a semiconductor package of two electronic substrates electrically connected together by solder bumps. In the method, a first electronic substrate is provided equipped with a first plurality of conductive pads formed in an insulating material layer, the plurality of conductive pads each having an aperture formed therethrough for receiving a solder material when the first electronic substrate is positioned juxtaposed to a second electronic substrate equipped with a second plurality of conductive pads such that solder bumps may be formed bonding the first plurality of conductive pads to the second plurality of conductive pads. One of the two electronic substrates may be a silicon wafer, while the other may be a printed circuit board or a silicon wafer.

Abstract: A bump connection is formed by stacking at least two metallic balls of different kinds of metals on a conductor of an electronic component such as a semiconductor device. The bump connection is obtained by forming the metallic balls using metallic wires. An apparatus for forming the connection includes a support, capillary member for having a wire pass therethrough, a pair of clamps for clamping the wire, and a “torch” (e.g., electrode, gas flame) which heats the tip of the wire, forming the ball. Successive balls can be formed by this apparatus atop the initially formed ball to provide a stacked configuration.

Abstract: A multi-layer circuit board for mounting an electronic part such as a semiconductor chip having as many pins as 40×40 pins arranged as an array on the side of the mounting surface or a semiconductor device has a plurality of layers, each layer disposed one above another and containing lands arranged as an array disposed at an angle to the edge of the mounting surface. On each layer a plurality of the lands have connected thereto circuits extending from the lands to the edge of the mounting surface, and also lands not connected to circuits. Those lands not connected to circuits are connected with via holes to orther layers.

Abstract: This invention mounts a semiconductor device having a plurality of electrodes to a substrate. A bump electrode having a pointed tail is formed on the electrode. The concave mounting pad is formed on the substrate. A sealing resin covers the substrate. And the tail of the bump electrode is buried into the sealing resin by putting the semiconductor device close to the substrate. Further, the semiconductor device is pressed to the substrate. And the sealing resin is hardened by heating.

Abstract: The electronic circuit unit of the present invention is provided with the broad width lands and the thin width lands tied with the broad width lands, which are configured by a solder resist that is formed on the surface of the circuit board. Owing to this configuration, the solders placed on the thin width lands are drawn toward the broad width lands, which increases the quantity of the solder buildup on the broad width lands, and accompanied with this increase, swells the heights of the solder buildup on the broad width lands. Thus, the electronic circuit unit of the present invention ensures the soldering.

Abstract: A printed-circuit board of the present invention, comprises a circuit substrate 1; a plurality of patterned wires 3 formed on a surface of said circuit substrate 1; a plurality of lands 2, each land 2 connected to at least one of said patterned wires 3 through an end portion 3a thereof; and a protection layer 6 with a plurality of openings 7, covering the surface of said circuit substrate 1, wherein said land 2 and said end portion 3a connected thereto are exposed in the associated opening 7 of said protection layer 6.

Abstract: Resistance and parasitic inductance resulting from interconnection of semiconductor chips in power modules are reduced to negligible levels by a robust structure which completely avoids use of wire bonds through use of ball bonding and flip-chip manufacturing processes, possibly in combination with chip scale packaging and hourglass shaped stacked solder bumps of increased compliance and controlled height/shape. Turn-off voltage overshoot is reduced to about one-half or less than a comparable wire bond packaged power module. Hourglass shaped solder bumps provide increased compliance and reliability over much increased numbers of thermal cycles over wide temperature excursions.

Abstract: The specification describes a high density IC BGA package in which one or more IC chips are wire bonded to a BGA substrate in a conventional fashion and the BGA substrate is solder ball bonded to a printed wiring board. The standoff between the BGA substrate and the printed wiring board to which it is attached provides a BGA gap which, according to the invention, accommodates one or more IC chips flip-chip bonded to the underside of the BGA substrate. The recognition that state of the art IC chips, especially chips that are thinned, can easily fit into the BGA gap makes practical this efficient use of the BGA gap. The approach of the invention also marries wire bond technology with high packing density flip-chip assembly to produce a low cost, high reliability, state of the art IC package.

Abstract: A semiconductor device in a chip size package form having a high durability and reliability and realizing a small size with high density, and an electronic apparatus mounting the same, connected to a motherboard by soldering, comprising a semiconductor chip wherein bumps are formed on pad portions thereof; an interposer supporting the bumps mechanically and having through-holes wherein conductors are formed and connected to the bumps electrically; and a sealing resin buried between the semiconductor chip and the interposer, wherein the interposer is formed from a material having a higher glass transition temperature than a curing temperature of the sealing resin, a coefficient of linear expansion of the interposer is of a value substantially intermediate between that of the motherboard and that of the semiconductor chip, and/or the interposer is formed from a material having a bending strength of 400 MPa or more.

Abstract: A film carrier tape includes: an insulating film; a plurality of lead terminals that are each disposed on the insulating film and provided with an end connected to a semiconductor chip; and electrical sorting pads disposed at another end of each of the plurality of the lead terminals, wherein at least some of the electrical sorting pads are configured so as to form pad groups each composed of two or more of the electrical sorting pads, and the electrical sorting pads composing each of the pad groups are positioned adjacent to one another so as to simultaneously contact a measurement terminal of a tester and so as to be electrically separated from one another.

Abstract: An adapter for a surface mount device, the adapter including an insulating body having offset first and second surfaces; a pattern of surface mount solder pads formed on the first surface; a pattern of signal carriers communicating between the first and second surfaces, each of the signal carriers being at least partially exposed in an area between the first and second surfaces and adjacent to the second surface; and a plurality of signal lines electrically coupling one or more of the surface mount solder pads with predetermined ones of the signal carriers.

Abstract: A multi-chip module includes bare IC chips mounted on respective areas of a printed wiring board. Outer electrode pads on the peripheries of the board are soldered to another printed wiring board such as a motherboard. Lead pads and the outer electrode pads are interconnected through a circuit pattern, through holes, and interstitial via holes. The circuit pattern is disposed on a die bonding surface of the bare IC chips for which insulation is not necessary.

Abstract: A high-density mounted device, in which a plurality of semiconductor devices such as semiconductor element or module boards, are mounted on a wiring board, includes an adhesive sheet which is interposed between the wiring board and the semiconductor device. The adhesive sheet has a sheet-like base board made of an adhesive member and a plurality of conductive Sections provided at predetermined pitches in the sheet-like base member. The conductive sections are electrically insulated from each other, and extend from one side of the sheet-like base member to the other side thereof, and enable electrical connection between the electrode terminals of the wiring board and the electrode terminals of the semiconductor device. The conductive sections work as heat conductive channels between the wiring board and the semiconductor device.

Abstract: System of components for hybridization including a first component (410) with a first set of hybridization studs (414), and at least a second component (412) with second hybridization studs (450), the first and second studs being respectively associated in pairs of studs, one of the first and one of the second studs, with at least one pair of studs, equipped with a projection (418) of meltable material and the other aforesaid first and second studs of the pair of studs, referred to as contact studs (450, 450a, 450b), having a surface wettable by the meltable material. According to the invention at least one part of the contact stud (450) forms a protuberance (452). Application to manufacturing of electronic, electro-optic and mechanical components.

Abstract: Switching noise within an LGA-packaged or PGA-packaged IC Vdd and IC Vss nodes is reduced by spreading the electrical current in the bypass path to reduce the effective current loop area, and thus reduce the energy stored in the magnetic field surrounding the current path. This result is achieved by minimizing the horizontal components of the linkage paths between the IC nodes to be bypassed and the bypass capacitor. Since effective inductance Leff seen by the bypass capacitor is proportional to magnetic energy, Leff is reduced over a broad band of frequencies. For each bypass capacitor, a pair of conductive vias is formed. A first via is coupled to the LGA package Vcc plane and to the IC Vdd node, and a second via is coupled to the LGA package Vss plane and to the IC Vss node.

Abstract: A method and apparatus for encapsulating a BGA package. Specifically, the molded packaging material is configured to provide cups on the backside of the package, opposite the semiconductor device. The cups expose pads on the substrate and are configured to receive solder balls.

Abstract: An adapter is provided for mounting a ball grid array device on a pin-type integrated circuit socket, and includes a base plate and an interfacing plate. The base plate has a device mounting side formed with a plurality of solder pads thereon. The base plate is further formed with a plurality of upper through holes, each of which corresponds to one of the solder pads. The interfacing plate is formed with a plurality of lower through holes that correspond respectively with the upper through holes and are coaxial therewith. The interfacing plate further has a socket confronting side with a plurality of insert pins depending therefrom. Electrical conductors are provided on the base plate and the interfacing plate for connecting electrically and respectively the solder pads and the insert pins via the upper and lower through holes.

Abstract: A system for delivering power to a processor enables a DC-to-DC converter substrate to be secured to the processor carrier in the Z-axis direction. The ability to assemble converter to the processor in this way facilitates assembly compared to systems in which the converter is plugged in to the processor carrier in the direction substantially parallel to the surface of the motherboard.

Abstract: The present invention provides a semiconductor device of the BGA (ball grid array) package type comprising: a semiconductor chip 1; a plurality of wiring layers 1B arranged on the semiconductor chip via an insulation layer 1A, each of the wiring layers having a chip-side land block 1C as a signal I/O region; a circuit substrate having a plurality of wiring lines; and a plurality of solder balls 2 each to be arranged on the chip-side land block for connecting the wiring layers to corresponding wiring lines on the circuit substrate; wherein each of the chip-side land blocks 1C has a land protrusion block 3 extending into the solder ball 2. The land protrusion block 3 increases the attachment strength between the chip-side land block 1C and the solder ball 2 and suppresses growth of a crack generated in the solder ball 2 due to a thermal stress.

Abstract: A printed wiring board with an increased strength of solder is provided by preventing solder bridge formation and increasing the amount of solder adherent thereto. A land (1) serving as a soldering foundation is formed in a star-shape, to minimize the proximal peripheral length (L2) between adjacent lands spaced distance (L1) apart, thus reducing the possibility of solder bridge formation. Since the star-shaped land (1) has a greater area than a rhombic land of identical size, the amount of solder adherent thereto is greater than that of the rhombic land, thus enabling to increase the strength of solder.

Abstract: A solder interconnection between a module and printed circuit board or card is provided by a plurality of solder connections arranged in a micro grid array joining solder wettable pads on a major surface of the module to a corresponding set of solder wettable pads of the printed circuit board or card. The solder connections are column shaped with the height of each connection being at least about 1.4 times the diameter of the connection.

Abstract: A header containing a semiconductor die, method of manufacture thereof and electronic device employing the same. In one embodiment, the header includes first and second contacts, and an intermediate body. The intermediate body includes an insulated section interposed between the first and second contacts and has a cavity therein. The intermediate body also includes a semiconductor die, located within the cavity, adapted to condition a signal passing through at least a portion of the header.

Abstract: A double-sided circuit board of which a solder conductor is prevented from deformation in a cycling test so as to maintain high connection reliability, comprises an insulating layer 2 made of an organic high molecular weight resin and a circuit 3 provided on each side of the insulating layer 2, the circuits 3 on both sides being electrically connected through via-holes filled with a conductor 4 made of solder having a metal powder 6 dispersed therein.

Abstract: Precision alignment of one or more parts on a common carrier is described. A self-aligned common carrier includes a carrier substrate having one or more pockets formed in the substrate. Each pocket includes a side profile formed in the pocket. A chip having an identical side profile that complements the side profile in the pocket is mounted to the carrier substrate by inserting the chip into the pocket. The complementary side profiles result in near perfect self-alignment between the chip and at least two orthogonal planes of the carrier substrate. The chip and the carrier substrate can be made from a single crystal semiconductor material and the side profiles can be formed by anisotropic etch process that selectively etches the chip and the substrate along a predetermined crystalline plane. The chip and the carrier substrate can be single crystal silicon having a (100) crystalline orientation and the side profiles can be formed by selectively etching the silicon along a (111) crystalline plane.

Abstract: Switching noise within an LGA-packaged or PGA-packaged IC Vdd and IC Vss nodes is reduced by spreading the electrical current in the bypass path to reduce the effective current loop area, and thus reduce the energy stored in the magnetic field surrounding the current path. This result is achieved by minimizing the horizontal components of the linkage paths between the IC nodes to be bypassed and the bypass capacitor. Since effective inductance Leff seen by the bypass capacitor is proportional to magnetic energy, Leff is reduced over a broad band of frequencies. For each bypass capacitor, a pair of conductive vias is formed. A first via is coupled to the LGA package Vcc plane and to the IC Vdd node, and a second via is coupled to the LGA package Vss plane and to the IC Vss node.

Abstract: In a substrate on which a ball grid allay type electrical part is mounted includes a substrate body, a normal land, an integrated land and a connection reinforcement section. The substrate body provided with a ball grid allay type electrical part. On the normal land, a normal electrode of the ball grid array type electrical part is connected. On the integrated land, a plurality of integrated electrodes of the ball grid allay type electrical part is connected.

Abstract: An electrically conductive wire wound into a conical coil 1 with leads from the small and large ends of the coil. The coil is filled with fine-grained magnetic material 11, and is mounted in a thin-walled, electrically non-conductive carrier 21 designed for precise automated assembly onto a circuit board 15. The wire leads are plastic-welded onto the carrier, and no metallic pads are used, greatly increasing the effective bandwidth of the choke. The small end 4 of the coil is positioned precisely on a micro-strip 17 on the circuit board. Attachment of the wire lead from the small end of the coil to the microstrip is done with minimum lead length and minimum conductive material for the highest possible frequency response. Precise coil positioning, minimal lead length, and a totally non-conductive carrier virtually eliminates electrical reflections and resonances to yield a broadband choke with exceptional frequency range.

Abstract: A method and structure for reducing thermally induced strains on the solder joints that couple a ball grid array (BGA) module to a circuit card, so as to improve the fatigue life of the BGA module. The thermally induced strains arise from a mismatch in thermal expansion coefficient between the dielectric substrate of the BGA module and the dielectric board of the circuit card. The method generates void annular regions around portions of the BGA dielectric substrate to which the BGA solder balls are to be attached and/or around portions of the circuit card dielectric material to which the BGA module is to be attached. This results in the formation of dielectric islands or peninsulas that bound the solder balls of the BGA module after installation on the circuit card. The dielectric islands or peninsulas thus formed serve to increase the effective height over which the differential expansion is accommodated, thereby reducing the strains throughout the solder joints.

Abstract: A bump connection structure and a method of attachment to integrated circuits or packages is provided which comprises a prefabricated core structure coated with solderable metal layers to form a composite bump. Said composite bump is aligned to contact pads of the chip or package which have been coated with solder paste, and the assembly heated to form a metallurgical bond. The prefabricated core structures are comprised of metal, plastic or ceramic of the size and dictated by package standards. The connection structure is preferably lead free.

Abstract: Electrical connection device for forming electrical connection between a first portion and a second portion of a semiconductor device. The first portion is set near or in contact with the second portion. The first and second portions are electrically connected by spraying fine metal particles of gold, nickel or copper in a carrier gas of helium, argon, hydrogen or nitgrogen on the first and second portions to form a metal bump. Prior to spraying the fine metal particles to form the metal bump, hard particles of titanium, copper, hafnium, zirconium or vanadium may be sprayed on the first and second portions to remove contamination layers.

Abstract: A flip-ship structure having a semiconductor substrate including an electronic device formed thereon, a contact pad on said semiconductor substrate electrically connected to said electronic device, a passivation layer on said semiconductor substrate and on said contact pad wherein said passivation layer defines a contact hole therein exposing a portion of said contact pad, an under-bump metallurgy structure on said passivation layer electrically contacting said portion of said contact pad that is exposed; and a solder structure on said under-bump metallurgy structure opposite said semiconductor substrate, said solder structure including an elongate portion on said elongate portion of said metallurgy structure opposite said contact pad and an enlarged width portion on said enlarged width portion of said metallurgy structure opposite said passivation layer.

Abstract: A component for forming solder connections includes a diectric base having a non solder-wettable surface, a plurality of solder-wettable pads exposed to said surface, and an electrically conductive potential plane element having a non solder-wettable surface overlying the surface of the base in proximity to the pads but spaced from said pads. The non-wettable surface of the potential plane element may include a metal such as nickel or a metal oxide. The potential plane element thus performs the functions of a solder mask to prevent solder from forming short circuits between adjacent pads, and may also act as a ground plane, power plane or shielding element.

Abstract: An adapter is provided for mounting a ball grid array device on a pin-type integrated circuit socket, and includes a base plate and an interfacing plate. The base plate has a device mounting side formed with a plurality of solder pads thereon. The solder pads correspond to and are adapted for surface mounting of solder balls of the ball grid array device thereon. The base plate is further formed with a plurality of upper through holes, each of which corresponds to one of the solder pads. The interfacing plate is formed with a plurality of lower through holes that correspond respectively with the upper through holes. The interfacing plate further has a socket confronting side with a plurality of insert pins depending therefrom. The insert pins correspond to and are adapted for insertion into pin holes in the integrated circuit socket in order to establish electrical contact with board mounting pins that are disposed in the pin holes.

Abstract: A semiconductor device includes a ball grid array substrate including an upper insulating layer of laminated insulating layers, an intermediate insulating layer, and a lower insulating layer of laminated insulating layers; lines on each top surface of the insulating layers included in the upper insulating layer, the intermediate insulating layer, and the lower insulating layer, respectively; and a semiconductor chip having electrodes connected to the lines, the semiconductor chip being connected with solder balls through via holes in each of the insulating layers, the solder balls being located on an outermost surface of the lower insulating layer.

Abstract: The substrate of the present invention mainly includes a plurality of bonding pads, a plurality of ball pads, a plurality of traces, a plurality of holes, a first wire and a second wire. The bonding pads and ball pads are located on a first surface of the substrate and are connected to one another by the traces. The first wire is arranged at the edge of the first surface of the substrate, the second wire is arranged at a slot area of a second surface of the substrate which is adhesively covered by a solder mask and further has two ends connecting to the first wire. The holes connect the first surface to the second surface. The traces are connected the bonding pads and ball pads of the first surface by passing through the corresponding holes and a slot area to the second wire of the second surface to form closed loops. In the slot area, the solder mask adhesively covers the traces.

Abstract: An LSI package structure having a smaller size in which the wiring length is shortened. The wiring structure for connecting the LSI 2 with the wiring board 1 comprises first connecting terminals 3 arrayed on the LSI 2 and second connecting terminals 6 arrayed on the wiring board 1. The first connecting terminals 3 are arrayed on the outer periphery 5 of the facing surface 4 which faces the wiring board 1 and the second connecting terminals 6 are arrayed on the interfacing surface 7 which intersects with the outer periphery 5. In such a structure, the wiring board 1 is similar to the LSI 2 in size. The facing surface 4 actually intersects with the intersecting face 7 for forming a intersecting line 8. The facing surface 4 substantially intersects with the intersecting face 7 along the intersecting line 8. Such a structure makes the size of the wiring board 1 smaller than that of the LSI 2.

Abstract: A BGA package is mounted on a multi-layer printed wiring board having a plurality of electrodes arranged in a matrix form through a plurality of solder bumps. In the most externally-located electrodes, a lead wire is formed to extend from a portion of the most-externally-located electrode located inside of a polygon formed by connecting each of the centers of adjacent most-externally-located electrodes. Therefore, the solder bumps are prevented from coming off the most-externally-located electrodes because a portion of the most-externally-located electrode to which stress caused by an external shock is intensively applied is located in an outside of the polygon. Thus, a contact failure between the BGA package and the multi-layer printed wiring board is prevented.

Abstract: A new interconnection scheme of a ball grid array (BGA) module is disclosed where a solder ball is connected to the BGA module by use of an electrically conducting adhesive The electrically conducting adhesive can be a mixture comprising a polymer resin, no-clean solder flux, a plurality of electrically conducting particles with an electrically conducting fusible coating and others. The solder balls in a BGA module can also be connected to a printed circuit board by use of another electrically conductive adhesive which can be joined at a lower temperature than the first joining to the BGA module. Additionally, an electrically conducting adhesive can be formed into electrically conducting adhesive bumps which interconnect an integrated circuit device to the BGA module.

Abstract: A module, such as a contact module for embedding an electronic device into a credit card, smart card, identification tag or other article, comprise a pattern of metal contacts having a first and a second surface and electrically-conductive vias built up on the first surface of the metal contacts. A layer of dielectric adhesive on the first surface of the pattern of metal contacts surrounds the electrically-conductive vias except the ends thereof distal from the metal contacts. An electronic device has electrical contacts connected to the exposed ends of the conductive vias, as by wire bonds or by flip-chip type connections.

Abstract: A method for making connections to a microelectronic device having bump leads thereon. A substrate is provided having a front surface and a plurality of electrically conductive posts extending upwardly from the front surface. The posts are disposed in groups, wherein the posts of each group define a gap therebetween. Contacts are provided extending generally horizontally outwardly from each post remote from the front surface of the substrate. The microelectronic device is assembled to the substrate and posts so that the bump leads penetrate into the gaps and engage the contacts which wipe against the bump leads as they are inserted.

Abstract: The present invention provides a ceramic circuit board including: a ceramic substrate; a plurality of metal circuit plates bonded to a surface of the ceramic substrate; and parts including semiconductor element integrally bonded to a surface of the metal circuit plates through a solder layer, wherein at least peripheral portion of one metal metal circuit plate to which the parts are solder-bonded and is adjacent to the other metal circuit plates is formed with a projection for preventing solder-flow. According to the structure described above, there can be provided a ceramic circuit board which is free from short-circuit due to the solder-flow or bonding defects of the parts thereby to have an excellent operating reliability, and is capable of being easily mass-produced with a high production yield.

Abstract: In a chip bonding method, first bonding bumps are applied to bonding electrodes of the chip, a first flexible circuit carrier is arranged on the chip, the flexible circuit carrier having cavities which are aligned with the bonding bumps, and second bonding bumps are applied to the first bonding bumps in such a way that bonding areas on the first flexible circuit carrier are in contact with the first and/or second bonding bumps.

Abstract: The specification describes a high density I/O IC package in which the IC chip is bonded to a silicon intermediate interconnection substrate (IIS), and the IIS is wire bonded to a printed wiring board. This marriage of wire bond technology with high density I/O IC chips results in a low cost, high reliability, state of the art IC package.

Abstract: A connection device for use in connection between two electronic components and a connection device provided on a first electronic component. The connection device includes two metal layers which have mutually different coefficients of thermal expansion, and a plurality of side wall pieces that are provided on the metal layers so as to form a connecting space for a second electronic component.

Abstract: A PCB having oval solder ball lands, and a BGA semiconductor package produced using such a PCB, are disclosed. The PCB has a plurality of conductive traces forming circuit patterns on at least one of an upper and a lower surface of a resin substrate. A plurality of solder ball lands are formed on the lower surface of the substrate and are electrically connected to respective upper surface conductive traces. At least a portion of the solder ball lands have an oval shape and a major axis. The oval solder ball lands are oriented such that their major axes are either radially directed relative to a center of the substrate, perpendicularly directed relative to a side edge of the substrate, or both radially and perpendicularly directed relative the center and a side edge of the substrate, respectively.

Abstract: A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.

Abstract: A surface mountable pin connector has a substrate or a circuit board carrier, which has a number of through holes or vias formed therein, and a number of connector pins, each of which is soldered into a respective one of the through holes with high melt temperature solder. A damming device or protrusion is located on each pin nearer to the shoulder than typical interference fit protrusions. The damming device is sized and shaped to completely block the through hole or via.