Abstract: Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.

Abstract: A method of fabricating a semiconductor package structure is provided. The structure is configured to include a base substrate, a die disposed on the base substrate, the die including a semiconductor device, a solder bump disposed on a surface of the die, and configured to discharge heat generated in the die to an outside; and a solder ball disposed on another surface, opposite to the surface, of the die, and configured to transmit a signal, which is produced by the semiconductor device of the die, to an external device.

Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.

Abstract: A semiconductor device assembly is provided. The assembly comprises a package substrate, a first stack of semiconductor dies having a first set of planform dimensions disposed over a first location on the substrate, a second stack of semiconductor dies having a second set of planform dimensions different from the first set disposed over a second location on the substrate, and an encapsulant at least partially encapsulating the substrate, the first stack and the second stack. The first stack of semiconductor dies has a first planform area, the second stack of semiconductor dies has a second planform area, and a sum of the first and second planform areas can be at least 50%, 67%, 75%, or even more of an area of the package substrate.

Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

Abstract: A circuit assembly is provided. The circuit assembly includes: a first bus bar and a second bus bar that are part of a power circuit; and a control board to which a control circuit configured to control current flow in the power circuit is mounted, the circuit assembly including: a semiconductor switching element including a drain terminal and a source terminal that are connected to the first bus bar and the second bus bar, respectively, and a gate terminal configured to receive input of a control signal from the control circuit configured to control current flow in the power circuit; and a third bus bar configured to electrically connect the gate terminal and the control board.

Abstract: A display device includes a display substrate with a display area, a first peripheral area, and a second peripheral area, the display area having first and second sides extending in directions crossing each other, the first peripheral area adjacent to the first side, and the second peripheral area adjacent to the second side, a first driving substrate attached to the first peripheral area, the first driving substrate including a first driving circuit portion and a first link wire connected to the first driving circuit portion, a second driving substrate attached to the second peripheral area, the second driving substrate including a second driving circuit portion and a second link wire connected to the second driving circuit portion, and a flexible circuit board attached to the first driving substrate, the flexible circuit board including a third link wire connected to the first and second link wires.

Abstract: A substrate structure includes a first portion, a second portion, and an intermedia portion disposed between the first and the second portion and the electrically connected business. The first portion includes a first fine redistribution layer (RDL) and a first coarse RDL. The first coarse RDL includes a first coarse conductive pattern, electrically connected to the first fine conductive pattern, where a, the first coarse RDL includes a first coarse conductive pattern Layout density of the first fine conductive pattern is denser than that of the first coarse conductive pattern. The second portion includes at least one of a second fine RDL and a second coarse RDL. An electronic device including a substrate structure is also provided.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

Abstract: There is provided a laminated body capable of lowering thermal resistance and capable of suppressing peeling off after a cooling/heating cycle. The laminated body according to the present invention includes an insulating resin layer, a first metal material being a metal foil or a metal plate, and a second metal material being a metal foil or a metal plate, the first metal material is layered on a first surface of the insulating resin layer and the second metal material is layered on a second surface opposite to the first surface of the insulating resin layer, the thickness of the insulating resin layer is 200 ?m or less, the total thickness of the first metal material and the second metal material is 200 ?m or more, the ratio of the thickness of the first metal material to the thickness of the second metal material is 0.

Abstract: A method includes bringing into contact respective first sides of a plurality of dies and a die attach film on a major surface of a carrier wafer, and simultaneously heating portions of the die attach film contacting the plurality of dies in order to simultaneously bond the plurality of dies to the die attach film.

Abstract: A display device includes a display substrate with a display area, a first peripheral area, and a second peripheral area, the display area having first and second sides extending in directions crossing each other, the first peripheral area adjacent to the first side, and the second peripheral area adjacent to the second side, a first driving substrate attached to the first peripheral area, the first driving substrate including a first driving circuit portion and a first link wire connected to the first driving circuit portion, a second driving substrate attached to the second peripheral area, the second driving substrate including a second driving circuit portion and a second link wire connected to the second driving circuit portion, and a flexible circuit board attached to the first driving substrate, the flexible circuit board including a third link wire connected to the first and second link wires.

Abstract: Artificial neuron apparatus includes first and second resistive memory cells. The first resistive memory cell is connected in first circuitry having a first input and output. The second resistive memory cell is connected in second circuitry having a second input and output. The first and second circuitry are operable in alternating read and write phases to apply a programming current to their respective memory cells on receipt of excitatory and inhibitory neuron input signals, respectively. During the write phase, resistance of the respective cells is changed in response to successive excitatory and inhibitory neuron input signals. During the read phase, a read current is applied to their respective cells to produce first and second measurement signals, respectively. An output circuit connected to the first and second outputs produces a neuron output signal at a neuron output when a difference between the first and second measurement signals traverses a threshold.

Abstract: A modulator drive circuit, including: a first transistor having: a first output terminal connected to a first reference voltage, a second output terminal connected to a first output terminal of the modulator drive circuit, and a control terminal; and a second transistor having: a first output terminal connected to a second reference voltage different from the first reference voltage, a second output terminal connected to the first output terminal of the modulator drive circuit, and a control terminal.

Abstract: A system includes a heat sink, a semiconductor device, a layer of thermal interface material (TIM) disposed between the heat sink and the semiconductor device, and a fastener system that couples the semiconductor device, the layer of TIM, and the heat sink together. The TIM may facilitate dissipation of heat generated by the semiconductor device via the heat sink during operation of the semiconductor device. The fastener system includes a first Belleville-type washer configured to cooperate with the TIM, which flows when heated beyond a threshold temperature, to maintain a substantially constant coupling force between the semiconductor device and the heat sink during operation of the semiconductor device.

Abstract: According to an aspect of the present inventive concept there is provided a system comprising: a conductive textile including conductive fibers, an electronic circuit unit arranged on a first main surface of the conductive textile and including circuitry and a carrier supporting the circuitry, the carrier having a first main surface and a second main surface facing the first main surface of the textile and including a through-hole extending from the first main surface to the second main surface, a conductive pin including an leg segment arranged at least partly in the through-hole, and a grip segment arranged to grip about at least one fiber of the conductive textile. There is also provided a method for mounting an electronic circuit unit on a conductive textile.

Abstract: In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer.

Abstract: A wiring substrate includes a first wiring structure and a second wiring structure having a higher wiring density. The second wiring structure includes a wiring layer formed on a first insulation layer of the first wiring structure. The wiring layer includes a first wiring pattern, the upper surface of which includes smooth and rough surfaces. A protective film, formed from a conductive material having a higher migration resistance than the wiring layer, covers only the smooth surface and includes a smooth upper surface. A second insulation layer stacked on the first insulation layer covers the wiring layer and the protective film. The smooth surface is continuous with and downwardly recessed from the smooth surface to expose a peripheral portion of the protective film. The second insulation layer covers upper, lower, and side surfaces of the peripheral portion.

Abstract: A method of removing material from a surface, which includes the steps of providing a base layer, at least one layer attached to the base layer, an intermediate finish surface, and a bonding interface surface. The intermediate finish surface is formed by removing the at least one layer and a portion of the base layer during a material removal process. The bonding interface surface is formed by a polishing process applied to the intermediate finish surface. There is an oxidation layer which is part of the base layer, as well as a mold release layer and a contamination layer, both of which are part of the at least one layer. The material removal process involves laser etching the at least one layer to create the intermediate finish surface, and the polishing process includes applying a second laser etching to the intermediate finish surface, forming the bonding interface surface.

Abstract: A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.

Abstract: A power module includes a power semiconductor device, and a chip component arranged on first and second circuit patterns that are electrically connected to the power semiconductor device, and arranged so as to bridge the first and second circuit patterns. The chip component is arranged so that first and second electrodes are respectively positioned on the first and second circuit patterns, and the first and second electrodes and the first and second circuit patterns are respectively joined with solder layers. Between a lower surface of the chip component and the first circuit pattern and between the lower surface of the chip component and the second circuit pattern, two spacers are provided in parallel with each other respectively at positions close to the first and second electrodes. The solder layers do not exist on an inner side of the two spacers in parallel with each other.

Abstract: An embodiment of a power-supply module includes a molded package, power-supply components disposed within the package, and an inductor disposed within the package and over the power-supply components. For example, for a given output-power rating, such a power-supply module may be smaller, more efficient, and more reliable than, and may run cooler than, a power-supply module having the inductor mounted outside of the package or side-by-side with other components. And for a given size, such a module may have a higher output-power rating than a module having the inductor mounted outside of the package or side-by-side with other components.

Abstract: The embodiments relate to a polymerizable thermoset composition having improved flame retardant properties, a polymerized thermoset having improved flame retardant properties, a process for manufacturing the polymerized thermoset, and use of the polymerizable thermoset composition to produce lightweight construction components, preferably carbon fiber composites (CFRP), and a lightweight construction component, preferably carbon fiber composite (CFRP), containing the polymerized thermoset.

Abstract: A display system is disclosed. The display system comprises a light emitting diode (LED) device and a backplane (BP) device. The LED device comprises a plurality of LEDs having LED terminals. An LED bonding surface comprising a dielectric layer with LED bonding surface contact pads is coupled to diode terminals of the LEDs. The backplane (BP) device comprises a BP substrate having top and bottom surfaces. A plurality of system on chip (SoC) chips are bonded to chip pads disposed on a bottom surface of the BP device. The SoC chips are electrically coupled to the CMOS components of the BP device and LEDs of the LED device.

Abstract: An integrated circuit package including a substrate having a cavity and one or more semiconductor devices assembled within the cavity of the substrate. The one or more semiconductor devices electrically coupled using redistribution layers, wherein the cavity is a first cavity, the substrate includes the first cavity and a second cavity, the one or more semiconductor devices are fully embedded within the first cavity of the substrate, the one or more semiconductor devices are fully embedded between the substrate and a first redistribution layer of said redistribution layers, bumps are fully embedded within the second cavity of the substrate, the bumps are fully embedded between the substrate and the first redistribution layer of said redistribution layers, and the first redistribution layer is fully embedded between the substrate and a semiconductor interposer.

Abstract: An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.

Abstract: A prepreg includes a fiber base material and a thermosetting resin composition impregnated into the fiber base material. The thermosetting resin composition contains a thermosetting resin including an epoxy resin; a curing agent; an inorganic filler; and an acrylic acid ester copolymer having a weight average molecular weight of 10×104 or more and less than 45×104. A content of the inorganic filler is 150 parts by mass or more relative to a total of 100 parts by mass of the thermosetting resin and the curing agent. A content of the acrylic acid ester copolymer is more than 30 parts by mass and 90 parts by mass or less relative to the total of 100 parts by mass of the thermosetting resin and the curing agent.

Abstract: A semiconductor package includes: a semiconductor chip including an effective chip region at a center of the semiconductor chip and in which pads connected to chip wirings are formed, and a dummy chip region at a side of the effective chip region and in which pads not connected to the chip wirings are formed; a base film including a chip mounting section on which the semiconductor chip is mounted; and a plurality of wiring patterns disposed on the base film and electrically connected to the chip wirings of the semiconductor chip, wherein first wiring patterns, which are a part of the plurality of wiring patterns, extend on a first region of the chip mounting section corresponding to the dummy chip region.

Abstract: A film material includes a substrate and a film layer arranged on one main surface of the substrate. The film layer contains a fibrous first resin and a thermosetting second resin in an uncured or semi-cured state, and a linear expansion coefficient CF of the first resin is smaller than a linear expansion coefficient CR of the second resin in cured state.

Abstract: A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently patterned to provide selected circuit connections or chemically-mechanically polished to completely remove the metal plating layer. Forming a metal plating layer over the vias may include filling the vias with a sacrificial filler to enable formation of the metal plating layer and subsequently removing the sacrificial filler via an etching operation or the like. In other embodiments, forming the metal plating layer over the vias is accomplished by bonding a metallic layer onto the first side of the substrate.

Abstract: An apparatus that includes a resonant DC-DC converter with switching frequencies based on stray inductances of the physical components used to construct the apparatus. This results in a relatively high efficiency and high density DC-DC converter that, in some implementations, does not require a discrete inductor component.

Abstract: A solar junction box includes a housing having a base and walls defining a cavity. The base has an opening configured to receive a conductive foil. A power cable is held in the housing having a power terminal terminated to an end of the power cable positioned within the housing. An electronic module is removably received in the cavity. The electronic module has a circuit board including electronic components mounted to the circuit board, a foil contact configured to be removably coupled to the foil, and a power contact configured to be removably coupled to the power terminal. The circuit board has a power circuit electrically connecting the foil contact and the power contact.

Abstract: A semiconductor device includes a two-input NOR circuit including four MOS transistors arranged in a line. Each of the MOS transistors is disposed on a planar silicon layer disposed on a substrate. The drain, gate, and source of the MOS transistor are arranged in the vertical direction. The gate surrounds a silicon pillar. The planar silicon layer is constituted by a first activation region of a first conductivity type and a second activation region of a second conductivity type. The first and second activation regions are connected to each other via a silicon layer disposed on a surface of the planar silicon layer, so as to form a NOR circuit having a small area.

Abstract: An information handling system is set forth which includes a fully connected 4S topology that can also be populated with two processors and two link modules (e.g., two passive “slugs”) to implement a fully connected 2S topology. More specifically, the link module is a printed circuit board that implements a loopback connection between certain links of the architecture. In certain embodiment, the link module includes no electrical components. The link module merely includes a set of electrical connections (e.g., copper traces) connecting pads (e.g., gold plated pads) on a thick printed circuit board (PCB) dielectric material that is shaped to fit the processor socket. The link module is used to carry user data when the information handling system is configured in a 2S topology. The link module includes proper lane assignment that allows the module to be passive without performance reduction.

Abstract: Wafer level packaged semiconductor device with enhanced heat dissipation properties. The semiconductor device includes a top and a bottom face and at least one metal pad is positioned on the top and the bottom faces. A top cover is affixed to the top face of the semiconductor device and a bottom cover is affixed to the bottom face of the semiconductor device. Vias extend through the top and bottom covers and an electroplated metal layer extends from an external face of the covers, through the visas to the metal pads on the semiconductor device.

Abstract: The width of scribe lines may be reduced in semiconductor devices by applying a process technique in which trenches may be formed first from the rear side on the basis of a required width of the corresponding trenches, while subsequently it may be cut into the substrate from the front side on the basis of a reduced thickness of the corresponding saw blades, thereby also enabling a reduction of the scribe line width. Furthermore, contamination of the front side, i.e., of the metallization system, may be reduced, for instance, by performing an optional intermediate cleaning process.

Abstract: The invention relates to a circuit module (10) having a circuit carrier (12), at least one circuit (14) mounted on the circuit carrier (12), encapsulated by a protective material (16), and at least one electrical/electronic component (18) encapsulated by a protective coating (20), protecting the at least one electrical/electronic component (18) from the protective material (16), and to a method for producing the circuit module (10). According to the invention, the protective coating (20) protecting the at least one electrical/electronic component (18) is only partially encapsulated by the protective material (16).

Abstract: There is provided a semiconductor device. The semiconductor device of the present invention includes a semiconductor element and a metal buffer layer in an electrical connection to the semiconductor element. The metal buffer layer and the semiconductor element are in a connection with each other by mutual surface contact of the metal buffer layer and the semiconductor element. The metal buffer layer is an external connection terminal used for a mounting with respect to a secondary mount substrate, and the metal buffer layer serves as a buffer part having a stress-relaxation effect between the semiconductor element and the secondary mount substrate.

Abstract: A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently patterned to provide selected circuit connections or chemically-mechanically polished to completely remove the metal plating layer. Forming a metal plating layer over the vias may include filling the vias with a sacrificial filler to enable formation of the metal plating layer and subsequently removing the sacrificial filler via an etching operation or the like. In other embodiments, forming the metal plating layer over the vias is accomplished by bonding a metallic layer onto the first side of the substrate.

Abstract: A GOA layout method, an array substrate and a display device are provided. The array substrate includes a plurality of GOA unit groups, each of which includes two adjacent GOA units. The plurality of GOA unit groups includes a first GOA unit group, two GOA units of the first GOA unit group have an overlapping region with at least one via hole provided therein, and the two GOA units of the first GOA unit group are electrically connected through the at least one via hole. With the array substrate, the density of gate lines can be increased.

Abstract: An integrated circuit includes a die having a conductive layer. The conductive layer includes a data wire, a first power supply wire of a first voltage potential, and a second power supply wire of a second voltage potential different from the first voltage potential. A segment of the data wire is located between, and substantially parallel to, a segment of the first power supply wire and a segment of the second power supply wire. Further, the first power supply wire is coupled to a first probe structure; and, the second power supply wire is coupled to a second probe structure.

Abstract: Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate. A first conductive layer having a plurality of openings is disposed over the first surface of the base substrate and via contacts. The openings are configured to match conductive trace layout of the package substrate. Conductive traces are disposed over the first conductive layer. The conductive traces are directly coupled to the via contacts through some of the openings of the first conductive layer.

Abstract: A method for manufacturing a semiconductor device, includes preparing a solder, a soldering article, a base material, a weight having a foot where a center of gravity of the weight is shifted from a center of the soldering article, a positioning jig having a hole for holding the soldering article in the base material, and a dam member; disposing the dam member on a side having a relatively lower height due to a warp of an edge portion of the base material; placing the positioning jig on a principal surface of the base material; placing the soldering article on the solder in the hole; placing the weight on an upper surface of the soldering article to position the center of gravity on the side having relatively lower height; and raising the temperature of the solder to a temperature equal to or higher than the melting point of the solder.

Abstract: An electrical connector assembly essentially consists of four connector units neighboring with one another each occupying a quadrant in a square manner so that each connector units defines two unexposed neighboring sides and two exposed outer sides. Each connector unit includes an insulative housing with a plurality of passageways to receive the corresponding contacts therein. A vertically and horizontally staggered structure is formed on each neighboring side of the housing. A pair of inner interengaging structures and a pair of outer neighboring structures are respectively formed on two opposite ends of the corresponding neighboring sides of the neighboring connector units so as to allow the neighboring connector units to be assembled in a pivotal way with the pair of outer interengaging structures as a fulcrum.

Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate.

Abstract: A waterproof electronic device with a soft polymer embedding enclosure configured to seal components embedded in the soft polymer embedding enclosure from water by direct contact of the soft polymer embedding enclosure with the components, and including an embedded microswitch operated by pressing on an outer surface of the soft polymer embedding enclosure. The apparatus may be built using various degrees of integration of its components.

Abstract: A method for manufacturing vias in a glass substrate includes bonding, through a bonding layer, a first face of the glass substrate including a plurality of holes to a first face of a glass carrier. The bonding layer has a thickness t between the first face of the glass substrate and the first face of the glass carrier and extends into at least some of the plurality of holes to a depth h from the first face of the glass substrate. The method includes etching back the bonding layer to a depth d through the plurality of holes in the glass substrate. The depth d is less than the sum of the thickness t and the depth h. The method can include filling the plurality of holes with an electrically conductive material, and de-bonding the glass substrate from the bonding layer and the glass carrier.

Abstract: A microelectronic structure includes a first row of contacts (14) and a second row of contacts (24) offset from the first row, so that the first and second rows cooperatively define pairs of contacts. These pairs of contacts include first pairs (30a) and second pairs (30b) arranged in alternating sequence in the row direction. The first pairs are provided with low connectors (32a), whereas the second pairs are provided with high connectors (32b). The high connectors and low connectors have sections vertically offset from one another to reduce mutual impedance between adjacent connectors.

Abstract: An electronic component including a wiring board having interlayer insulation layers and conductive patterns, the wiring board having a first surface and a second surface on the opposite side of the first surface, multiple first bumps formed on a first conductive pattern positioned on the first surface of the wiring board among the conductive patterns of the wiring board, a semiconductor element mounted on the first surface of the wiring board through the first bumps, an encapsulating resin encapsulating the semiconductor element and at least a portion of a side surface of the wiring board, the side surface of the wiring board extending between the first surface and second surface of the wiring board, and multiple of second bumps formed on the second surface of the wiring board and connected to a second conductive pattern of the conductive patterns in the wiring board.

Abstract: An electronic device includes a base body, which has a top side and also an underside lying opposite the top side. The base body has connection locations at its underside. An electronic component is arranged at the base body at the top side of the base body. The base body has at least one side area having at least one point of inspection having a first region and second region. The second region is embodied as an indentation in the first region. The first and the second region contain different materials.