Abstract: A silicon MEMS device can have at least one solder contact formed thereupon. The silicon MEMS device can be configured to be mounted to a circuit board via the solder contact(s). The silicon MEMS device can be configured to be electrically connected to the circuit board via the solder contact(s).

Abstract: Board assemblies with minimized warpage and systems and methods for making the same are disclosed. A board may be pre-conditioned by designing the board to mount components in selected areas of the board and by selectively copper flooding certain regions of the board. Pre-conditioning of the board may assist in preventing board warpage. A reflow fixture may fix a board during solder pasting and reflow processing thereof. After reflow, an underfill fixture may fix the board during underfill processing. Each of these fixtures may include respective clamp members that may hold various portions of the board to correct and/or prevent warpage of the board.

Abstract: An interposer is shown with contact points on a lateral edge. When assembled between a board under test and an integrated circuit, traces of the interposer carry signals between the board under test and the integrated circuit and also between signal lines of the integrated circuit and the lateral edge contact points. The signals can then be accessed by test equipment at the lateral edge contact points. The interposer may include additional components connected to the traces.

Abstract: In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.

Abstract: In a case where a first mounted substrate to which a semiconductor element is bounded by solder is mounted on a second substrate, connection strength becomes low, when the first mounted substrate is bonded to the second substrate by using a solder having a low melting point. A mounted structure, in which a first mounted substrate on which a semiconductor element is bonded by using a first solder having a melting point of 217° C. or more, is mounted on a second substrate, includes plural bonding parts bonding the first mounted substrate to the second substrate; and a reinforcing member formed around the bonding part. Each of the bonding parts contains a second solder having a melting point, that is lower than the melting point of the first solder, and a space exists, in which the reinforcing members do not exist, between the bonding parts neighboring each other.

Abstract: In a high-frequency switch module, a switch IC is mounted on a multilayer board to define a high-frequency switch module. The multilayer board includes two internal wirings and two internal ground electrodes. The internal ground electrodes are spaced apart from each other at an interval when viewed from a lamination direction of the multilayer board. The first internal wiring is located on the upper surface side of the first internal ground electrode, and is entirely separated from an RF wiring, and the first internal wiring includes a power supply wiring for supplying power to the switch IC. The second internal wiring is located on the upper surface side of the second internal ground electrode, and is entirely separated from the power supply wiring, and the second internal wiring includes a signal wiring through which an RF signal propagates.

Abstract: A ceramic multilayer substrate includes stacked ceramic layers; internal conductors which are stacked with one of the ceramic layers therebetween, and are arranged such that at least a portion of the internal conductors overlap each other in a stacking direction; and a constraining layer which is arranged on a layer different from layers on which the internal conductors are located. The constraining layer overlaps, in the stacking direction, an internal conductor-overlapping region where at least two of the internal conductors overlapping each other in the stacking direction, has a planar area not more than twice the planar area of the internal conductor-overlapping region, and contains an unsintered inorganic material powder. The constraining layer has a planar area not more than one-half the planar area of the ceramic layers. The constraining layer is arranged so as to entirely cover the internal conductor-overlapping region.

Abstract: A circuit board according to an embodiment is one in which a plurality of electronic components is mounted on a printed wiring board. The circuit board includes a semiconductor component that is mounted on the printed wiring board, and the semiconductor component includes a semiconductor device and a first EBG structure formed on or above the semiconductor device. An operating frequency of the semiconductor device exists outside a cutoff band of the first EBG structure, and the first EBG structure is connected to a ground or a power supply of the printed wiring board.

Abstract: A method for producing an arrangement of optoelectronic components (10) is specified, comprising the following steps: producing at least two fixing regions (2) on a first connection carrier (1); introducing solder material (3) into the fixing regions (2); applying a second connection carrier (4) to the fixing regions (2); and soldering the second connection carrier (4) onto the first connection carrier (1) with the solder material (3) in the fixing regions (2).

Abstract: An electric circuit apparatus includes: a first-circuit board that includes a first-through-hole, and a first-electrode disposed on a front side of the first-circuit-board; a second-circuit-board that is disposed on a back side of the first-circuit-board, the second-circuit-board including on the front side of the second-circuit-board a second-electrode associated with the first-through-hole; a semiconductor device that is disposed on the front side of the first-circuit-board, the semiconductor device including on a back side a third-electrode-associated with the first-electrode, and a fourth-electrode-associated with the second-electrode; a first-bonding-material that bonds the first-electrode and the-third-electrode; a second-bonding-material that bonds the second-electrode and the fourth-electrode while passing through the first-through-hole; and a support body that is disposed between the first-electrode and the second-circuit-board and that supports the first-circuit-board.

Abstract: A network communication device is disclosed. The network communication device includes a circuit board, a network connector, a network chip and a plurality of network magnetic assemblies. The network connector, the network chip and the network magnetic assemblies are disposed on the circuit board. The network magnetic assemblies are electrically connected with the network connector and the network chip, respectively. Each of the network magnetic assemblies includes an Ethernet transformer and at least one inductor. The Ethernet transformer is electrically connected in series with the inductor via a conductive trace of the circuit board. The spaced distance or a path length of the conductive trace between the Ethernet transformer and the inductor of the at least one network magnetic assembly is less than a first specific length.

Abstract: An electronic component includes a frame-shaped supporting body including a heat-curable resin and surrounding a functional unit on one main surface of a substrate and so as to be separated from a periphery of the substrate on an inner side and in which a lid member is fixed to the supporting body such that an opening of the frame-shaped supporting body is sealed. The frame-shaped supporting body includes a frame-shaped supporting body main body, a first protrusion that protrudes toward an inside from the supporting body main body and a second protrusion that protrudes toward an outside from the supporting body main body at a portion where the supporting body main body and the first protrusion are continuous with each other.

Abstract: A wiring board includes a plurality of wiring layers, a plurality of insulating layers, and an electrode member made of a conductive material, the electrode member being incorporated in the wiring board in a state in which the electrode member includes exposed sections on side surfaces that cross the plurality of wiring layers and the plurality of insulating layers.

Abstract: Disclosed herein is a power module package including an external connection terminal; a substrate in which a fastening unit allowing one end of the external connection terminal to be insertedly fastened thereinto is buried at a predetermined depth in a thickness direction; and a semiconductor chip mounted on one surface of the substrate.

Abstract: An interposer (support substrate) for an opto-electronic assembly is formed to include a thermally-isolated region where temperature-sensitive devices (such as, for example, laser diodes) may be positioned and operate independent of temperature fluctuations in other areas of the assembly. The thermal isolation is achieved by forming a boundary of dielectric material through the thickness of the interposer, the periphery of the dielectric defining the boundary between the thermally isolated region and the remainder of the assembly. A thermo-electric cooler can be used in conjunction with the temperature-sensitive device(s) to stabilize the operation of these devices.

Abstract: On a surface layer of a printed wiring board, main power supply patterns to be applied with different DC voltages are disposed in a second region. Power supply patterns are disposed on the surface layer, and the power supply patterns are led from the main power supply patterns to a first region. The power supply patterns connect power supply terminals of terminal groups in the second region. The power supply patterns connect the power supply terminals between the terminal groups in the first region. Power supply terminals of the terminal groups of a semiconductor package are electrically connected to the main power supply patterns by the power supply patterns. Thus, potential fluctuations are reduced and radiation noise is suppressed, and the number of layers of the printed wiring board is reduced.

Abstract: Embodiments pin connections, electronic devices, and methods are shown that include pin configurations to reduce voids and pin tilting and other concerns during pin attach operations, such as attachment to a chip package pin grid array. Pin head are shown that include features such as convex surfaces, a number of legs, and channels in pin head surfaces.

Abstract: A wiring substrate (11) includes: a substrate; and, formed upon the substrate, a plurality of wiring lines, a plurality of circuit elements, and a plurality of connecting terminals (51) connected via the plurality of wiring lines. Each of the plurality of connecting terminals (51) includes a pair of protrusion parts (50), forming a depression part (60) between the pair of protrusion parts (50), and a depression electrode (52) that is disposed in the depression part (60) and that at least partially covers each protrusion of the pair of protrusion parts (50).

Abstract: A semiconductor device includes a package board having a front side and a back side opposite to each other. A first memory device has data pins and is mounted on the front side of the package board, and a second memory device has data pins and is mounted on the back side of the package board. The data pins of the first and second memory devices have a same arrangement. A controller provides data signals to the first and second memory devices, with the same data signal provided from the controller to one data pin of the first memory device and one data pin of the second memory device.

Abstract: An electronic device comprises: a printed wiring board that comprises a substrate, pads formed on the substrate, and an insulating film layer covering a surface of the substrate on which the pads are formed; and an electronic element that comprises external terminals electrically connected to the pads and that is mounted on the printed wiring board. The insulating film layer comprises at least one connecting opening section each exposing at least part of one of the pads. At least part of an inner wall of the connecting opening section comprises at least one step section.

Abstract: A wafer-scale assembly circuit including a plurality of metal interconnect layers, where each metal layer includes patterned metal portions and where at least some of the patterned metal portions are RF signal lines. The circuit further includes at least one benzocyclobutene layer provided between two metal interconnect layers that includes at least one trench via formed around a perimeter of the benzocyclobutene layer at a circuit sealing ring, where the trench via provides a hermetic seal at the sealing ring. The benzocyclobutene layer also includes a plurality of stabilizing post vias formed through the benzocyclobutene layer adjacent to the trench via proximate to the sealing ring and extending around the perimeter of the benzocyclobutene layer, where the stabilizing vias operate to prevent the benzocyclobutene layer from shrinking in size.

Abstract: Provided is a memory module, a system using the memory module, and a method of fabricating the memory module. The memory module may include a printed circuit board and a memory package on the printed circuit board. The printed circuit board may include an embedded optical waveguide and a first optical window extending from the optical waveguide to a first surface of the printed circuit board. The memory package may also include a memory die having an optical input/output section and a second optical window. The optical input/output section, the second optical window, and the first optical window may be arranged in a line and the first optical window and the second optical window may be configured to at least one of transmit an optical signal from the optical waveguide to the optical input/output section and transmit an optical signal from the optical input/output section to the optical waveguide.

Abstract: The present invention addresses the problem of providing a power device comprising a terminal-holding member excellent in insulating properties. The present invention relates to a power device having a power element, a terminal, and a terminal-holding member composed of a liquid crystalline polyester, wherein the liquid crystalline polyester is a liquid crystalline polyester having a repeating unit (1) derived from an aromatic hydroxycarboxylic acid, a repeating unit (2) derived from an aromatic dicarboxylic acid, and a repeating unit (3) derived from an aromatic diol, and the content of a repeating unit derived from isophthalic acid in the liquid crystalline polyester is 0 to 7 mol % relative to the total amount of all repeating units of the liquid crystalline polyester.

Abstract: There is provided an interconnection structure. An interconnection structure according to an aspect of the invention may include: a plurality of side portions provided on one surface of a substrate part and a plurality of cavities located between the side portions and located further inward than the side portions; and electrode pattern portions provided on surfaces of the side portions and the cavities.

Abstract: A high-frequency device includes a wireless IC chip and a board which is coupled to the wireless IC chip and electrically connected to radiator plates, and an inductor and/or a capacitance are provided as a static electricity countermeasure element in the board. The inductor is connected in parallel between the wireless IC chip and the radiator plates, and its impedance at the frequency of static electricity is less than an impedance of the wireless IC chip.

Abstract: A COF includes, in at least one embodiment, a heat dissipating material on a back surface of an insulating film. The heat dissipating material has a slit for reducing a degree of thermal expansion. Thus, at least one embodiment of the invention provides the COF in which deformation and disconnection of wiring are prevented.

Abstract: A display apparatus and a driving chip mounting film in the display apparatus, capable of simplifying a manufacturing process and reducing a process time. The display apparatus includes an insulating substrate; a display device formed on the insulating substrate and for defining an image display unit; pads formed on the insulating substrate and electrically connected to the display device; a first circuit substrate disposed at and separate from a first side of the insulating substrate; and a number of driving chip mounting films including one-side ends electrically connected to the first circuit substrate, and other-side ends electrically connected to the pads. A number of driving chips are mounted on each of the number of driving chip mounting films.

Abstract: A package is connected at a first side to a printed circuit board and with a die fixed to it on a second side opposite to the first side. The package has an integrated pre-match circuit to provide an impedance match for a signal to be sent to a circuit external to the package. The signal has a predetermined main frequency component. The pre-match circuit has a pair of transmission lines and a pair of stubs on a predetermined layer of the package and connected to the pair of transmission lines. The pair of stubs have a length such as to form a short circuit for an harmonic frequency of the main frequency component in the signal.

Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.

Abstract: A composite wafer includes a molded wafer and a second wafer. The molded wafer includes a plurality of first components, and the second wafer includes a plurality of second components. The second wafer is combined with the molded wafer to form the composite wafer. At least one of the first components is aligned with at least one of the second components to form a multi-component element. The multi-component element is singulatable from the composite wafer.

Abstract: A hermetically sealed microelectromechanical system (MEMS) package for an implantable medical device is presented. The MEMS comprises a first substrate that includes an aperture. A feedthrough assembly is coupled to the aperture, the feedthrough assembly comprises a conductive element housed in a glass insulator member. A second substrate is coupled to the first substrate.

Abstract: Disclosed is a metal nanoparticle paste that uses the low-temperature sintering characteristics of metal nanoparticles to easily obtain a metal bond with excellent conductivity and mechanical strength, and which can form a wiring pattern with excellent conductivity. The metal nanoparticle paste is characterized by containing (A) metal nanoparticles, (B) a protective film that coats the surface of the metal nanoparticles, (C) a carboxylic acid, and (D) a dispersion medium.

Abstract: An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.

Abstract: The present disclosure provides a wiring board including a thin film member configured to include an inorganic dielectric film formed over an overall area of a mounting face thereof for an electronic part, a first conductive film formed over an overall area of one of faces of the inorganic dielectric film and including a plurality of patch electrode portions disposed in a predetermined pattern corresponding to a predetermined electromagnetic band gap structure in at least part of the area, and a second conductive film formed over an overall area of the other face of the inorganic dielectric film.

Abstract: A circuit board includes a plurality of conductive layers, at least one group of vias, a number of second vias, at least one power supply element, and at least one electronic element. Each conductive layer includes a conductive portion. Both the first vias and the second vias are defined through the conductive layers and electrically connected each conductive layers. The at least one group of first vias surrounds the at least one power supply element. The second vias are arranged along the side of the conductive portion, and positioned between the power supply element and the electronic element. Current from a power supply element flows to the inner conductive layers through the group of surrounding first vias. Current transmission on each conductive layer continuously flows to another conductive layer having a lower resistance through the second vias during transmission.

Abstract: A power module includes a power module body portion and a wiring board. The power module body portion includes P-side semiconductor elements and N-side semiconductor elements, and a P-side terminal connection portion, a U-phase terminal connection portion, and an N-side terminal connection portion which establish electrical connection with the wiring board on an upper surface of the power module body portion and into which a current flows from the wiring board and from which a current flows to the wiring board.

Abstract: An electronic device comprising a laminate comprising pluralities of insulator layers each provided with conductor patterns, and an amplifier-constituting semiconductor device mounted to a mounting electrode formed on an upper surface of the laminate, a first ground electrode being formed on an insulator layer near an upper surface of the laminate; a second ground electrode being formed on an insulator layer near a lower surface of the laminate; the first ground electrode being connected to the mounting electrode through pluralities of via-holes; conductor patterns constituting the first circuit block being disposed in a region below the amplifier-constituting semiconductor device between the first ground electrode and the second ground electrode; and at least part of a conductor pattern for a line connecting the first circuit block to the amplifier-constituting semiconductor device being disposed on an insulator layer sandwiched by the mounting electrode and the first ground electrode.

Abstract: Aspects of the invention are directed to a power module including a metal base, an insulating substrate which is attached to the metal base, a semiconductor chip and a control terminal which are attached to a circuit pattern of the insulating substrate, and a resin case which is attached to the metal base. The control terminal can include a penetration portion which penetrates a cover of the resin case, an L-shaped processed portion which is connected to the penetration portion, and a connection portion which is connected to the L-shaped processed portion. A protrusion portion can be installed in a portion of the control terminal, which penetrates the cover. The protrusion portion can be in contact with a protrusion receiving portion which is configured with a front surface of the cover. The L-shaped processed portion can be in contact with a convex portion in a rear surface of the cover.

Abstract: The present invention provides: an insulating substrate or metal-clad laminate able to sufficiently reduce or prevent negative warping of a semiconductor device; a printed wiring board that uses the insulating substrate or metal-clad laminate; and a semiconductor device. The insulating substrate is composed of a cured product of a laminate including one or more fibrous base material layers and two or more resin layers, in which the outermost layers on both sides is the resin layers. At least one of the fibrous base material layers is shifted towards the first side or a second side on the opposite side thereof with respect to the reference position, namely the dividing position at which a total thickness of the insulating substrate is equally divided by the number of the fibrous base material layers and each divided region having the thickness is further equally divided by two. The fibrous base material layers are not shifted in different directions.

Abstract: In accordance with an embodiment of the present invention, a device includes a circuit board with a thermally conductive core layer and a chip disposed over the circuit board. The device further includes a heat sink disposed over the chip. The thermal conductivity of the heat sink along a first direction is larger than a thermal conductivity along a second direction. The first direction is perpendicular to the second direction. The heat sink is thermally coupled to the thermally conductive core layer.

Abstract: In some examples, an integrated circuit system includes a plurality of integrated circuit layers. At least one of the integrated circuit layers includes an integrated circuit die, which may not include any through-silicon vias that provide a pathway to an adjacent integrated circuit layer, and an interposer portion, which includes electrically conductive through-vias. The interposer portion may facilitate communication of the integrated circuit die with other integrated circuit layers of the integrated circuit system. In some examples, the stacked integrated circuit system may include more than one integrated circuit die, which may be in the same integrated circuit layer as at least one other integrated circuit die, or may be in a different integrated circuit layer.

Abstract: In a multilayer wiring board 100 having a high-density wiring region and a high-frequency propagation region mounted in the same board, it is possible to propagate a signal frequency of 40 GHz or more in the high-frequency propagation region by using a resin material with a dissipation factor (tan ?) of less than 0.01 as a material of an insulating layer used at least in the high-frequency propagation region. The insulating layer is formed of a polymerizable composition which contains a cycloolefin monomer, a polymerization catalyst, a cross-linking agent, a bifunctional compound having two vinylidene groups, and a trifunctional compound having three vinylidene groups and in which the content ratio of the bifunctional compound and the trifunctional compound is 0.5 to 1.5 in terms of a weight ratio value (bifunctional compound/trifunctional compound).

Abstract: The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed.

Abstract: A chip arrangement is provided: the chip arrangement including: a carrier; a chip disposed over the carrier; a ceramic layer formed over the chip and on at least a portion of the carrier; wherein the chip is surrounded by the carrier and the ceramic layer.

Abstract: A semiconductor device includes a semiconductor mounting substrate, a mother case having an opening and housing the semiconductor mounting substrate, a plurality of securing members provided along a rim of the mother case, a screw terminal, and a lid member. The screw terminal has a flat plate portion, an insertion portion extending from the flat plate portion, and a terminal bottom portion, is secured to the securing members by insertion of the insertion portion between adjacent securing members, and is electrically connected to the semiconductor mounting substrate on the terminal bottom portion side. The lid member closes the opening with the screw terminal secured to the securing members. The screw terminal is bent such that the flat plate portion faces an upper surface of the lid member closing the opening. The semiconductor device that can achieve reduction in size of the entire device is obtained.

Abstract: The invention provides an anti-UV electronic device and fabrication method thereof. The anti-ultraviolet (anti-UV) electronic device includes an integrated circuit die, wherein the integrated circuit die has an ultraviolet (UV) light erasable memory; and an anti-UV light layer is formed on and covers the ultraviolet (UV) light erasable memory.

Abstract: A semiconductor structure includes a plurality of solder structures between a first substrate and a second substrate. A first encapsulation material is substantially around a first one of the solder structures and a second encapsulation material is substantially around a second one of the solder structures. The first one and the second one of the solder structures are near to each other and a gap is between the first encapsulation material and the second encapsulation material.

Abstract: According to one embodiment, a power module includes a metal base, a ceramic substrate, a semiconductor chip, a nut holder housing a nut, an electrode terminal and a casing. The ceramic substrate is connected to an upper surface of the metal base via a lower electrode. The semiconductor chip is located on a first major surface of the ceramic substrate. The electrode terminal includes a bent portion surrounding a nut holder. The electrode terminal includes a first connecting portion extending perpendicularly to the bent portion from one end of the bent portion, and being located on the first major surface via an upper electrode, and electrically connected to the semiconductor chip. A casing is bonded to the metal base to enclose the semiconductor chip and the electrode terminal. An upper end portion of the bent portion of the electrode terminal is exposed to outside of the casing through the opening.

Abstract: Provided is a multilayer wiring board including a plurality of signal layers and ground layers. The multilayer wiring board includes: a first differential wiring wired to a third signal layer; and a second differential wiring wired to a ninth signal layer disposed above the third signal layer. The multilayer wiring board includes a first differential signal via and a second differential signal via that are connected to the first differential wiring. The multilayer wiring board includes a third differential signal via which is connected to the second differential wiring and a stub of which is terminated above the third signal layer. The multilayer wiring board includes a fourth differential signal via which is connected to the second differential wiring and a stub of which is terminated above the third signal layer, the first differential wiring wired to pass between the fourth differential signal via and the third differential signal via.

Abstract: A multilayered wiring substrate that includes at least one signal layer and at least one ground layer is provided. The multilayered wiring substrate includes a first signal via that extends in a direction substantially perpendicular to the layers of the multilayered wiring substrate, is conductively connected to one of a pair of differential signaling wires provided in the signal layer, and is formed on a first grid point; and a second signal via that extends in a direction substantially perpendicular to the layers of the multilayered wiring substrate, is conductively connected to the other of the pair of differential signaling wires, and is formed on a second grid point that is positioned diagonally adjacent with respect to the first signal via.