Abstract: Embodiments of provide an integrated circuit (IC) device. The IC device can include a substrate having first and second opposing surfaces, an IC die electrically coupled to the first surface of the substrate, a plurality of contact members coupled to the first surface of the substrate, and an interposer. The interposer can include a plurality of contact elements located on a first surface thereof, each conductive element being coupled to a respective one of the plurality of contact members, and an antenna formed using a conductive layer of the interposer, the antenna being electrically coupled to the IC die through at least one of the plurality of contact elements and at least one of the plurality of contact members.

Abstract: A circuit package includes: electronic circuitry, electrically conductive material forming multiple leads, and multiple connections between the electronic circuitry and the multiple leads. A portion of the electrically conductive material associated with the multiple leads (e.g., low impedance leads supporting high current throughput) is removed to accommodate placement of the electronic circuitry. Each of the multiple leads can support high current. The multiple connections between the, the multiple leads provide connectivity between circuit nodes on the electronic circuitry and pads disposed on a planar surface of the electronic circuit package.

Abstract: A multichip module comprising: a base substrate; a wiring board disposed on the base substrate and having a wiring pattern; an adhesive layer configured to bond the base substrate to the wiring board while maintaining an electrical connection between the base substrate and the wiring board; and a plurality of chips connected to a surface of the wiring board, the surface being opposite the adhesive layer, wherein, assuming that ? is a coefficient of thermal expansion of the wiring board, ? is a coefficient of thermal expansion of the base substrate, and ? is a coefficient of thermal expansion of the adhesive layer, the relationship ?<?<? is satisfied.

Abstract: A method of manufacturing a connection structure which includes a wiring substrate, a first electronic component that is flip-chip mounted on the front surface thereof, and a second electronic component that is flip-chip mounted on the rear surface. The method includes the steps of: temporarily mounting the first electronic component on the front surface of the wiring substrate with a first adhesive film disposed therebetween; temporarily mounting the second electronic component on the rear surface of the wiring substrate with a second adhesive film disposed therebetween, placing, on a pressure bonding receiving base, the wiring substrate on which the first electronic component and the second electronic component are temporarily mounted; and mounting the first electronic component and the second electronic component at a time onto the respective front and rear surfaces of the wiring substrate.

Abstract: A prepreg that yields a semiconductor device which, even when using Cu wire, exhibits excellent reliability under conditions of high temperature and high humidity (heat-resistant and moisture-resistant reliability), a metal-clad laminate and a printed wiring board that use the prepreg, and a semiconductor device that uses the printed wiring board. Specifically disclosed are a prepreg comprising a substrate and a B-staged resin composition comprising (a) a thermosetting resin, (b) a hydrotalcite compound having a specific composition, (c) zinc molybdate, and (d) lanthanum oxide.

Abstract: An electronic module with excellent electrical characteristics includes an electronic component, a mount board, signal electrodes, a ground electrode, and an insulating layer. The electronic component is mounted on a first main surface of the mount board. The signal electrodes and the ground electrode are located on a second main surface of the mount board. The insulating layer is arranged so as to cover a portion of the second main surface of the mount board. The insulating layer is arranged so as not to cover end portions of the signal electrodes that face the ground electrode.

Abstract: A tire inside information acquiring device (100) attached inside a tire-wheel assembly, includes a housing body (10) configured to house a receiving antenna for receiving a radio signal and an electronic circuit unit connected to the receiving antenna, the electronic circuit unit constitutes the tire inside information acquiring device (100), and a substrate (40) on which the housing body (10) and a component constituting the tire inside information acquiring device (100) are disposed. The housing body (10) is formed of a nonmetallic inorganic material. The component is only formed of parts having water resistance.

Abstract: Consistent with an example embodiment, a semiconductor device comprises a patterned conductive layer defining contact pads for being connected to terminals of a semiconductor chip. The semiconductor chip comprises the terminals at a first side and an adhesive layer at a second side opposite to the first side; wherein, the semiconductor chip is mounted with an adhesive layer on a patterned conductive layer such that the semiconductor chip part of each respective contact pad leaves part thereof uncovered by the chip for wire bonding. Wire bonds connect respective terminals of the semiconductor chip and respective contact pads at the first side thereof. A molding compound covers the semiconductor chip, the wire bonds and the contact pads; wherein, the molding compound is also located on the second side of the semiconductor device, separating the contact regions that are located directly on a backside of the contact pads.

Abstract: A wireless apparatus has a board, a power amplifier high-frequency IC chip, and a process variations detector. The process variations detector monitors a circuit characteristic variation amount due to process variations. An underfill having a parameter value calculated using the monitored circuit characteristic variation amount is applied between the board and the high-frequency IC chip and the mounting board. As a result, the wireless apparatus exhibits a desired circuit characteristic even with process variations and influence of the underfill.

Abstract: A circuit assembly includes a substrate having a substrate electrical circuit, opposite top and bottom substrate surfaces, and a substrate hole extending through the substrate. The circuit assembly also includes a discrete component assembly electrically connected to the substrate electrical circuit and a support member attached to the discrete component. At least a portion of the discrete component is physically mounted in the substrate hole.

Abstract: Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by opening switches on the first die, converting the TSVs previously connected through the open switches into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by opening switches on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

Abstract: The invention discloses a COF packaging unit and a COF packaging tape. The COF packaging unit comprises COF baseband(s), IC Die(s) packaged on the COF baseband(s), and input end wires and output end wires connected with the IC Die(s); the input end wires and the output end wires are respectively provided with input terminals and output terminals at two edges of the COF baseband. In the invention, because the input terminals and the output terminals are pitched along the edges of the COF baseband, the length of the single COF packaging unit is set in accordance with the pitching requirement of the input end wires and the output end wires, so that the COF baseband can have sufficient area for wiring, to adapt to the requirement of large LCD panels. Thus, resources are reasonably integrated and used, equipment utilization rate is increased, material purchasing cost is saved, and economic benefits are increased.

Abstract: An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”).

Abstract: A siloxane compound containing structures represented by the following general formulae (1) and (2): wherein R1 and R2 independently represent a hydrogen atom, a halogen atom, an alkyl group having from 1 to 3 carbon atoms, a halogenated alkyl group, a thiol group, an acetyl group, a hydroxyl group, a sulfonic acid group, a sulfoalkoxyl group having from 1 to 3 carbon atoms, or an alkoxyl group having from 1 to 3 carbon atoms; x and y independently represent an integer of from 0 to 4; and A represents a single bond or an azomethine group, an ester group, an amide group, an azoxy group, an azo group, an ethylene group, or an acetylene group, and wherein R3 and R4 independently represent an alkyl group, a phenyl group, or a substituted phenyl group; and n represents an integer of from 1 to 100.

Abstract: A system, a packaged component and a method for making a packaged component are disclosed. In an embodiment a system comprises a component carrier, a component disposed on the component carrier and an insulating layer disposed on an electrically conductive surface of at least one of the component carrier or the component, wherein the insulating layer comprises a polymer and an inorganic material comprising a dielectric strength of equal or greater than 15 ac-kv/mm and a thermal conductivity of equal or greater than 15 W/m*K.

Abstract: A device includes an interposer and a radio-frequency (RF) device bonded to a first side of the interposer. The interposer includes a first side and a second side opposite to the first side. The interposer does not have through-interposer vias formed therein. First passive devices are formed on the first side of the interposer and electrically coupled to the RF device. Second passive devices are formed on the second side of the interposer. The first and the second passive devices are configured to transmit signals wirelessly between the first passive devices and the second passive devices.

Abstract: A wiring board has a first resin insulation layer, a first conductive pattern formed on the first resin insulation layer, a second resin insulation layer formed on the first conductive pattern and having an opening portion exposing at least a portion of the first conductive pattern, a second conductive pattern formed on the second resin insulation layer, and a via conductor formed in the opening portion of the second resin insulation layer and electrically connecting the first conductive pattern and the second conductive pattern. The via conductor has a side surface extending between the first conductive pattern and the second conductive pattern and a bent portion where an inclination of the side surface of the via conductor changes in a depth direction of the via conductor.

Abstract: A display device includes a flexible display panel for displaying an image, and a printed circuit board electrically connected with the flexible display panel through a circuit film. The printed circuit board may include a plurality of boards in a stack, the boards being respectively provided with integrated circuits, driving chips, and circuit wires, and a conducting portion connecting circuit wires of at least two boards among the plurality of boards.

Abstract: In one embodiment, a circuit board is disclosed. The circuit board includes a first metal core; a second metal core spaced apart from the first metal core in a first direction when viewed as a cross section, such that a first side of the first metal core faces a first side of the second metal core; a first electrode electrically connected to the first side of the first metal core; a second electrode electrically connected to the first side of the second metal core facing the first metal core; and a dielectric layer between the first and second electrodes.

Abstract: In a circuit board for a semiconductor package, the contact pad of the circuit board is partially exposed through a contact hole and a subsidiary pad is provided around the contact hole in such a way that the contact hole is defined by the subsidiary pad. A subsidiary film having the subsidiary pad is provided on a mask pattern for protecting an internal circuit pattern and the contact pad from their surroundings. A contact terminal is provided on the subsidiary film in such a way that the contact hole is at least partially filled with the contact terminal and the subsidiary pad is covered with the contact terminal and an external body is bonded to the contact terminal. The contact area between the circuit board and the contact terminal is enlarged due to the subsidiary pad, thereby increasing the contact reliability of the semiconductor package.

Abstract: A high frequency device includes a base plate having a main surface, a dielectric on the main surface, along a first side of the base plate, a signal line on the dielectric and extending from the first side toward a central portion of the main surface, an island pattern of a metal on the dielectric, a metal frame having a contact portion contacting the main surface and a bridge portion on the signal line and the island pattern, together enclosing the central portion, a lead frame connected to an outside signal line of the signal line and which is located outside the metal frame, a semiconductor chip secured to the central portion, and a wire connecting the semiconductor chip to an inside signal line of the signal line and which is enclosed within the metal frame.

Abstract: Disclosed are various embodiments of power source redundancy in a power supply for a rack mounted computing device. The power supply includes a plurality of AC power converters configured to receive power from corresponding power sources. A first AC power converter provides DC power to a common DC bus of the power supply. A second AC power converter provides DC power to the common DC bus in response to a change in the voltage level provided by the first AC power converter.

Abstract: A conductive material includes a first metal part whose main ingredient is a first metal; a second metal part formed on the first metal part and whose main ingredient is a second metal, the second metal having a melting point lower than a melting point of the first metal, which second metal can form a metallic compound with the first metal; and a third metal part whose main ingredient is a third metal, which third metal can make a eutectic reaction with the second metal.

Abstract: A display panel that includes: a display substrate; a driving chip bonded onto the display substrate; an anisotropic conductive film provided between the display substrate and the driving chip; and a protection film attached to a bottom of the display substrate, and the protection film is provided with a bending prevention means.

Abstract: A semiconductor chip (101) with bond pads (110) on a substrate (103) with rows and columns of regularly pitched metal contact pads (131). A zone comprises a first pair (131a, 131b) and a parallel second pair (131c, 131d) of contact pads, and a single contact pad (131e) for ground potential; staggered pairs of stitch pads (133) connected to respective pairs of adjacent contact pads by parallel and equal-length traces (132a, 132b, etc.). Parallel and equal-length bonding wires (120a, 120b, etc.) connect bond pad pairs to stitch pad pairs, forming differential pairs of parallel and equal-length conductor lines. Two differential pairs in parallel and symmetrical position form a transmitter/receiver cell for conducting high-frequency signals.

Abstract: A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via.

Abstract: Disclosed herein is a method for fabricating a printed circuit board, including: stacking a second insulating layer including a reinforcement on an outer surface of a first insulating layer having a post via formed thereon; polishing an upper surface of the second insulating layer to expose an upper side of the post via; stacking a film member on the second insulating layer to cover the post via and compress the second insulating layer; polishing an upper surface of the film member to expose an upper side of the post via; and forming a circuit layer connected to the post via on the upper surface of the film member.

Abstract: A package substrate is disclosed. The package substrate includes a base layer and a dam structure or a dent structure on at least one side of the base layer. The base layer may be a CCL core, a molding compound, or an epoxy base.

Abstract: A display panel includes a periphery area, an active display area adjacent to the periphery, a driving chip disposed out of the active display area for driving the active display area, and a plurality of wires electrically connecting the driving chip and the active display area. The width of at least one wire at a portion adjacent to the driving chip is smaller than the width of the at least one wire at the other portion adjacent to the active display area.

Abstract: A circuit board having a semiconductor chip embedded therein includes: a core board having opposing first and second surfaces and a through-hole; a semiconductor chip received in the through-hole and having a first active surface and an opposing second active surface, wherein first electrode pads comprising signal pads, power pads, and ground pads are provided on the first active surface; a first dielectric layer provided on the first surface of the core board and the first active surface of the semiconductor chip and configured to fill a gap between the through-hole and the semiconductor chip so as to secure the semiconductor chip in position to the through-hole; and a first circuit layer disposed in the first dielectric layer so as to be flush with the first dielectric layer, provided with first conductive vias disposed in the first dielectric layer, and electrically connected to the first electrode pads.

Abstract: A semiconductor device includes a semiconductor chip, a plurality of external terminals, and a board. The board includes a first main surface in which a plurality of first electrodes electrically connected to the semiconductor chip are formed, a second main surface in which a plurality of second electrodes electrically connected to the plurality of external terminals are formed, and a plurality of interconnect layers, provided between the first main surface and the second main surface, for forming a plurality of signal paths that electrically connect the first electrode and the second electrode corresponding thereto. The interconnect layer includes a plurality of metal members which are dispersedly disposed at a distance shorter than an electromagnetic wavelength equivalent to a signal band of a signal supplied to the signal path, in the vicinity of a portion in which a structure of an interconnect for forming the signal path is changed.

Abstract: Disclosed herein is a circuit board that includes a resin substrate including a substrate wiring layer, and an electronic component embedded in the resin substrate and having a plurality of external electrodes. The resin substrate includes a plurality of via holes that expose the external electrodes and a plurality of via conductors embedded in the via holes to electrically connect the substrate wiring layer to the external electrodes. At least some of the via holes are different in planar shape from each other.

Abstract: A laminate electronic device comprises a first semiconductor chip, the first semiconductor chip defining a first main face and a second main face opposite to the first main face, and having at least one electrode pad on the first main face. The laminate electronic device further comprises a carrier having a first structured metal layer arranged at a first main surface of the carrier. The first structured metal layer is bonded to the electrode pad via a first bond layer of a conductive material, wherein the first bond layer has a thickness of less than 10 ?m. A first insulating layer overlies the first main surface of the carrier and the first semiconductor chip.

Abstract: The present invention relates to a printed circuit board, a semiconductor package using the same, and a method for manufacturing the printed circuit board and the semiconductor package. The method for manufacturing a semiconductor package in accordance with the present invention includes: forming a circuit of a predetermined pattern on a PCB substrate; applying a first insulating material on the substrate; removing the first insulating material in the remaining portion except a predetermined portion by exposing and developing the substrate; forming a solder bump in the circuit portion exposed; molding a certain region of an upper surface portion of the PCB substrate including the solder bump by filling a second insulating material on the PCB substrate including the circuit portion; mounting a semiconductor chip on the PCB substrate; and completing one package in which the semiconductor chip and the PCB substrate are integrated.

Abstract: A printed wiring board includes an interlayer insulation layer, first pads positioned to mount a semiconductor element and forming a first pad group on the insulation layer, second pads forming a second pad group on the insulation layer and positioned along a peripheral portion of the first group, a first solder-resist layer formed on the insulation layer and having first openings exposing the first pads, respectively, and second openings exposing the second pads, respectively, conductive posts formed on the second pads through the second openings of the first solder-resist layer, respectively, and a second solder-resist layer formed on the first solder-resist layer and having a third opening exposing the first pads and fourth openings exposing surfaces of the posts, respectively. The second openings have a diameter greater than a diameter of the posts, and the second solder-resist layer is filling gaps formed between the second openings and the posts.

Abstract: In one embodiment, a biasing device is actuated using an actuator which is aligned with the biasing device along an alignment axis. A first frame is thereby biased toward a second frame along the alignment axis to bias an integrated circuit package toward a socket. The actuator also latches the first and second frames together and biased towards each other with the integrated circuit package and the socket biased toward each other. Other aspects and features are also described.

Abstract: In one embodiment, a stack device comprising a film interposer of a polyimide film material, for example, is assembled. In accordance with one embodiment of the present description, a front side of the film interposer is attached to a first element of the stack device, which may be an integrated circuit package, an integrated circuit die, a substrate such as a printed circuit board, or other structure used to fabricate electronic devices. In addition, a back side of the film interposer is attached to a second element which like the first element, may be an integrated circuit package, an integrated circuit die, a substrate such as a printed circuit board, or other structure used to fabricate electronic devices. Other aspects are described.

Abstract: A method of manufacturing an optical component embedded printed circuit board, the method including: stacking a first insulation layer on one side of a metal core; embedding an optical component in a cavity formed in the metal core; stacking a second insulation layer of a transparent material on the other side of the metal core; and forming a circuit pattern on the first insulation layer, the circuit pattern electrically connected with the optical component.

Abstract: Disclosed herein is a manufacturing method of a circuit board. The manufacturing method includes a first step for preparing a prepreg in which a core material is impregnated with an uncured resin. The prepreg has a through-hole surrounded by the core material and the resin so as to penetrate through the core material and the resin. The manufacturing method further includes a second step for housing a semiconductor IC in the through-hole, and a third step for pressing the prepreg so that a part of the resin flows into the through-hole to allow the semiconductor IC housed in the through-hole to be embedded in the resin.

Abstract: Electronic devices may contain electrical systems in which electrical components are mounted on a substrate such as a printed circuit board. The electrical components may include surface mount technology components. Multiple surface mount technology components may be stacked on top of each other and beside each other to form an electrical component that minimizes the amount of area that is consumed on a printed circuit board. Noise suppression circuits and other circuits may be implemented using stacked surface mount technology components. Surface mount technology components placed on the printed circuit board may be pushed together and subsequently injection molded to form packed component groups. An integrated circuit may be mounted to the printed circuit board via an interposer and may cover components mounted to the printed circuit board. An integrated circuit may be mounted over a recessed portion of the printed circuit board on which components are mounted.

Abstract: A display apparatus including a display and a waveguide plate is provided. The display panel includes multiple rows of display units and multiple rows of solar cell units. The display units and the solar cell units are substantially parallel to a first direction and alternately arranged along a second direction perpendicular to the first direction. The waveguide plate is disposed at one side of the display panel. A first side of the waveguide plate adjacent to the display panel includes multiple microstructures. First and second structure surfaces of each microstructure respectively correspond to one row of the display units and one row of the solar cell units. When the display apparatus is disposed such that the second direction is perpendicular to a ground surface, an inclination of the first structure surface makes a thickness of the waveguide plate gradually decrease along an upward direction from the ground surface.

Abstract: A circuit board includes a first circuit area, a first processing unit and a conductive pattern. The first circuit area includes a plurality of first electrically contacts. The first processing unit, which includes a ball grid array (BGA) substrate, is disposed on the first circuit area and is electrically connected to the first electrically contacts. The BGA substrate has a plurality of solder balls and a bypass circuit. The conductive pattern is electrically connected to the first electrically contacts.

Abstract: A computer processor retention device comprises a load frame, a load plate, and a pair of retractable cover members. The load frame may be secured to a circuit board around a processor mounting site. The load plate is pivotally coupled to the load frame and is pivotable between being open for receiving a processor at the processor mounting site and closed in engagement with a periphery of the received processor. The load plate has a window that is open to the processor mounting site when the load plate is closed. The retractable cover members span the window and are alternately movable along a track toward one another to cover the processor mounting site and away from one another to expose the processor mounting site.

Abstract: According to one embodiment, semiconductor memory device is capable of operating at a first mode and a second mode which is higher in speed than the first mode. The semiconductor memory device comprising: a semiconductor memory; a controller which controls the semiconductor memory; a connector which is provided with terminals for sending and receiving data to and from an external device; and a substrate on which the semiconductor memory, the controller, and the connector are mounted, the substrate comprising a plurality of wiring layers. The controller and the connector are mounted on an identical surface of the substrate. The substrate comprises a wiring which connects a mounting pad for the terminal for data transfer at the second mode of the connector and a mounting pad for a pin for data transfer at the second mode of the controller to each other on the wiring layer on a mounting surface for the connector and the controller.

Abstract: A wiring substrate with improved heat dissipation capability and with reduced size is disclosed. The wiring substrate includes a metal core substrate, a buffer layer formed so as to cover at least a part of the metal core substrate and containing a phase change material or a material with an electrocaloric effect, an electronic device mounted on a surface of a base including the metal core substrate and the buffer layer or inside the base, and a thermal via formed between the electronic device and the buffer layer.

Abstract: Methods and apparatus for improved electromagnetic interference (EMI) shielding and thermal performance in integrated circuit (IC) packages are described. A die-up or die-down package includes a protective lid, a plurality of ground posts, an IC die, and a substrate. The substrate includes a plurality of ground planes. The IC die is mounted to the substrate. Plurality of ground posts is coupled to plurality of ground planes that surround IC die. Protective lid is coupled to plurality of ground posts. The plurality of ground posts and the protective lid from an enclosure structure that substantially encloses the IC die, and shields EMI from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.

Abstract: A circuit device according to one exemplary embodiment includes a ceramic substrate, a first conductive pattern provided on one face of the ceramic substrate, a second conductive pattern, formed mainly of Cu, which is provided on the other face of the ceramic substrate, and a semiconductor element provided on an island that constitutes the second conductive pattern. An electrode, whose outermost surface is formed mainly of Cu, is provided in the semiconductor element, and the interface between the island and the electrode is directly fixed by solid-phase bonding.

Abstract: A power FET (100) comprising a leadframe including a pad (110), a first lead (111), and a second lead (112); a first metal clip (150) including a plate (150a), an extension (150b) and a ridge (150c), the plate and extension spaced from the leadframe pad and the ridge connected to the pad; a vertically assembled stack of FET chips in the space between the plate and the pad, the stack including a first n-channel FET chip (120) having the drain terminal on one surface and the source and gate terminals on the opposite surface, the drain terminal attached to the pad, the source terminal attached to a second clip (140) tied to the first lead; and a second n-channel FET chip (130) having the source terminal on one surface and the drain and gate terminals on the opposite surface, the source terminal attached to the second clip, its drain terminal attached to the first clip; wherein the drain-source on-resistance of the FET stack is smaller than the on-resistance of the first FET chip and of the second FET chip.

Abstract: Representative implementations of devices and techniques provide isolation between a carrier and a component mounted to the carrier. A multi-layer device having lateral elements provides electrical isolation at a preset isolation voltage while maintaining a preselected thermal conductivity between the component and the carrier.

Abstract: A component may be configured for connection with a microelectronic assembly having terminals and a microelectronic element connected with the terminals. The component may include a support structure bearing conductors configured to carry command and address information, and a plurality of contacts coupled to the conductors and configured for connection with the terminals.