Abstract: In a particular embodiment, there are a plurality of parallel electrically conductive rows and a plurality of parallel electrically conductive columns crossing the rows, thereby forming a cross-point array with a plurality of intersections. Resistive devices, such as magnetic memory cells, also known as spin valve memory cells, are provided in electrical contact with and located at each intersection. A feedback controlled sense pre-amplifier is also provided to maintain an equi-potential for a given memory cell. A reference voltage is provided to the sense pre-amplifier. As voltage potential, VA?, is provided to the first end of a selected column, contacting a selected memory cell, a feedback voltage VA is provided to the sense pre-amplifier by an independent sense path. The independent sense path connects to the second end of the selected column. The sense pre-amplifier adjusts the applied potential VA to minimize the difference between the feedback and reference voltage.

Abstract: A memory storage device includes a memory cell configurable to have at least a first conductive state and includes a first and second conductor each electrically coupled to the memory cell. A regulation circuit is configured to regulate a sense voltage on the second conductor to be independent of a current conducted through the first conductor when the memory cell is configured to have the first conductive state.

Abstract: A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.

Abstract: A bistable electrical device (50) employing a bistable body (52) and a high conductivity material (54). A sufficient amount of high conductivity material (54) is included in the bistable body (52) to impart bistable between a low resistance state and a high resistance state by application of an electrical voltage (60).

Abstract: It is an object of the present invention to make it possible to decrease the on-state resistance of a selection transistor of a memory cell without increasing the whole area of a memory cell array and accelerate and stabilize the reading operation of data stored in the memory cell. Therefore, a plurality of variable resistive elements capable of storing information in accordance with a change of electrical resistances is included, one ends of the variable resistive elements are connected each other, and an electrode of a selection element constituted by a MOSFET or diode element for selecting the variable resistive elements in common is connected with one end of each of the variable resistive elements to constitute a memory cell.

Abstract: The present invention is directed to systems for evaluating one-time programmable memory cells. A threshold current is applied to a resistive circuit, thereby generating a threshold voltage. A read current is applied to a first memory cell, thereby generating a memory cell voltage. The memory cell voltage is compared to the threshold voltage, thereby determining the state of the memory cell. In a further embodiment of the invention, a second threshold voltage is generated and compared the memory cell voltage, thereby verifying the state of the memory cell. The threshold current is optionally a substantial replica of said read current. The threshold current is optionally a proportional substantial replica of said read current. In an embodiment, the resistive circuit includes a second memory cell, which can be programmed or unprogrammed. The second memory cell is optionally arranged to average the memory cell resistance.

Abstract: A magnetic memory includes a plurality of variable resistors arrayed as memory elements in a matrix, a plurality of bit lines each of which is arranged on each row of the matrix and connected to one terminal of each variable resistor belonging to the same row, a read circuit which detects the resistance values of the variable resistors based on currents flowing through the bit lines, and load elements connected to the bit lines independently of and in parallel with the memory elements.

Abstract: A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode.

Abstract: A memory may have access devices formed using a chalcogenide material. The access device does not induce a snapback voltage sufficient to cause read disturbs in the associated memory element being accessed. In the case of phase change memory elements, the snapback voltage may be less than the threshold voltage of the phase change memory element.

Abstract: A resistance variable memory element and method for stabilizing the resistance variable memory element by providing a first and second electrode connected to a resistance variable material whereby the first and second electrodes comprise materials capable of providing a differential electrochemical potential across the resistance variable memory element which causes the resistance variable memory element to write to a predetermined “on” state. The resistance variable memory element is stabilized in a low resistance “on” state by the differential electrochemical potential. The first electrode preferably is a platinum electrode and the second electrode is preferably a silver electrode. The method and circuitry further includes a reverse refresh for stabilizing the resistance variable memory element in a high resistance state by applying a reverse voltage to the memory element.

Abstract: A programming method which controls the amount of a write current applied to a Phase-change Random Access Memory (PRAM), and a write driver circuit realizing the programming method. The programming method includes maintaining a ratio of a resistance of the PCM in the higher resistance state to a resistance of the Phase-change Memory (PCM) in the lower resistance state constant or substantially constant independent of an ambient temperature. The ratio may be maintained by increasing, decreasing, or keeping the same a reset current and/or a set current.

Abstract: A dynamically-operating restoration circuit (106) is used to apply a voltage or current restore pulse signal to thyristor-based memory cells (108) and therein restore data in the cell using the internal positive feedback loop of the thyristor (110). In one example implementation, the internal positive feedback loop in the thyristor (110) is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.

Abstract: This invention relates to a resistive memory array architecture which incorporates certain advantages from both cross-point and one transistor per cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the one transistor per cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of resistive memory cells each column being provided in a respective stacked memory layer.

Abstract: A data storage device having parallel memory planes is disclosed. Each memory plane includes a first resistive cross point plane of memory cells, a second resistive cross point plane of memory cells, a plurality of conductive word lines shared between the first and second planes of memory cells, a plurality of bit lines, each bit line coupling one or more cells from the first plane to another memory cell in the second plane, and a plurality of unidirectional elements. Further, the one unidirectional element couples a first memory cell from the first plane to a selected word line and a selected bit line in a first conductive direction and a second unidirectional element couples a second cell from the second plane to the selected word line and selected bit line in a second conductive direction. The device further provides for a unidirectional conductive path to form from a memory cell in the first plane to a memory cell in the second plane sharing the same bit line.

Abstract: A memory cell is provided with a pair of electrodes, and an active layer sandwiched between the electrodes and including a molecular system and ionic complexes distributed in the molecular system. The active layer having a high-impedance state and a low-impedance state switches from the high-impedance state to the low-impedance state when an amplitude of a writing signal exceeds a writing threshold level, to enable writing information into the memory cell. The active layer switches from the low-impedance state to the high-impedance state when an amplitude of an erasing signal having opposite polarity with respect to the writing signal exceeds an erasing threshold level, to enable erasing information from the memory cell.

Abstract: The present invention provides an improved write circuit and method for writing a programmable conductor random access memory (PCRAM) cell. The method comprises precharging a bit line to a first voltage and applying a second voltage to a first terminal of a chalcogenide memory element. A second terminal of the chalcogenide memory element is selectively coupled to the bit line to produce a voltage across the memory element sufficient to write a predetermined resistance state into the element. The first voltage may take on two different values to program two different resistance states into the memory element.

Abstract: A resistance variable memory element with improved data retention and switching characteristics switched between resistance memory states upon the application of write pulses having the same polarity. The resistance variable memory element can be provided having at least one silver-selenide layer in between glass layers, the glass layers are a chalcogenide glass having a GexSe100?x composition.

Abstract: A phase change memory includes a plurality of word lines, a plurality of bits lines intersecting the word lines, and a plurality of memory cells arranged in rows along the word lines and located at corresponding intersection regions of the word lines and bit lines. Each of the memory cells includes a cell transistor having a gate connected to a corresponding word line, and a resistor and a phase change cell connected in series between a drain of the cell transistor and a corresponding bit line. In order to increase a cell drive current, the phase change memory also includes a plurality of auxiliary transistors respectively connected between the drains of the cell transistors of adjacent said memory cells.

Abstract: Non-volatile memory cell with a single semiconductor device per memory cell. The present invention generally allows for a plurality of memory cells to be formed on a semiconductor substrate that supports a semiconductor device. A multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse is formed above the substrate, generally at a very high temperature. While the layers fabricated between the substrate and the multi-resistive state material use materials that can withstand high temperature processing, the layers fabricated above the multi-resistive state material do not need to withstand high temperature processing.

Abstract: A phase-change memory element including a phase-change material. The phase-change memory element has a plurality of memory state wherein each of the memory states has a corresponding threshold voltage. The threshold voltages may be used to determine the current memory state of the memory element. The phase-change material may include a chalcogen element.

Abstract: Non-volatile memory cell with a single semiconductor device per memory cell. The present invention generally allows for a plurality of memory cells to be formed on a semiconductor substrate that supports a semiconductor device. A multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse is formed above the substrate, generally at a very high temperature. While the layers fabricated between the substrate and the multi-resistive state material use materials that can withstand high temperature processing, the layers fabricated above the multi-resistive state material do not need to withstand high temperature processing.

Abstract: A non-volatile memory circuit comprising first and second transistors (101, 102) each having a gate and a drain, wherein the gates of these transistors are connected to each other and the drains of these transistors are connected to each other, whereby a first inverter is formed; third and fourth transistors (103, 104) each having a gate and a drain, wherein the gates of these transistors are connected to each other and the drains of these transistors are connected to each other, whereby a second inverter is formed; a fifth transistor (105) provided with a gate, which is connected to a word line (107), and which is connected between a first bit line (108) and an input terminal of the second inverter; a sixth transistor (106) provided with a gate, which is connected to the word line (107), and which is connected between a second bit line (109) and an input terminal of the first inverter; and first and second resistor elements (114, 115) which are serially connected to the first and second inverters, respective

Abstract: An apparatus including a volume of phase change material disposed between a first conductor and a second conductor on a substrate, and a plurality of electrodes coupled to the volume of phase change material and the first conductor. A method including introducing, over a first conductor on a substrate, a plurality of electrodes coupled to the first conductor, introducing a phase change material over the plurality of electrodes and in electrical communication with the plurality of electrodes, and introducing a second conductor over the phase change material and coupled to the phase change material.

Abstract: MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SC1 and SC2. The sub-cell SC1 includes magneto resistive elements MTJ1 and MTJ2 and a selection transistor Tr1, and the sub-cell SC2 includes magneto resistive elements MTJ3 and MTJ4 and a selection transistor Tr2. The magneto resistive elements MTJ1 and MTJ2 are connected in parallel, and the magneto resistive elements MTJ3 and MTJ4 are also connected in parallel. Further, the sub-cells SC1 and SC2 are connected in series between the write/read bit line BLW/R and the ground.

Abstract: A non-volatile memory device, such as a Programmable Conductor Random Access Memory (PCRAM) device, having an exemplary memory stored state retention characteristic is disclosed. There is provided a method for retaining stored states in a random access memory device generally comprising the steps of programming a memory cell or an array of memory cells by applying a first voltage to the cells and stabilizing the cells by applying a second voltage to the cells, which is less than the first voltage. The second voltage, which acts as a stabilizing voltage, may be a read-out voltage. The second voltage may also be continuously applied to the cells. The second voltage may also be provided as a sweep voltage, a pulse voltage, or a step voltage.

Abstract: A novel switching device is provided with an active region arranged between first and second electrodes and including a molecular system and ionic complexes distributed in the system. A control electrode is provided for controlling an electric field applied to the active region, which switches between a high-impedance state and a low-impedance state when the electrical field having a predetermined polarity and intensity is applied for a predetermined time.

Abstract: A programmable multiple data state memory cell including a first electrode layer formed from a first conductive material, a second electrode layer formed from a second conductive material, and a first layer of a metal-doped chalcogenide material disposed between the first and second electrode layers. The first layer providing a medium in which a conductive growth can be formed to electrically couple together the first and second electrode layers. The memory cell further includes a third electrode layer formed from a third conductive material, and a second layer of a metal-doped chalcogenide material disposed between the second and third electrode layers, the second layer providing a medium in which a conductive growth can be formed to electrically couple together the second and third electrode layers.

Abstract: There are provided a phase change-type memory element, which can reduce a reset pulse current value necessary for returning the phase state from an ON state to an OFF state, can improve integration density, is not restricted by the process temperature at the time of the production thereof, and can be simply produced, and a process for producing the same. The phase change-type memory element comprises: two or more electrodes provided opposite to each other through an insulating layer; an exposed surface on which at least a part of the insulating layer and at least a part of each of the electrodes are exposed; and a phase change recording material layer provided, on the exposed surface, in contact with the at least two electrodes.

Abstract: An apparatus including a volume of phase change material disposed between a first conductor and a second conductor on a substrate, and a plurality of electrodes coupled to the volume of phase change material and the first conductor. A method including introducing, over a first conductor on a substrate, a plurality of electrodes coupled to the first conductor, introducing a phase change material over the plurality of electrodes and in electrical communication with the plurality of electrodes, and introducing a second conductor over the phase change material and coupled to the phase change material.

Abstract: The present invention is directed to methods and systems for evaluating one-time programmable memory cells. A threshold current is applied to a resistive circuit, thereby generating a threshold voltage. A read current is applied to a first memory cell, thereby generating a memory cell voltage. The memory cell voltage is compared to the threshold voltage, thereby determining the state of the memory cell. In a further embodiment of the invention, a second threshold voltage is generated and compared the memory cell voltage, thereby verifying the state of the memory cell. The threshold current is optionally a substantial replica of said read current. The threshold current is optionally a proportional substantial replica of said read current. In an embodiment, the resistive circuit includes a second memory cell, which can be programmed or unprogrammed. The second memory cell is optionally arranged to average the memory cell resistance.

Abstract: Providing a multi-output multiplexor. The invention is multi-output multiplexor that, depending on the control signals, allows various modulating circuits to pass no voltage, pass some voltage or pass all the voltage on one of the multiplexor's ports. A modulating circuit can be fully turned on, partially turned on, or fully turned off. In a preferred embodiment, a gate circuit is in electrical contact with ground such that when the gate circuit is turned on and its associated modulating curcuit is not passing voltage, the multiplexor output associated with the modulating curcuit goes to ground.

Abstract: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.

Abstract: A method and apparatus is disclosed for sensing the resistance state of a Programmable Conductor Random Access Memory (PCRAM) element using complementary PCRAM elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the high and low resistance elements to determine the resistance state of an element being read.

Abstract: The present invention relates to an apparatus for dividing a bank in a flash memory. A block of the flash memory is divided into two banks and each page buffer is located between the two banks to share an input/output line. Therefore, it is possible to shorten the length of a bit line, improve a data sensing rate, and allow one bank to perform one operation while the other bank performs a read, write or erase operation.

Abstract: A magnetic random access memory (MRAM) circuit block and access method thereof are disclosed herein which includes a circuit for sensing a data write current passing through a bitline 32 and, for generating a stop signal for stopping a data write current supply to the bitline 32 and a write wordline 30 after data is written in an magnetic tunnel junction (MTJ) element 44. Further, when data to be written to the storage element is the same as the data already stored therein, no write current is supplied to the write wordline 30, thereby saving power.

Abstract: A driver circuit having one or more MOS transistors. The driver circuit is capable of providing an output voltage greater than the power supply voltage; however, the magnitude of the voltages appearing across the terminals of the MOS transistors are preferably less than or equal to the magnitude of the power supply voltage. The driver circuit may comprise a plurality of serially coupled PMOS transistors and a plurality of serially coupled NMOS transistors wherein the plurality of PMOS transistors and plurality of NMOS transistors are coupled at the output node of the driver.

Abstract: A programming circuit is provided. As a conductive memory cell is programmed, its resistance changes. The provided programming circuit monitors the changing resistance while programming the memory cell. The programming circuit can be used to only program the memory cell for as long as programming is actually needed. Additionally, the programming circuit can be used to only program the memory cell when it has a value that needs to be changed.

Abstract: A method of programming a programmable resistance element. The programmable resistance element may be programmed to a BLOWN state. After being programmed to the BLOWN state, the element can no longer be programmed to its low resistance state. The method of programming allows the programmable resistance element to be used as a fuse.

Abstract: A magnetic random access memory (MRAM) device having parallel memory planes is disclosed. Each memory plane includes a first magneto-resistive cross point plane of memory cells, a second magneto-resistive cross point plane of memory cells, a plurality of conductive word lines shared between the first and second planes of memory cells, a first plurality of bit lines, each of the first plurality of bit lines coupling one or more cells from the first plane to at least one other memory cell in the first plane, a second plurality of bit lines, each of the second plurality of bit lines coupling one or more cells from the second plane to at least one other memory cell in the second plane, and a plurality of unidirectional elements.

Abstract: The present invention is a method, circuit and system for determining a reference voltage. Some embodiments of the present invention relate to a system, method and circuit for establishing a set of operating reference cells to be used in operating (e.g. reading) cells in an NVM block or array. As part of the present invention, at least a subset of cells of the NVM block or array may be read using each of two or more sets of test reference cells, where each set of test reference cells may generate or otherwise provide reference voltages at least slightly offset from each other set of test reference cells. For each set of test reference cells used to read the at least a subset of the NVM block, a read error rate may be calculated or otherwise determined. A set of test reference cells associated with a relatively low read error rate may be selected as the set of operating reference cells to be used in operating (e.g. reading) other cells, outside the subset of cells, in the NVM block or array.

Abstract: An output buffer circuit of the present invention includes a plurality of unit circuits in each of which a pull-up transistor controlled by a first input signal is connected between a high-potential power supply and common node, and a pull-down transistor controlled by a second input signal is connected between the common node and a low-potential power supply, an output terminal connected to a common connecting point of the common nodes of the plurality of unit circuits, and first resistors formed respectively between the common nodes of the plurality of unit circuits and the common connecting point.

Abstract: A nano-scale flash memory comprises: (a) source and drain regions in a plurality of approximately parallel first wires, the first wires comprising a semiconductor material, the source and drain regions separated by a channel region; (b) gate electrodes in a plurality of approximately parallel second wires, the second wires comprising either a semiconductor material or a metal, the second wires crossing the first wires at a non-zero angle over the channel regions, to form an array of nanoscale transistors; and (c) a hot electron trap region at each intersection of the first wires with the second wires. Additionally, crossed-wire transistors are provided that can either form a configurable transistor or a switch memory bit that is capable of being set by application of a voltage. The crossed-wire transistors can be formed in a crossbar array.

Abstract: Briefly, in accordance with an embodiment of the invention, a memory is provided. The memory may include a memory element and a first access device coupled to the memory element, wherein the first access device comprises a first chalcogenide material. The memory may further include a second access device coupled to the first access device, wherein the second access device comprises a second chalcogenide material.

Abstract: A method for reading and verifying the state of a memory cell during a write operation before writing allows a decision to be made whether to write to the cell or not based on the current state of the cell.

Abstract: A data storage device having parallel memory planes is disclosed. Each memory plane includes a first resistive cross point plane of memory cells, a second resistive cross point plane of memory cells, a plurality of conductive word lines shared between the first and second planes of memory cells, a plurality of bit lines, each bit line coupling one or more cells from the first plane to another memory cell in the second plane, and a plurality of unidirectional elements. Further, the one unidirectional element couples a first memory cell from the first plane to a selected word line and a selected bit line in a first conductive direction and a second unidirectional element couples a second cell from the second plane to the selected word line and selected bit line in a second conductive direction. The device further provides for a unidirectional conductive path to form from a memory cell in the first plane to a memory cell in the second plane sharing the same bit line.

Abstract: The present invention provides a method and apparatus for writing a programmable conductor random access memory (PCRAM) element. After a read operation of the memory element a complement logical state from that read is written back to the memory element. In one embodiment the memory element is then again written back to its original state. In another embodiment logic circuitry keeps track of whether the original logic state or its complement are stored in the memory element so that during the next read the stored logic will be correctly read.

Abstract: A cell in a structural phase-change memory is programmed by raising cell voltage and cell current to programming threshold levels, and then lowering these to quiescent levels below their programming levels. A precharge pulse is then applied which raises the bitline voltage of the selected cell and does not raise the cell voltage and cell current to their programming levels. Then, the cell current is raised to a read level which is below the programming threshold level, and the bitline voltage is compared to a reference voltage while the cell current is at the read level.

Abstract: A magnetic memory includes a plurality of variable resistors arrayed as memory elements in a matrix, a plurality of bit lines each of which is arranged on each row of the matrix and connected to one terminal of each variable resistor belonging to the same row, a read circuit which detects the resistance values of the variable resistors based on currents flowing through the bit lines, and load elements connected to the bit lines independently of and in parallel with the memory elements.

Abstract: A memory cell comprises at least two antifuses in series with a diode. Each antifuse expresses a different resistance from the others when blown, and each requires an escalating programming voltage over the last to be programmed. The antifuse structures differ in their respective geometries and materials so that a low programming voltage will blow the more sensitive fuse first, and a higher voltages will program the lesser sensitive fuses thereafter.

Abstract: The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.