Abstract: A nonvolatile semiconductor memory according to an aspect of the invention includes a memory cell array and a power supply circuit. The memory cell array includes memory cells each having an insulating film and being programmed to store information by inflicting an electric stress on the insulating film to break the insulating film. The power supply circuit supplies to the memory cell a program voltage for the electric stress depending on a negative temperature coefficient the electric stress.

Abstract: The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.

Abstract: An object of the present invention is to provide a resistive nonvolatile memory element having an electric current path which can be realized by a simple and convenient process, and capable of allowing for micro-fabrication. The resistive nonvolatile memory element of the present invention includes first electrode 203, oxide semiconductor layer 204a which is formed on the first electrode 203 and the resistance of which is altered depending on the applied voltage, metal nanoparticles 204b having a diameter of between 2 nm and 10 nm arranged on the oxide semiconductor layer 204a, tunnel barrier layer 204c formed on the oxide semiconductor layer 204a and on the metal nanoparticles 204b, and second electrode 206 formed on the tunnel barrier layer 204c, in which the metal nanoparticles 204b are in contact with the oxide semiconductor layer 204a.

Abstract: A memory device 10 has an arrangement in which a memory thin film 4 is sandwiched between first and second electrodes 2 and 6, the memory thin film 6 contains at least rare earth elements, the memory thin film 4 or a layer 3 in contact with the memory thin film 4 contains any one of elements selected from Cu, Ag, Zn and the memory thin film 4 or the layer 3 in contact with the memory thin film 4 contains any one of elements selected from Te, S, Se. The memory device can record and read information with ease stably, and this memory device can be manufactured easily by a relatively simple manufacturing method.

Abstract: A magnetoresistive resistor memory cell having four individually polarizable magnetoresistive resistors that form a magnetoresistive bridge circuit. Each of the four magnetoresistive resistors is surrounded by a write trace segment pair. One upper write trace segment is directly above a magnetoresistive resistor and one lower write trace segment is directly below that resistor. The two write traces of a write trace segment pair are oriented at 90 degrees relative to the anisotropic axis, that is, the length, of the magnetoresistive resistor. The combination of the magnetoresistive resistor bridge circuit and four write trace segment pairs forms a magnetoresistive resistor memory cell.

Abstract: A nonvolatile memory, such as a write-once memory, includes a memory cell array that has first memory cells and at least one second memory cell. The memory also includes a first writing circuit that is capable of writing data to the first memory cells and the second memory cell, a second writing circuit, and a verify circuit which is capable of confirming whether the data is normally stored in the first memory cells. When the writing of data to one of the first memory cells fails, the second writing circuit is arranged to assign an address of the one of the first memory cells to the second memory cell. The first memory cells and the second memory cell are arranged to irreversibly change their electrical resistance when the data is stored in them. The first memory cells and the second memory cell include an organic compound layer interposed between a pair of electrodes.

Abstract: In a configuration having a nonvolatile memory and a volatile memory, when storage information of the nonvolatile memory is changed and an abnormal operation occurs due to temporary blackout, ?-ray or others, the abnormal operation is recovered to a normal operation regardless of the presence of the detection of the abnormal operation. A reset to be inputted to the nonvolatile memory is collectively transmitted for each 1 bit, each 1 word or each predetermined arbitrary bit, and the collectively transmitted reset serving as one unit is periodically transmitted, so that the abnormal operation is recovered to a normal operation without input signals from outside even if the storage information of the nonvolatile memory is changed due to temporary blackout, ?-ray or others.

Abstract: A method of programming a nonvolatile memory device includes (i) providing a nonvolatile memory cell comprising a diode in series with at least one metal oxide, (ii) applying a first forward bias to change a resistivity state of the metal oxide from a first state to a second state; (iii) applying a second forward bias to change a resistivity state of the metal oxide from a second state to a third state; and (iv) applying a third forward bias to change a resistivity state of the metal oxide from a third state to a fourth state. The fourth resistivity state is higher than the third resistivity state, the third resistivity state is lower than the second resistivity state, and the second resistivity state is lower than the first resistivity state.

Abstract: A memory device driving circuit is disclosed which drives a memory device including a first electrode, a second electrode, and a memory layer interposed between the first electrode and the second electrode. The memory device driving circuit may include a main driver connected to the memory device, to drive the memory device, and a secondary driver connected between the memory device and the main driver, to control a set resistance of the memory device. The memory device driving circuit may freely adjust the set resistance of the memory device, to maintain the resistance of the memory device at a desired value. Accordingly, an improvement in the operation reliability of the memory device may be achieved.

Abstract: Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between the first and second electrode.

Abstract: In a method of controlling resistance drift in a memory cell of a resistance-changeable material memory device, the resistance changeable material in the memory cell is treated so that a drift parameter for the memory cell is less than about 0.18, wherein a change in resistance of a memory cell over the time period is determined according to the relationship: Rdrift=Rinitial×t?; where Rdrift represents a final resistance of the memory cell following the time period, Rinitial represents the initial resistance of the memory cell following the programming operation, t represents the time period; and ? represents the drift parameter.

Abstract: A bistable resistance random access memory comprises a plurality of programmable resistance random access memory cells where each programmable resistance random access memory cell includes multiple memory members for performing multiple bits for each memory cell. The bistable RRAM includes a first resistance random access member connected to a second resistance random access member through interconnect metal liners and metal oxide strips. The first resistance random access member has a first resistance value Ra, which is determined from the thickness of the first resistance random access member based on the deposition of the first resistance random access member. The second resistance random access member has a second resistance value Rb, which is determined from the thickness of the second resistance random access member based on the deposition of the second resistance random access member.

Abstract: An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh. In some embodiments, the circuitry may further include shift registers and one or more arithmetic logic units to provide a video memory.

Abstract: A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell including a diode and a metal oxide antifuse dielectric layer over the first electrode, and forming a second electrode over the at least one nonvolatile memory cell. In use, the diode acts as a read/write element of the nonvolatile memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.

Abstract: A phase change memory apparatus includes a phase change memory array in which a plurality of phase change memory devices are arranged, and a pulse generator that supplies a writing current pulse, an erasure current pulse, and a reverse repair current pulse to the phase change memory devices in the phase change memory array. The reverse repair current pulse has opposite direction to the writing current pulse and the erasure current pulse of the phase change memory devices, and is of such a size that resultant Joule heat and electromigration move the elements of the reverse repair current pulse. The reverse repair current pulse has a width equal to or more than a smaller one of duration of a normal writing operation and duration of a normal erasure operation.

Abstract: In an example embodiment, an electronic circuit comprises a memory matrix with rows and columns of memory cells. First row conductors are provided for each of the rows. Second row conductors correspond to pairs of rows, each successive row forming a respective pair with a preceding one of the rows, so that each pair overlaps with one row of the next pair. Column conductors are provided for each of the columns. Each of the memory cells comprises an access transistor, a node and a first and a second resistive memory element. The access transistor has a control electrode coupled to the first row conductor of the row of the memory cell, a main current channel coupled between the column conductor for the column of the memory cell and the node. The first and second the resistive memory element are coupled between the node and the second row conductors for the pairs of rows to which the memory cell belongs.

Abstract: A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally include an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a bias across the electrodes, and thus information may be stored using the structure.

Abstract: In a phase-change random access memory (PRAM) device, a write operation is performed by applying a set pulse to failed PRAM cells. The set pulse comprises a plurality of stages sequentially decreasing from a first current magnitude to a second current magnitude. The first current magnitude or the second current magnitude varies from one write loop to another.

Abstract: The present invention relates to a phase change memory and a method of fabricating a phase change memory. The phase change memory includes a heater structure disposed on a phase change material pattern, wherein the heater structure is in a tapered shape with a bottom portion contacting the phase change material pattern. The fabrication of the phase change memory is compatible with the fabrication of logic devices, and accordingly an embedded phase change memory can be fabricated.

Abstract: A resistance variable memory apparatus (100) of the present invention is a resistance variable memory apparatus (100) using a resistance variable element (22) transitioning between plural resistance states in response to electric pulses of the same polarity, in which a series resistance setting unit (10) is configured to set a resistance value of the series current path and a parallel resistance setting unit (30) is configured to set a resistance value of a parallel current path such that the resistance values become resistance values at which a node potential is not larger than a second voltage level in a state where an electric pulse application device (50) is outputting a first electric pulse after the resistance variable element (22) has switched to the high-resistance state, and the node potential is not larger than a first voltage level in the state where the electric pulse application device (50) is outputting a second electric pulse after the resistance variable element (22) has switched to the low-re

Abstract: A contactless ID chip to which a signal is inputted from an antenna by a wireless means, where data can be written only once. In the contactless ID chip having a nonvolatile EEPROM, data indicating whether writing is performed to the EEPROM is written simultaneously with basic data writing, and once writing is performed to the EEPROM, other data cannot be written thereto.

Abstract: A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at least a portion of this material above a melting energy level. A portion of the energy applied to the phase change material is allowed to dissipate below the melting energy level. The shape of the energy dissipation from the phase change material is controlled until the energy applied to the phase change material is less than a quenched energy level, to cause the phase change device to have the desired Vth. A remaining portion of the energy applied to the phase change material is allowed to dissipate to an environmental level.

Abstract: A phase change memory device comprising a substrate. A plurality of bottom electrodes isolated from each other is on the substrate. An insulating layer crosses a portion of the surfaces of any two of the adjacent bottom electrodes. A pair of phase change material spacers is on a pair of sidewalls of the insulating layer, wherein the pair of the phase change material spacers is on any two of the adjacent bottom electrodes, respectively. A top electrode is on the insulating layer and covers the phase change material spacers.

Abstract: An integrated circuit having a resistance-based or resistively switching memory cell, and a method for operating a resistively switching memory cell is disclosed. One embodiment is adapted to be put in a low-resistance state by applying a first threshold voltage and in a high-resistance state by applying a second threshold voltage, wherein reading out of the data content from the memory cell is performed by applying a voltage to the memory cell in the range of the first or second threshold voltage or a higher voltage.

Abstract: A phase change memory device and a method of manufacturing the phase change memory device are provided. The phase change memory device may include a switching element and a storage node connected to the switching element, wherein the storage node includes a bottom electrode and a top electrode, a phase change layer interposed between the bottom electrode and the top electrode, and a titanium-tellurium (Ti—Te)-based diffusion barrier layer interposed between the top electrode and the phase change layer. The Ti—Te based diffusion barrier layer may be a TixTe1?x layer wherein x may be greater than 0 and less than 0.5.

Abstract: A method of programming a one-time programmable device is provided. A switching device disposed in a substrate is turned on and a program current is applied to a fuse electrically connected to the switching device, thereby cutting the fuse. The fuse includes a first electrode electrically connected to the switching device, a second electrode spaced apart from the first electrode, and a chalcogenide pattern disposed between the first and second electrodes. Related one-time programmable devices, phase change memory devices and electronic systems are also disclosed.

Abstract: When a phase-change element that can transition between a reset state (amorphous state) and a set state (crystalline state) is to be caused to transition to the reset state, a first pulse having a first voltage is applied to the phase-change element. The first voltage is higher than the threshold voltage in the reset state, and can cause current to flow that corresponds to an amount of generated heat required for placing the element in the reset state. When the phase-change element is to be caused to transition to the set state, a second pulse having a second voltage and the same time width as the first pulse is applied to the phase-change element. The second voltage that is higher than the threshold voltage but lower than the first voltage, and can cause only a current to flow that does not attain the necessary amount of generated heat.

Abstract: Provided are a phase change memory device and a method of forming the same. According to the phase change memory, a first plug electrode and a second plug electrode are spaced apart from each other in a mold insulating layer. A phase change pattern is disposed on the mold insulating layer. The phase change pattern contacts a top of the first plug electrode and a first potion of a top of the second plug electrode. An interconnection is electrically connected to a second portion of the top of the second plug electrode.

Abstract: A method and apparatus for programming a phase change memory cell is disclosed. A phase change memory cell includes a memory element of a phase change material having a first state, in which the phase change material is crystalline and has a minimum resistance level, a second state in which the phase change material is amorphous and has a maximum resistance level, and a plurality of intermediate states with resistance levels there between. The method includes using programming pulses to program the phase change memory cell in either the set, reset, or one of the intermediate states. To program in the intermediate states, a programming pulse creates a crystalline percolation path having an average diameter through amorphous phase change material and a second programming pulse modifies the diameter of the crystalline percolation path to program the phase change memory cell to the proper current level.

Abstract: A nonvolatile memory device may be operated in a multi-bit mode at a lower operating current and with higher integrated of the memory device. A first buried electrode may be used as a first bit line, a second buried electrode may be used as a second bit line, and/or a gate electrode may be used as a word line. First and second resistance layers may be programmed with 2-bit data and the 2-bit data may be read from the first and second resistance layers. More than 2-bit data may be programmed and read using more than 2 buried electrodes.

Abstract: A method and system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC). The method and system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching.

Abstract: A programming method for a phase-change random access memory (PRAM) may be provided. The programming method may include determining an amorphous state of a chalcogenide material using programming pulses to form programming areas having threshold voltages corresponding to logic high and logic low, and/or controlling a trailing edge of programming pulses during programming to control a quenching speed of the chalcogenide material so as to adjust a threshold voltage of the chalcogenide material. Accordingly, programming pulses corresponding to logic low or logic high may have uniform magnitudes regardless of a corresponding logic level. Accordingly, reliability of a PRAM device may be improved.

Abstract: A switching element for reversible switching between an electrically insulating OFF state and an electrically conductive ON state, having two electrodes, namely a reactive electrode and an inert electrode, and also a solid electrolyte arranged between the two electrodes, which is characterized by the fact that the electrical conductivity of the solid electrolyte increases as the temperature thereof rises, but essentially no longer increases below a critical decomposition temperature of the solid electrolyte.

Abstract: A phase change memory has a first electrode formed over a substrate, a patterned phase change material layer formed over the first electrode to contact the first electrode and including a conductive material, and a second electrode formed over the patterned phase change material layer to contact the patterned phase change material layer. Instead of heat generation, the conductive channel is used to adjust resistance while maintaining characteristics of non-volatile memories. Hence, the power consumption can be reduced. Due to no use of the phase change, the shortened lifetime of equipment for fabricating semiconductor memories, usually caused by a volume change during the phase change, can be reduced.

Abstract: A nonvolatile memory device including one-time programmable (OTP) unit cell is provided. The nonvolatile memory device includes: a unit cell; a detecting unit configured to detect data from the unit cell; and a read voltage varying unit configured to vary an input voltage and supply a varied read voltage to the unit cell.

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device comprises a substrate. A dielectric layer is formed over the substrate and a phase change material layer is embedded in the dielectric layer. A first conductive electrode is also embedded in the dielectric layer to penetrate the phase change material layer and extends perpendicular to a top surface of the dielectric layer.

Abstract: Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.

Abstract: A method of programming a nonvolatile memory device includes (i) providing a nonvolatile memory cell comprising a diode in series with at least one metal oxide, (ii) applying a first forward bias to change a resistivity state of the metal oxide from a first state to a second state; (iii) applying a second forward bias to change a resistivity state of the metal oxide from a second state to a third state; and (iv) applying a third forward bias to change a resistivity state of the metal oxide from a third state to a fourth state. The fourth resistivity state is higher than the third resistivity state, the third resistivity state is lower than the second resistivity state, and the second resistivity state is lower than the first resistivity state.

Abstract: A memory includes a bit line and a plurality of resistive memory cells coupled to the bit line. Each resistive memory cell is programmable to each of at least three resistance states. The memory includes a first resistor for selectively coupling to the bit line to form a first current divider with a selected memory cell during a read operation.

Abstract: A magnetic memory device and methods thereof are provided. The example magnetic memory device may include a transistor disposed within a given unit cell region and a magnetic tunneling junction (MTJ) element connected to the transistor, the MTJ element including an MTJ cell and first and second pad layers forming a magnetic field at first and second ends of the MTJ cell, the transistor including a drain connected to the first pad layer in the given unit cell region and a bit line, a source connected to the second pad layer in an adjacent unit cell region, and a gate connected to a word line corresponding to the given unit cell region.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell including a variable resistance element changing its electric resistance by voltage application and having current-voltage characteristics in which a positive bias current flowing when a positive voltage is applied from one electrode as a reference electrode to the other electrode through an incorporated rectifier junction is larger than a negative bias current, a memory cell selection circuit for selecting the memory cell from the memory cell array, a voltage supply circuit for supplying a voltage to the memory cell so that a predetermined positive voltage corresponding to the reading operation is applied to the other electrode of the variable resistance element, in the reading operation, and a readout circuit for detecting the amount of the positive bias current and reading the information stored in the selected memory cell, in order to suppress the reading disturbance of the memory cell.

Abstract: In a method of writing into a nonvolatile semiconductor memory device including a resistance memory element which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage, a variable resistor is parallelly connected to the resistance memory element, and when the voltage is applied to the resistance memory element to switch the resistance memory element between the high resistance state and the low resistance state, a resistance value of the variable resistor is set corresponding to the resistance state of the resistance memory element so that a writing circuit for applying the voltage to the resistance memory element, and a synthetic resistor of the resistance memory element and the variable resistor make the impedance-matching.

Abstract: Disclosed herein is a memory device having an increased level of integration with a simplified method of manufacture.

Abstract: The present invention is related to a memory circuit comprising: a resistive memory element comprising a programmable metallization cell, a bit line, a selection transistor operable to address the resistive memory element for coupling the resistive memory element to the bit line, and a further transistor coupled with the resistive memory element for applying a predefined potential at a node between the selection transistor and the resistive memory element.

Abstract: A memory device includes a first bit line in a first conducting layer and a second bit line parallel to the first bit line. The second bit line is in a second conducting layer. The memory device includes a MOS select transistor and a word line coupled to a gate of the MOS select transistor. The word line is at an angle with respect to the first bit line and the second bit line. The memory device includes a first resistive memory element coupled between a source of the MOS select transistor and the first bit line. The memory device includes a second resistive memory element coupled between a drain of the MOS select transistor and the second bit line.

Abstract: Provided are a non-volatile memory device having a threshold switching resistor, a memory array including the non-volatile memory device, and methods of manufacturing the same. A non-volatile memory device having a threshold switching resistor may include a first resistor having threshold switching characteristics, an intermediate electrode on the first resistor, and a second resistor having at least two resistance characteristics on the intermediate electrode.

Abstract: A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.

Abstract: A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.

Abstract: A printed read only memory (ROM) device that consists of an array of memory resistors, a reference resistor, and analog-to-digital circuit is disclosed. Resistance values are dependent on the data to be stored in the read only memory. During read operation, a resistor in the array is powered, activating a voltage divider between the powered resistor and the reference resistor. The analog-to-digital circuit will read the divided voltage level between the two resistors, compare the voltage supply level and interpret it into bits of memory data. During the manufacturing of the ROM circuit, an array of memory resistors is printed as the means for storage of the data. Resistive inks of specific resistance values are selected and printed in a preferred layout that includes a reference resistor coupled to the determined array of memory resistors and an analog to digital converter so as to form a read only memory with the received data.

Abstract: A memory device, and methods relating thereto, having memory cells in which a single an access transistor controls the grounding of at least two storage resistive memory elements, such as resistive storage elements, for purposes of reading the respective logical states of the storage elements. The logical states of the storage elements are decoupled from one another and are read independently. The storage elements are disposed in respective layers. Each storage element is coupled to first and second conductors having for reading the memory that have respective, parallel, longitudinal axes. The longitudinal axes are oriented substantially parallel to one another, at least in proximity to a particular storage element.