Abstract: An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include an antifuse component, a switch, and a read transistor having a control electrode. Within the nonvolatile memory cell, the switch can be coupled to the antifuse component, and the control electrode of the read transistor can be coupled to the antifuse component. The nonvolatile memory cell can be programmed by flowing current through the antifuse component and the switch and bypassing the current away the read transistor. Thus, programming can be performed without flowing current through the read transistor decreasing the likelihood of the read transistor sustaining damage during programming. Further, the antifuse component may not be connected in series with the current electrodes of the read transistor, and thus, during read operations, read current differences between programmed and unprogrammed nonvolatile memory cells can be more readily determined.

Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.

Abstract: An apparatus includes a bit cell of a programmable memory circuit. The bit cell includes a programmable device. The bit cell includes a first device having a first type. The first device is configured to conduct a first current between a first node and a second node in response to a first value of a signal on the word line and a signal on a bit line. The programmable device is configured to be programmed in response to a first level of the first current. The bit cell includes a circuit coupled to the second node. The circuit is configured to reduce a leakage current through the first device in response to a second value of the signal on the word line and based on a feedback signal. In at least one embodiment of the apparatus, the feedback signal is based on a signal on the bit line.

Abstract: A write-once memory can be written only once to each memory cell; therefore, a defective bit cannot be detected by an actual inspection of writing. Accordingly, as described above, the measures, in which a redundant circuit is provided and the defective bit is modified before shipping, cannot be taken; thus, it is difficult to provide a memory with few defects. It is an object of the present invention to provide a write-once memory where the probability of a defect is reduced considerably. A nonvolatile memory that can be written only once includes a redundant memory cell, a first circuit which allocates an address to the redundant memory cell, a second circuit which outputs a determination signal that expresses whether writing is performed normally or not, and a third circuit, to which the determination signal is inputted, which controls the first circuit and the second circuit.

Abstract: A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.

Abstract: Provided is a memory device in which the circuit structure is simplified while the functions of a memory including an OTP memory and a memory including a pseudo-MTP memory are maintained. A memory device includes a plurality of memory sets each including a mark bit storage area for storing a mark bit, which indicates that an object is deleted data, and a data bit storage area for storing data to be stored, the memory device being built from a one time programmable (OTP) memory including an OTP memory block and a pseudo-MTP memory block, the OTP memory block containing a given number of memory sets selected out of the plurality of memory sets to operate as an OTP memory, the pseudo-MTP memory block containing the rest of the plurality of memory sets which remains after the memory sets of the OTP memory block are excluded and operates as a pseudo-MTP memory. The mark bit is written in advance in the mark bit storage area of the OTP memory block.

Abstract: The present invention provides a non-volatile memory cell structure. A first isolation structure is disposed on a substrate and a semiconductor layer is disposed on the first isolation structure to form a silicon on insulator device. A first doping region is made of a portion of the semiconductor layer. A gate is disposed on the first doping region. A gate oxide layer is sandwiched between the first doping region and the gate. A second doping region is disposed within the semiconductor layer and outside the first doping region. A second doping region is in direct contact with the first doping region. A second isolation structure is disposed on the first isolation structure. Further, the second isolation structure surrounds the first doping region and the second doping region. The second isolation structure is also in direct contact with the first doping region and the second doping region.

Abstract: Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line.

Abstract: According to one embodiment, a semiconductor memory device includes first and second upper-layer contact members. The upper-layer contact members are arranged alternately with the first upper-layer contact members in a first direction and shifted in a second direction orthogonal to the first direction. Plugs are formed on the second upper-layer contact members. First metal wirings are provided on the first upper-layer contact members. Second metal wirings are provided on the plugs. A height of a top surface of the plugs is higher than a top surface of the first metal wirings. A width of a bottom surface of the first metal wirings in a shorter-side direction is shorter than a width of a top surface of the first metal wirings. A width of a bottom surface of the second metal wirings in a shorter-side direction is shorter than a width of a top surface of the second metal wirings.

Abstract: A signal converting system has a multi-segment digital to analog converter coupled to an error shaping loop. A control value is received at a vector processor that indicates a number N of elements that are to be selected from a vector having M elements. The elements of the vector are sorted into a bitonic sequence and separated into a larger value group and a smaller value group using a bitonic split. Only the larger value group is sorted into an ordered sequence with repeated bitonic splits when the control value is less than M/2, and N largest elements are selected from the ordered sequence. Only the smaller value group is sorted into an ordered sequence with repeated bitonic splits when the control value is greater than M/2, and N?M/2 largest elements are selected from the ordered sequence.

Abstract: An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer of a first conductivity type, second and third semiconductor layers of a second conductivity type, which are disposed to be separated from each other in the first semiconductor layer, a first electrode electrically connected to the second semiconductor layer, and a second electrode electrically connected to the third semiconductor layer, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, through application of a voltage equal to or higher than a predetermined threshold between the first electrode and the second electrode.

Abstract: An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer, second and third semiconductor layers, a dielectric film and a conductive film, a first electrode, a second electrode, and a third electrode, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, the filament being formed by causing a dielectric breakdown of at least a part of the dielectric film, through application of a voltage equal to or higher than a predetermined threshold between the second and third electrodes, thereby causing an electric current to flow between the conductive film and the third semiconductor layer.

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region and a gate disposed about a first portion of the body region. The device includes a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion, wherein the source and drain regions are opposing.

Abstract: A high density anti-fuse cell can be built at the cross points of two perpendicular interconnect lines, such as active region lines, active and polysilicon lines, active and metal lines, or polysilicon and metal lines. The cell size can be very small. At least one of the anti-fuse cells have a thin oxide fabricated before, after, or between a diode in at least one contact holes at the cross points of the interconnect lines. The thin oxide of the anti-fuse cells at the cross points can be selected for rupture by applying supply voltages in the two perpendicular lines. In some embodiments, a diode can be created after thin oxide is ruptured so that explicitly fabricating a diode or opening a contact hole at the cross-point may not be necessary.

Abstract: A One-Time Programmable (OTP) unit cell and a nonvolatile memory device having the same are disclosed. A unit cell of a nonvolatile memory device includes: an anti-fuse connected between an output terminal and a ground voltage terminal; a first switching unit connected to the output terminal to transfer a write voltage to the output terminal; and a second switching unit connected to the output terminal to transfer a read voltage to the output terminal.

Abstract: The present invention discloses a mask-ROM with reserved space (mask-ROMRS). On its original data-mask, at least one mask-region is reserved for the new contents and contains no patterns. The present invention further discloses a 3-D mask-ROM with reserved memory level(s) (3D-MPROMRL). At least one memory level is reserved for the new contents and not manufactured in the original 3D-MPROMRL. By avoiding mask replacement, the present invention minimizes extra mask cost due to content revision.

Abstract: A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.

Abstract: An apparatus and method for providing a read-only memory (ROM) bit cell having one each of a PMOS transistor and an NMOS transistor, which has reduced static and dynamic electric power losses, are described. In particular, the bit cell does not require a pre-charge transistor. The sense amplifier for determining the voltages on ROM bit lines may be a digital inverter, address decoding may be simplified since there are no timing requirements with respect to transistor pre-charge, and chips containing a plurality of ROM bit cell may be readily programmed. In one embodiment of the invention, each bit cell includes one PMOS transistor having its source in electrical connection with a voltage source, its drain connected or unconnected to a bit line, and its gate connected to an inverted version of the word line signal; and one NMOS transistor having its source connected to a lower voltage source, its drain connected or disconnected to the bit line, and its gate connected to the word line.

Abstract: A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.

Abstract: A semiconductor memory cell array includes an elongated continuous active region. First and second pass transistors are formed in the elongated continuous active region and form part of first and second adjacent memory cells, respectively, of a column of memory cells in the array. An isolation transistor is formed in the elongated continuous active region between the first and second pass transistors and biased in an off state. First and second word lines are coupled to the gates of the pass transistors for applying a reading voltage. The array includes a differential bit line pair including first and second bit lines, a first logic value being encoded into the memory cells by connecting the pass transistors to the first bit line and a second logic value being encoded into the memory cells by connecting the pass transistors to the second bit line.

Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

Abstract: A one time programmable memory having a memory cell formed on a substrate is provided. The memory cell has a transistor and an anti-fuse structure. The anti-fuse structure is consisted of a doping region, and a dielectric layer and a conductive layer is formed in the top edge corner region of an isolation structure. The upper surface of the isolation structure is lower than the surface of the substrate so as to expose the top edge corner region. The conductive layer is formed on the isolation structure and covers the top edge corner region. The dielectric layer is formed on the top edge corner region and between the doping region and the conductive layer. The memory cell stores the digital data depending on whether the dielectric layer breaks down or not.

Abstract: A semiconductor device includes a memory cell including a thyristor element with a gate having a pnpn structure formed in a semiconductor substrate, and a plurality of access transistors formed on the semiconductor substrate and each connected at a first terminal thereof to a storage node at one terminal of the thyristor element such that a potential at the storage node can be transmitted to bit lines different from each other, the gate of the thyristor element and the gates of the plurality of access transistors of the memory cell being connected to word lines different from one another.

Abstract: A memory includes conductive layers provided to extend along the word lines, memory cells each including a diode having a cathode connected to the conductive layer and a source line reading data stored in the memory cells, wherein either the conductive layers or the bit lines are in floating states in a standby time.

Abstract: Data is stored in a quantum-well type structure with double gate control. According to an example embodiment, a transistor-based data storage circuit includes a gate, a back gate and a semiconductor channel between the gate and the back gate. Carriers are stored in a storage pocket structure in the channel, in response to biases applied to the gate and back gate. Current passing through the channel is sensed and used to detect the stored carriers and, correspondingly, a memory state of the storage circuit.

Abstract: In an illustrative embodiment, a memory cell comprises a first and a second MOSFET, wherein the first MOSFET undergoes a process to modify the threshold voltage such that a modified threshold voltage represents a first stored logic value. By determining which one of the first and the second MOSFETs has an altered threshold voltage, the stored logic value is determinable. The threshold voltage of the first MOSFET is altered by supplying current through a MOSFET gate, causing a gate heating effect that results in a threshold voltage shift.

Abstract: A memory is so formed that, in a first block and a second block each including a prescribed number of the bit lines arranged therein, positions of the bit lines simultaneously selected in the first and second blocks with reference to ends of the first and second blocks respectively are different from each other.

Abstract: A non-volatile memory is provided. The non-volatile memory comprises at least a silicon-on-insulator transistor including a substrate; an insulating layer disposed on the substrate; an active region disposed on the insulating layer; and an energy barrier device disposed in the active region and outputting a relatively small current when the non-volatile memory is read.

Abstract: This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data.

Abstract: In a programmable circuit making use of fuse cells, a snapback NMOS or NPN transistor or SCR without reversible snapback capability is used as an anti-fuse, and programming comprises biasing the control electrode of the transistor to cause the transistor to go into snapback mode.

Abstract: A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.

Abstract: In a semiconductor integrated circuit device having a volatile memory high-speed operation is enabled and the density of the memory can be enhanced. The volatile memory includes a word line, a complementary bit line having bit lines, a plurality of common source lines, and a memory cell that is coupled with the word line and the complementary bit lines. The memory cell includes transistors. The gate electrodes of the transistors are coupled with the word line, and the drain electrode of one of the transistors is coupled with one of the bit lines. The drain electrode of the other transistor is coupled with the other bit line. The respective source electrodes of the transistors are coupled with any one of the common source lines, or brought in a floating state, thereby storing storage information in the memory cell.

Abstract: A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor in a first operation such that a lingering change is created in transistor characteristics of the MIS transistor in response to the data stored in the latch, wherein the MIS transistor includes a highly-doped substrate layer, a lightly-doped substrate layer disposed on the highly-doped substrate layer, diffusion regions formed in the lightly-doped substrate layer, a gate electrode, sidewalls, and an insulating film.

Abstract: A multi-bit memory cell stores information corresponding to a high resistive state and multiple other resistive states lower than the high resistive state. A resistance of a memory element within the multi-bit memory cell switches from the high resistive state to one of the other multiple resistive states by applying a corresponding current to the memory element.

Abstract: A pn junction type solar cell is formed in a predetermined region on a substrate made of glass. Light emitted from a light emitting unit reaches an n-type semiconductor layer after it passed through substrate. The solar cell generates electromotive force corresponding to a quantity of the emitted light. A control circuit, a mask ROM, a transmitting circuit and an antenna are formed on an upper side of the solar cell. A surface of a semiconductor storage device is entirely covered with an insulating film to block entry of outside air. The insulating film is typically formed of physicochemically stable glass or silicon dioxide.

Abstract: A memory array having memory cells comprising a diode and an antifuse can be made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and by using a diode having a lower band gap than that of silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example, hafnium silicon oxynitride or hafnium silicon oxide, are particularly effective. Diode materials with band gaps lower than that of silicon, such as germanium or a silicon-germanium alloy, are particularly effective.

Abstract: A memory operable at a high speed is obtained. This memory comprises a plurality of word lines, first transistors each connected to each the plurality of word lines for entering an ON-state through selection of the corresponding word line, a plurality of memory cells including diodes having cathodes connected to the source or drain regions of the first transistors respectively and a data determination portion connected to the drain or source regions of the first transistors for determining data read from a selected memory cell.

Abstract: Techniques for use with a fuse-based non-volatile memory circuit include digitally controlling a resistance threshold of the circuit. The circuit includes a fuse circuit and a comparator circuit. The comparator circuit is configured to compare a first signal indicative of the fuse resistance to a second signal indicative of a reference level. At least one of the first and second signals is digitally controllable. The comparator circuit is configured to generate a digital output signal indicative of the comparison. The circuit may include a first digital-to-analog converter circuit configured to generate a first analog signal based on at least a first plurality of digital signals. The first signal is at least partially based on the first analog signal. The circuit may include a control circuit configured to digitally control the digitally controllable ones of the first and second signals at least partially based on the digital output signal.

Abstract: A read only memory (ROM) for providing a high operational speed with reduced leakage and low power consumption. The read only memory (ROM) includes multiple bit lines, multiple word lines, multiple column select lines and these lines are operatively coupled with multiple transistors. The arrangement of the ROM is such that the word line of a selected row is pulled down to a ground voltage (Vgnd). Non-selected word lines are kept at a supply voltage VDD to ensure that unwanted rows will not have any sub-threshold current (as Vds=0). So during read “1” operation (that is when bit line (BL) is high) load cells would not leak unnecessarily. Thus the ROM achieves a high operational speed with reduced leakage and low power consumption.

Abstract: A nonvolatile memory, such as a write-once memory, includes a memory cell array that has first memory cells and at least one second memory cell. The memory also includes a first writing circuit that is capable of writing data to the first memory cells and the second memory cell, a second writing circuit, and a verify circuit which is capable of confirming whether the data is normally stored in the first memory cells. When the writing of data to one of the first memory cells fails, the second writing circuit is arranged to assign an address of the one of the first memory cells to the second memory cell. The first memory cells and the second memory cell are arranged to irreversibly change their electrical resistance when the data is stored in them. The first memory cells and the second memory cell include an organic compound layer interposed between a pair of electrodes.

Abstract: For realizing high speed one time programmable memory, bit line is multi-divided for reducing capacitance, so that the bit line is quickly charged when reading and multi-stage sense amps are used for connecting divided bit line, wherein the multi-stage sense amps are composed of a first dynamic circuit serving as a local sense amp for reading the memory cell, a second dynamic circuit serving as a segment sense amp for reading the local sense amp, and a tri-state inverter serving as an amplify circuit of a global sense amp for reading the segment sense amp. When reading data, a voltage difference in the bit line is converted to a time difference for differentiating high data (programmed) and low data (unprogrammed) by the multi-stage sense amps. And buffered data path is connected to the global sense amp for realizing fast data transfer. Additionally, alternative circuits and memory cell structures are described.

Abstract: Disclosed is a multichip system and method of transferring data between memory chips in direct. The multichip system includes first and second memory chips, and a host system to control operations of the first and second memory chips. The first memory chip controls the second memory chip to transfer data to the second memory chip in response to local transfer information provided from the host system. The first memory chip controls the host system not to access the first and second memory chips while conducting a local transfer operation. According to the invention, since the data is able to be directly transferred between the memory chips without the host system, it enhances the efficiency of the multichip system and improves a data transfer speed.

Abstract: An embodiment of a device for memorization of a memory bit is provided, comprising a bistable circuit having complementary first and second read/write terminals, wherein the device comprises an initialization input connected to said bistable circuit, said input being designed to go into a first state controlling a pre-load phase of said bistable circuit and following said preload phase, to go into a second state controlling setting up of said memory bit and its complement at said read/write terminals.

Abstract: The invention concerns a ROM comprising a set of memory points arranged in rows and columns, each memory point capable of storing two bits of data and comprising a single switch controllable to connect together first and second terminals of said switch, each of said first and second terminals being connected to one of first, second and third conductive lines, wherein said switch is connected via said first and second terminals between said first and second lines to encode a first data value, between said first and third lines to encode a second data value, between said second and third lines to encode a third data value, and both of said first and second terminals being connected to the same one of said first, second and third lines to encode a fourth data value.

Abstract: In a conventional semiconductor memory device, a replica circuit configured by using a dummy bit line has been unable to charge the dummy bit line to a desired potential due to off leak current. Consequently, the time required for charging or discharging the dummy bit line differs from the desired time, and therefore, it has been unable to set optimum operation timing. To solve these problems, a semiconductor memory device of the present invention includes a dummy memory cell array in which source lines of dummy memory cells are charged simultaneously by a charge circuit configured similarly to a dummy bit line charge circuit, thus suppressing off leak current and performing appropriate timing generation.

Abstract: The present invention provides a new semiconductor Read-Only Memory, ROM, which stores more than one bit per cell. The potential of multiple threshold voltages combined with the potential multiple ratios of device channel width and length makes an ROM cell store multiple bits feasible. An N-type or a P-type MOS device of the standard CMOS process or a flat-cell mask ROM process are operable devices and processes in the design of this multi layer cell ROM. The ROM cell with smaller size is implemented to represent the LSB bits, while the larger size ROM cell is to represent the MSB bits.

Abstract: A three-dimensional memory device includes a base layer having a memory array and peripheral circuits formed on a bulk silicon substrate, and N circuit layers each having a memory array formed on a silicon-on-insulator (SOI) substrate.

Abstract: An integrated circuit includes a logic portion including M conductive layers, a memory portion including N conductive layers, and at least one common top conductive layer over the logic portion and the memory portion. M is greater than N.

Abstract: A programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.

Abstract: A switching element has an ion conductor capable of conducting metal ions for use in an electrochemical reaction therein, a first electrode and a second electrode which are disposed in contact with said ion conductor and spaced a predetermined distance from each other, and a third electrode disposed in contact with the ion conductor. When a voltage for causing the switching element to transit to an on state is applied to the third electrode, metal is precipitated between the first electrode and the second electrode by metal ions, electrically interconnecting the first electrode and the second electrode. When a voltage for causing the switching element to transit to an off state is applied to the third electrode, the precipitated metal is dissolved to electrically disconnect the first electrode and the second electrode from each other.