Abstract: A self-aligned, nonvolatile memory structure based upon phase change materials, including chalcogenides, can be made with a very small area on an integrated circuit. The manufacturing process results in self-aligned memory cells requiring only two array-related masks defining the bit lines and word lines. Memory cells are defined at intersections of bit lines and word lines, and have dimensions that are defined by the widths of the bit lines and word lines in a self-aligned process. The memory cells comprise structures including a selection device, a heating/barrier plate layer and a phase change memory element, vertically arranged at the intersections of the bit lines and word lines.

Abstract: A cells array of mask read only memory, at least includes numerous essentially parallel cells chains and numerous isolation dielectric layers which are located between any two adjacent cells chains. Each cells chain at least includes: numerous gates that located on a substrate, numerous doped regions, numerous polysilicon layers, numerous cover dielectric layers, a conductor layer and numerous isolation dielectric layers.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A chip ID register configuration includes a shift register having individual stages. A fuse device connected to the shift register has fuses each substantially assigned to a respective one of the individual stages of the shift register, for identifying a chip having various required and non-required categories. The fuse device stores information from the categories to be read out serially through the shift register to identify the chip. A memory unit stores items of defined information. A logic circuit reads the fuse device for the required category and reads one of the items of defined information stored in the memory unit for the non-required category, on the basis of the categories of the chip to be identified. Standard testing of different chips is made possible while taking up little chip area.

Abstract: To correct a software bug in a microcomputer for use in various electric apparatus having a mask ROM mounted therein without correcting the mask ROM. When there is a bug in a first data, a predetermined bit of a second data is arranged to be rewritten. Thereby, the software bug of the microcomputer is corrected.

Abstract: A bit line selector for a virtual ground non-volatile read only memory (“NROM”) cell array is disclosed. The selector transistors are oriented such that the channel length is perpendicular to the bit line and the channel width is parallel to the bit line. Subsequent reduction in the bit line pitch does not affect the channel width of the select transistors or their drive current.

Abstract: A semiconductor memory comprises a memory cell array having a plurality of rows and a plurality of columns, a plurality of word lines each connected to a gate of memory cells of a corresponding row in the memory cell array, and a plurality of bit lines each connected to a connection node between a source of memory cells of a corresponding column in the memory cell array and a drain of memory cells of an adjacent column. Each word line is connected to a corresponding output of a row address decoder, and each bit line is connected through a switching transistor to a corresponding digit line which is connected through a column selector controlled by a column address decoder, to a sense amplifier or a precharge circuit. Each switching transistor is on-off controlled by a corresponding bank select line.

Abstract: A cells array of mask read only memory, at least includes numerous essentially parallel cells chains and numerous isolation dielectric layers which are located between any two adjacent cells chains. Each cells chain at least includes: numerous gates that located on a substrate, numerous doped regions, numerous polysilicon layers, numerous cover dielectric layers, a conductor layer and numerous isolation dielectric layers.

Abstract: A control circuit comprises an external command recognition section for recognizing an external command, the external command being an operation command input from outside the control circuit, an internal ROM bank including a plurality of storage regions, the internal ROM bank being used to store an internal code for achieving operations specified by the external command recognized by the external command recognition section, an internal ROM selection section for selecting a required storage region from the plurality of storage regions of the internal ROM bank in accordance with the external command recognized by the external command recognition section, a program counter for selecting and indicating an address of an internal command to be executed from a plurality of addresses of internal commands stored in the internal ROM bank, an internal command register for storing the internal command read from the internal ROM bank, and an internal command execution section for executing the internal command stored in

Abstract: The external intelligent component (3) connected with a microprocessor system (2) is described for essentially automatic control of a control element (1) without burdening the microprocessor system operation. The control parameters for the control element (1) are written into a data memory (6) of the external component (3) from the microprocessor system (2) and are read out internally from the data memory (6) during normal operation of the external component (3). Control of the external component (3) is possible by the microprocessor system (2) without blocking the system bus (5,7) of the microprocessor system (2) using a control line from the microprocessor to a reset input (RESET) of a controller (13) of the external component (3).

Abstract: An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit. The write voltage, particularly if greater than VDD, may be generated by an on-chip voltage generator, such as a charge pump, which may require an undesirably large amount of die area, particularly relative to a higher bit density three-dimensional memory array formed entirely in layers above a semiconductor substrate. In several preferred embodiments, the area directly beneath a memory array is advantageously utilized to layout at least some of the write voltage generator, thus locating the generator near the selected memory cells during a write operation.

Abstract: To correct a software bug in a microcomputer for use in various electric apparatus having a mask ROM mounted therein without correcting the mask ROM. When there is a bug in a first data, a predetermined bit of a second data is arranged to be rewritten. Thereby, the software bug of the microcomputer is corrected.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A semiconductor memory device is provided with a memory cell array, a sense circuit which activates main bit lines in the memory cell array, a buffer which generates an activating signal which activates the sense circuit from a control signal, an address designating section which selects a memory cell indicated by an address signal among a plurality of memory cells in the memory cell array, and a delay circuit which delays the activating signal and outputting it to the sense circuit. The address designating section activates a word line to which a memory cell indicated by the address signal is connected after some delay from the activation of a chip enable signal.

Abstract: A programmable circuit and its method of operation are disclosed in which a transistor is used as a programmable element. The transistor may be programmed to one of two different gate threshold voltage values for operation. During reading of the transistor, a gate threshold voltage between the two values is applied and the status of the transistor as on or off is determined to determine the program state of the transistor. The program state of the transistor can be determined by a simple latch circuit.

Abstract: A read only memory integrated semiconductor device includes at least one memory cell. The memory cell includes a storage transistor made within a semiconductor substrate and whose source is connected to ground. A word line is connected to the gate of the transistor. Only one of several bit lines may be connected to the drain of the transistor at a time.

Abstract: A ROM including columns of memory cells connected by columns to respective bit lines; a reference bit line; charge transistors controllable by a common charge line and respectively connecting the bit lines and the reference bit line to a high supply potential. The reference bit line is associated with a column of unprogrammed cells, and the memory includes means for activating the charge line before activation of a word line, the duration between the activation of the charge line and the activation of the word line, and the features of the charge transistors, being chosen so that the level variation of the bit lines is low as compared to the level of the high supply potential.

Abstract: A memory circuit that includes a series of parallel elongated diffusion bit lines and an array of 2-bit non-volatile memory cells connected between the diffusion bit lines. Column select circuits are located at the ends of the diffusion bits lines that selectively connect the diffusion bit lines to a bit line decoder circuit to read appropriate signals from selected memory cells. A series of metal jumpers extend over and connect the ends of the diffusion bit lines. By connecting both ends of the diffusion bit lines together, the metal jumpers allow the diffusion bit lines to be longer without increasing resistance, so that a single pair of column select circuit control a large number of memory cells to increase the area efficiency of the memory array. Conversely, the metal jumpers reduce the resistance in shorter diffusion bit lines, thereby increasing memory array endurance.

Abstract: This semiconductor memory device is provided with a plurality of main bit lines; a main bit line controller for controlling whether to impress a specific voltage on the main bit lines, connect the main bit lines to a sense amplifier, or place the main bit lines in the OPEN state, based on an address signal; a plurality of virtual main grounding lines; and a virtual main grounding line controller for controlling whether to impress a specific voltage on the virtual main grounding lines, impress a grounding voltage on the virtual main grounding lines, or place the virtual main grounding lines in the OPEN state, based on an address signal.

Abstract: To correct an unintentionally erasing error in an EPROM circuit, in accordance with the same one-bit data, each of first and second EPROM cells is either unprogrammed to output a first logic value representing an unprogrammed condition when reading or programmed to output a second logic value representing a programmed condition when reading. A logic operation gate outputs the first logic value when both the first and second EPROM cells output the first logic value and outputting the second logic value when at least one of the first and second EPROM cells output the second logic value. To correct unintentionally writing error in an N-bit EPROM circuit, a first parity is stored and a second parity is detected from N logic operation gates. If the first parity disagrees with the second parity, a correction signal is generated.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: In an EEPROM including a plurality of NAND memory cells each constituted by connecting memory cells each having a floating gate and a control gate in series with each other, first selection transistors respectively coupled between the same bit line and terminals, on one side, of each pair constituted by two NAND memory cells of the plurality of memory cells, and second selection transistors respectively coupled between terminals on the other side and source lines (SL), the first or second selection transistors are constituted by an enhancement transistor and a depletion transistor which are coupled in series with each other, and the arrangements of the depletion transistor and enhancement transistor of the first selection transistors are reversed to those of the second selection transistors in the same NAND memory cells.

Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.

Abstract: In a semiconductor memory device including memory cells, first and second decoders generate first and second selection signals, and a driver circuit generates a drive signal for driving the memory cells. The driver circuit includes a transfer gate, controlled by the first selection signal, thus passing the second selection signal to generate the drive signal.

Abstract: There is provided a non-volatile memory device having a multi-bit cell structure. In the non-volatile memory device, a memory cell array includes a plurality of cells of a first conductivity type which has different threshold voltages and are arranged in a matrix on a semiconductor substrate. A bulk region of a second conductivity type opposite to the first conductivity underlies the memory cell array and receives a predetermined back bias voltage when a cell is driven. The threshold voltage difference between states can be sufficiently widened because a state having a high bulk concentration is highly susceptible to a body effect. Therefore, reduction of masks leads to process simplicity, reduced turnaround time, and improved process margin.

Abstract: A flat-cell ROM array reduces the number of transistors utilized to read a memory cell, allows for the layout of straight metal lines, while sharing the metal lines between even and odd cells, and achieves very high density and high performance. Parallel buried diffusion regions are implanted in the substrate. A gate oxide is laid over the substrate. A plurality of polysilicon word lines are laid over the gate oxide perpendicular to the buried diffusion regions, so that the areas between respective pairs of buried diffusion regions and under the polysilicon word lines, form columns of flat cell field effect transistors. An insulating layer is laid over the polysilicon word lines and a plurality of metal bit lines and virtual ground lines are formed. These metal lines are shared by even and odd columns of field effect transistors. Access to metal lines is made through a plurality of block select transistors connected to every other buried diffusion bit line.

Abstract: A manufacturing method and a structure for ROM component having a silicon controlled rectifier as the basic memory instead of a channel transistor in a conventional ROM, and using a formation of contact windows for coding a ROM instead of performing an ion implantation process. Also, since a silicon controlled rectifier occupies a smaller component surface area, the level of integration is correspondingly increased. Furthermore, due to interposition of an insulating layer between two bit lines, short circuiting between the adjacent bit lines is prevented. The component of this invention operates by applying a suitable voltage to the word line electrode and the bit line electrode respectively to select a particular memory unit, and as a result, a current will flow in a vertical direction through the memory unit, exit through the common electrode depending on the ON/OFF state of the memory, and be detected there.

Abstract: An integrated circuit, apparatus, and a method is provided for programming and reading manufacturing information upon non-volatile storage elements of the integrated circuit. The manufacturing information includes the particular processing recipe and layout of the integrated circuit, each recipe or layout indicative of a specific hardware revision. The storage elements may be programmed prior to assembling the integrated circuit within a semiconductor package, and the programmed elements are read prior to shipping the packaged integrated circuit to a customer. If the read hardware revision is not qualified for release, the product will be placed in a staging area and prevented from shipping to a customer or end user. Thus, the programmed hardware revision serves to gate product at test before shipping that product to a customer.

Abstract: Disclosed is a field-emission erasable programmable read-only memory cell which includes one or more field-emission tips on one or more layers of the cell. The cell is programmable and/or erasable by electron emission from the emission tips. Methods of making and using this field-emission erasable programmable read-only memory (FEEPROM) cell are also provided.

Abstract: The present invention, generally speaking, provides compact ROM layouts for trace or via-programmable (e.g., metal programmable) using transistor stacks. A number of field effect transistors (for example, eight) are coupled in series. For a particular transistor, a logic zero is programmed by forming a metal trace between the source and drain of the transistor. To read out the value of a particular bit, a logic zero is applied to the gate of the corresponding transistor. Logic ones are applied to the gates of the remaining transistors in the stack. A logic one precharge signal is applied to the top and bottom of the stack. A logic zero is then applied to the bottom of the stack. The logic zero reaches a sense amplifier coupled to the top of the transistor stack only if there is a short circuit across the transistor being read, indicating a logic zero bit value. Otherwise, the precharged logic one condition remains.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A column of read-only-memory (ROM) cells is programmed to store two or more bits of information in each cell by forming a plurality of coding (bit) lines adjacent to the column of cells, and selectively connecting the cells to the plurality of coding lines so that the different logic conditions defined by the two or more bits are represented by the coding lines that are connected to a memory cell.

Abstract: A read only memory device having a given burst length comprises: a memory cell array having a plurality of memory cells, each of the memory cell storing a data bit; a pass gate circuit having a plurality of pass gate blocks assigned to a plurality of bit lines coupled to the memory cells; a sense amplifier circuit having a plurality of sense amplifiers connected to the pass gate blocks with a given ratio thereof; decoding means for causing the pass gate circuit to transfer a given number of the data bits from the memory cells to the sense amplifier circuit; and means for receiving the data bits from the sense amplifier circuit and for outputting a plurality of data bits corresponding to the burst length in a given operation mode. The memory device preferably conducts in a sequential mode or interleave mode, with a pipelined data output configuration according to the burst length.

Abstract: An integrated circuit anti-fuse is described which is fabricated as a capacitor using a layer of oxide. The two plates of the anti-fuse are coupled to appropriate voltage levels to rupture the oxide and form a conductive short between the plates. One of the plates is formed as a diffused well which is coupled to an external voltage during programming. The well is biased to an internal voltage during normal operation of the circuit incorporating the anti-fuse.

Abstract: An address storing PROM cell array formed of a PROM having one polysilicon layer stores an address of a defective cell contained in a mask ROM used as a main memory cell array. A data storing PROM cell array formed of a PROM having one polysilicon layer stores data to be written into the defective cell. When an input address hits the address stored in the address storing PROM cell array, an address detecting circuit reads out data stored in the data storing PROM cell array instead of data of the mask ROM. When data in an address corresponding to the defective cell of the mask ROM is rewritten twice or more, a priority setting circuit permits newest data to be preferentially read out.

Abstract: A semiconductor memory includes a plurality of main bit lines led to sense amplifiers and arranged in a row, direction, a first group of sub bit lines interposed between the memory banks and connected to the main bit lines through a first group of selection transistors, and a second group of sub bit lines interposed between the memory banks and the first group of sub bit lines and connected to a common ground line through a second group of selection transistors.

Abstract: In a ROM having a ROM core and a plurality of output enable circuit blocks, precharging is achieved by precharging one or more nodes in each output enable circuit block. Each of the nodes corresponds to a group of bit lines. Substantially less current is used to precharge the nodes than is used to precharge multiple bit lines. The output enable circuit block includes a plurality of column enable circuits and a least one buffer. Each column enable circuit receives an enable signal and a bit line signal, and has an output line coupled to one of the buffers. During precharging, the output lines are in tri-state and the precharge signal drives the buffers. After precharging, one enable signal goes active. The corresponding column enable circuit generates an output which drives a buffer. The other column enable circuits are in tri-state.

Abstract: Non-volatile storage elements are provided on an integrated circuit, where the non-volatile storage elements are low voltage CMOS devices and hence compatible in a manufacturing sense with other similar transistors on an integrated circuit, thereby not requiring special types of transistors for the non-volatile storage. The non-volatile storage elements are either one-time programmable devices which are programmed by rupturing their gate oxide, EEPROM floating gate transistor cells, or other EEPROM cells.

Abstract: A code mechanism is provided in an integrated circuit for identifying the integrated circuit such as by serial number or for use in enabling the circuit and equipment housing the circuit. Fuses, antifuses, and programmable field effect transistors are used in an array for establishing a code. The code can be established by loading a register through the array and then reading the register. Alternatively,the contents of the register can be compared with a code provided by a user to enable the circuit. In another embodiment, a ROM is loaded with a table of encryption keys, and a user addresses the ROM by loading an address in a register or in a RAM.

Abstract: A decoding method is used for a ROM matrix having silicon controlled rectifier memory units. In the memory units a voltage is applied to the emitter terminal and the base terminal of the first transistor of a silicon controlled rectifier unit so that the silicon controlled rectifier memory unit is operational. Current flows via the emitter terminal of the second transistor of the silicon controlled rectifier unit to the common electrode and can be detected. Decoding comprises selecting a memory unit for a read operation by applying a first voltage to the triggering word line electrode, that is electrically coupled to the selected memory unit, while applying a second voltage which is bigger than the first voltage to the remaining triggering word line electrodes.

Abstract: A semiconductor memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against the noises. In order to accomplish this a control electrode is formed to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size.

Abstract: A semiconductor memory device in which a plurality of data lines of a memory array comprising storage transistors arranged in a matrix form as those having a high or low threshold voltage according to stored data are divided into a plurality of blocks, and sense amplifiers for performing amplification operations dispersedly in time are used to amplify signals. Moreover, a first and a second group of sense amplifiers corresponding to odd- and even-numbered adjoining data lines are arranged so that while the output signals of one group of sense amplifiers are output, word lines are switched, and the other group of sense amplifiers are caused to perform the operation of amplifying the signals read from the memory cells corresponding to the word lines thus switched, respectively.

Abstract: An identification section fabricated onto a semiconductor integrated circuit includes structure for storing die-specific information that characterizes that particular integrated circuit. The identification section may also include structure for reading the die-specific information from the structure for storing. In addition or otherwise, the identification section may also include structure for programming the die-specific information into the structure for storing.

Abstract: A method and system for programming vROM programmable memories using antifuses fabricated from undoped amorphous silicon as a high resistance link or layer between two metal layers. Whenever a programming voltage higher than a normal operating voltage is applied across the link between the two metal layers, the resistance of the link is reduced by transforming the insulating amorphous silicon into conducting polysilicon. This causes a closed or conductive link to be formed between the two metal layers. In the programming of the vROM, current is actively pumped to the link; and a current measurement or check is made prior to the application of the programming voltage to determine whether the link already has been programmed. Immediately following the application of the programming voltage, the current through the link again is checked to determine proper programming of the link.

Abstract: An efficient technique or providing ROM memory on a microprocessor local bus is described whereby a ROM and all necessary address decoding and control circuitry is incorporated in a single integrated circuit. By doing this, only one chip is required to add ROM to a microprocessor local bus, saving considerable space and power over discrete implementations. The ROM is implemented in a wide memory format, matching the bus width of the microprocessor to which it is connected. This permits full-speed access to the local bus ROM, and eliminates any need for such techniques as ROM "shadowing".

Abstract: An integrated device with electrically programmable and erasable memory cells, including one time programmable (OTP) read-only memory cells. A matrix of user memory cells is added at least one row of OTP cells sharing the column selection lines with the other cells. Similarly to the other cells, these have a selection terminal connected to a row selection line. The source terminals of such OTP cells in the row are connected to the device ground through a common selection transistor which is driven from the same row selection line.

Abstract: A system and method for isolating one or more causes of wafer misprocessing. A list of interesting queries (10) is generated. During wafer processing (15), processing parameters are measured (20) and a wafer tracking database (25) is created. The list of queries (10) may be filtered (30) before the queries are tested for interestingness. Interestingness is determined by outlier calculation (35) and trend analysis (40) on data stored in the wafer tracking database (25). Queries found to be interesting are displayed (50).

Abstract: An efficient technique for providing ROM memory on a microprocessor local bus is described whereby a ROM and all necessary address decoding and control circuitry is incorporated in a single integrated circuit. By doing this, only one chip is required to add ROM to a microprocessor local bus, saving considerable space and power over discrete implementations. The ROM is implemented in a wide memory format, matching the bus width of the microprocessor to which it is connected. This permits full-speed access to the local bus ROM, and eliminates any need for such techniques as ROM "shadowing".