Abstract: An SRAM array with a dummy cell row structure in which the SRAM array is divided into segments isolated by a row pattern of dummy cells. The dummy cell structure provides a continuous cell array at the lower cell patterning levels. The SRAM array includes a first and second array block each including an SRAM cell having a first layout configuration, one or more of the dummy cells having a second layout configuration arranged along the row pattern associated with a wordline of the SRAM array, a first power supply voltage line connected to the first array block, and a second different power supply voltage line connected to the second array block. The first and second power supply voltage lines of the array blocks are further connected to the one or more dummy cells.

Abstract: The non-volatile, programmable fuse apparatus has a pair of p-channel transistors coupled in a latch configuration. A supercell is coupled between each transistor and ground. Each supercell is comprised of a plurality of non-volatile memory cells that are each programmed substantially similarly for each supercell. The supercells are programmed in a complementary fashion. The output state of the apparatus is determined by the state of the supercell to which the output is coupled.

Abstract: The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.

Abstract: Each nonvolatile memory cell transistor has such directivities that a current flows only from the drain to the source and that charge is exchangeable only at the source. The source of one of a pair of memory cell transistors connected to each word line is connected to the drain of the other memory cell transistor, and the drain of the one memory cell transistor is connected to the source of the other. During a data rewrite operation, reverse voltages are applied to the sources and drains of the pair of memory cell transistors. Because of the directivities of each memory cell transistor, charge is exchanged with a charge accumulation layer only in the source region. This makes the data rewritable in only one of the pair of memory cell transistors. As a result, data is rewritable on a memory cell basis without increasing the memory cell size.

Abstract: Non-volatile memory elements having a high programming speed and a reduced constant voltage requirement for data storage. Each memory cell of a non-volatile SRAM includes an SRAM unit and a non-volatile memory unit. When power is off, the data levels of data nodes of the SRAM unit are programmed into a corresponding non-volatile memory element through a pass transistor connected to the data node. When the power is on, the data levels programmed into the non-volatile memory elements are recalled to the corresponding data nodes through the pass transistors, and then the programmed non-volatile memory element is erased. The non-volatile memory element has an oxide stack including a tunnel oxide film, a storage oxide film, and a blocking oxide film. A potential well where the SRAM unit is formed is isolated from a potential well where the non-volatile memory unit is formed. Bias voltages are applied during program, recall and erase modes to the potential well where the non-volatile memory unit is formed.

Abstract: In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored such in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks.

Abstract: A memory cell includes a volatile circuit operable to store first data, and a nonvolatile circuit coupled to the volatile circuit and operable to store second data. The volatile circuit is operable to program the nonvolatile circuit with the first data, and the nonvolatile circuit is operable to program the volatile circuit with the second data.

Abstract: An exemplary cascode amplifier circuit comprises a first intrinsic FET, a second intrinsic FET, a third intrinsic FET, and a fourth FET. The first intrinsic FET has a source connected to a target memory cell via a bit line and a drain connected to a first node. The second intrinsic FET has a gate connected to the source of the first intrinsic FET and a source connected to a reference voltage. The second intrinsic FET also has a drain connected at a second node to a gate of the first intrinsic FET. The third intrinsic FET has a source connected to the first node and a gate connected to a supply voltage, and further provides a load across the supply voltage and the first node. The fourth FET has a source connected to the second node and a drain connected to the supply voltage, the fourth FET having a gate connected to an input control voltage.

Abstract: A semiconductor memory system comprising a memory matrix including a plurality of memory cells arranged in rows and columns and connected to a plurality of column lines, each memory cell of the same column having a first and a second terminal connected to a first and a second column line respectively. Furthermore, the memory system comprises a first and a second conduction line which can be connected to said first and second column lines, and generating means provided with at least a first and a second output line, making available a first and a second reading/writing voltage to said first and second terminal respectively. The memory system also comprises at least a first and a second selection transistor connected to the same command line and having corresponding operative terminals connected directly to the first and to the second output lines respectively and corresponding cell terminals connected directly to the first and to the second conduction lines respectively.

Abstract: Non-volatile SRAMs having an improved recall characteristic are disclosed. An illustrated non-volatile SRAM includes a plurality of unit memory cells arranged in an array. Each of the plurality of unit memory cells comprises a SRAM unit and a non-volatile circuit. The non-volatile circuit includes storage transistors, SONOS transistors connected to the storage transistors, and recall transistors connected to the SONOS transistors. The thickness of the gate insulation films of the recall transistors is thinner than the thickness of the gate insulation films of the storage transistors.

Abstract: Various apparatuses and methods are shown in which an integrated circuit includes a dual-polarity non-volatile memory cell and a test circuit. The test circuit has a bias voltage generator and a first switch. The bias voltage generator couples to the dual-polarity non-volatile memory cell via the first switch.

Abstract: A memory may include a phase change memory element and series connected first and second selection devices. The second selection device may have a higher resistance and a larger threshold voltage than the first selection device. In one embodiment, the first selection device may have a threshold voltage substantially equal to its holding voltage. In some embodiments, the selection devices and the memory element may be made of chalcogenide. In some embodiments, the selection devices may be made of non-programmable chalcogenide. The selection device with the higher threshold voltage may contribute lower leakage to the combination, but may also exhibit increased snapback. This increased snapback may be counteracted by the selection device with the lower threshold voltage, resulting in a combination with low leakage and high performance in some embodiments.

Abstract: In accordance with the present invention, a memory cell includes a pair of non-volatile devices and a pair of DRAM cells each associated with a different one of the non-volatile devices. Each DRAM cell further includes an MOS transistor a capacitor. The DRAM cells and their associated non-volatile devices operate differentially and when programmed store and supply complementary data. The non-volatile devices are erased prior to being programmed. Programming of the non-volatile devices may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the DRAM are loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile devices are restored in the DRAM cells. The differential reading and wring of data reduces over-erase of the non-volatile devices.

Abstract: A hardening system includes a data storage device having a data input, a clock input, a data node Q, and a data complement node QN. The data storage device provides drive to the data node Q and the data complement node QN. A hardening circuit includes first, second, third, fourth, and fifth transistor circuits. The first and second transistor circuits form a first node therebetween, and the first transistor circuit prevents the data node Q from changing states in the presence of radiation. The third and fourth transistor circuits form a second node therebetween, and the third transistor circuit prevents the data complement node QN from changing states in the presence of radiation. The first node is coupled to the third transistor circuit, and the second node is coupled to the first transistor circuit. The fifth transistor circuit prevents the first and second nodes from floating.

Abstract: A circuit architecture and a method perform a page programming in non-volatile memory electronic devices equipped with a memory cell matrix and an SPI serial communication interface, as well as circuit portions associated to the cell matrix and responsible for the addressing, decoding, reading, writing and erasing of the memory cell content. Advantageously, a buffer memory bank is provided to store and output data during the page programming in the pseudo-serial mode through the interface. Data latching is performed one bit at a time and the following outputting occurs instead with at least two bytes at a time.

Abstract: The non-volatile, programmable fuse apparatus has a pair of p-channel transistors coupled in a latch configuration. A supercell is coupled between each transistor and ground. Each supercell is comprised of a plurality of non-volatile memory cells that are each programmed substantially similarly for each supercell. The supercells are programmed in a complementary fashion. The output state of the apparatus is determined by the state of the supercell to which the output is coupled.

Abstract: An SRAM memory cell includes first and second inverters (14, 16) interconnected between first and second data nodes. Each inverter is formed from complementary MOS transistors (18, 20, 18′, 20′) connected in series between a DC voltage supply source and a grounding circuit (22). A circuit (28, 30) programs the MOS transistors by causing an irreversible degradation of a gate oxide layer of at least some of the transistors (18, 18′).

Abstract: A nonvolatile semiconductor memory device of the present invention includes: a plurality of memory blocks each including a memory array including a plurality of memory cells, a plurality of word lines and bit lines provided so as to cross each other for selecting the memory cell, a row decoder for selecting the word line according to an externally-input row address signal, a column decoder for selecting the bit line according to an externally-input column address signal; and at least one internal voltage generation circuit for applying a voltage required for performing data write/erase operations on the memory array, a plurality of first switch circuits are provided such that each first switch circuit is provided between the at least one internal voltage generation circuit and the row decoder or the column decoder, and a switch selection circuit is provided for selectively operating the plurality of first switch circuits.

Abstract: A random access memory cell has first and second inverters each having an input and an output. The input of the first inverter is coupled to the output of the second inverter by a Schottky-diode-free MOSFET. The input of the second inverter is coupled to the output of the first inverter.

Abstract: The present memory includes a plurality of transistors laid out in a number of rows and columns. First and second series-connected transistors are included in a first column, and are connected between first and second bit lines and are respectively associated with first and second word lines. A region between the series-connected first and second transistors is connected to a first bit line. Third and fourth series-connected transistors are included in a second column, and are connected between the second bit line and a third bit line and are respectively associated with third and fourth word lines. A region between the series-connected third and fourth transistors is connected to a second bit line. The first, second, third and fourth transistors are respective parts of first, second, third and fourth rows of transistors.

Abstract: A conventional volatile SRAM cell is modified into a non-volatile, read only memory cell. This permits a device whose design currently includes on-chip SRAM, but no ROM, to have non-volatile, read only memory with minimal redesign and development effort. The modifications made to the already present SRAM are fairly minimal resulting in much of the modified SRAM being largely unchanged. Because existing on chip, volatile memory is used largely as is with fairly minimal modifications to make the memory non-volatile, the time-to-market for such a device is much shorter than it would have been had the device been redesigned to include conventional ROM.

Abstract: A high-voltage semiconductor device includes: a drain region; a metal electrode electrically connected to the drain region; and electrically floating plate electrodes formed on a field insulating film over a semiconductor regionm. Parts of the metal electrodes are extended onto the interlevel dielectric film and located over the respective plate electrodes. Each part of the metal electrode is capacitively coupled to associated one of the plate electrodes.

Abstract: A static memory cell having reduced susceptibility to soft error events, wherein data storage nodes are hardened by way of junction isolation. The memory cell is comprised of a pair of cross-coupled inverters. A first inverter is formed with a first N-channel Metal Oxide Semiconductor (NMOS) device and a first P-channel MOS (PMOS) device, with a first isolation device disposed therebetween. A second inverter is cross-coupled to the first inverter to form a pair of data storage nodes therein. The second inverter is also provided with a second isolation device disposed between its pair of NMOS and PMOS devices. A first data storage node is formed at a coupling between the first PMOS device and the first isolation device and a second data storage node is formed at a coupling between the second PMOS device and the second isolation device.

Abstract: An OTP bit cell includes a latch circuit of cross-coupled inverters. A floating gate PMOS transistor is inserted in each of the inverters. One or the other of the floating gate PMOS transistors is programmed through an included programming circuit so that a differential output of the latch circuit provides a corresponding logic state that is the same each time when read. To program a selected floating gate PMOS transistor, appropriate write inputs are applied to the programming circuit while a high reference voltage to the OTP bit cell is raised to a level such that the selected floating gate PMOS transistor is programmed.

Abstract: The nonvolatile memory includes a nonvolatile memory circuit that possesses a pair of series circuits of load elements and nonvolatile memory transistors, which are connected in a static latch configuration, a program control circuit that writes information into the nonvolatile memory circuit, a volatile latch circuit that latches information read from the nonvolatile memory circuit, and a readout control circuit that makes the volatile latch circuit latch the information read from the nonvolatile memory circuit. In response to the instruction of the readout operation, the readout control circuit supplies the operating voltage for the static latch operation to the nonvolatile memory circuit, and stops the supply of the operating voltage, after completing the latch operation.

Abstract: Architecture, circuitry and method are provided for a ternary content addressable memory (TCAM), and use thereof. Each TCAM cell is relatively small in size. If the TCAM cell is called upon to store voltage values indefinitely, provided power is retained on the cell, the TCAM cell employs no more than 16 transistors. Additional savings in size is achieved by using a single common conductor (or dual common conductors in a differential arrangement) to suffice as both the bit line and compare line. The common bit line and compare line connects to not only the X memory cell, but also the Y memory cell and the compare circuit of the TCAM cell. The compare circuit can either be activated or deactivated. During a compare operation, the compare circuit is selectively activated by placing a ground supply upon a match line enable conductor. The ground supply is imputed upon the match line whenever a mismatch occurs to designate that mismatch.

Abstract: A semiconductor storage device conducts a late-write operation. The semiconductor storage device comprises: a memory core circuit storing data; a data latch circuit storing preceding data corresponding to a preceding write-operation; an address compare circuit comparing a preceding address corresponding to the preceding write-operation and a present address corresponding to a present read-operation so as to determine whether the preceding address and the present address match each other; and a control circuit. The control circuit controls a test read-operation to read data from the memory core circuit regardless of whether the preceding address and the present address match each other.

Abstract: A ferroelectric memory devices including a reference programming portion for regulating and outputting voltages of reference level control signals by using a programmable register, which programs the level of output signal with externally applied signals and maintains the program results without power, to control on/off of switches regulating capacitance of capacitors connected to driving power; and a reference voltage generating portion for outputting a reference voltage according to the reference level control signal. A method for programming the ferroelectric memory device is also disclosed which includes the steps of: decoding a signal inputted in a signal input unit; activating a program mode operating signal corresponding to the program mode and deactivating the signal input unit; and performing the program mode in response to the program mode operating signal.

Abstract: A non-volatile latch circuit includes a first, volatile information-storage element; a second, non-volatile information-storage element electrically programmable and associated with the first element; first circuit means activatable for operatively coupling the second element to the first element, the first circuit means being activated for loading into the first element an information stored in the second element. The circuit additionally includes second circuit means associated with the first element for setting the first element in a select state; third circuit means associated with the second element and driven by the first element for selectively enabling the programming of the second element depending on the state of the first element.

Abstract: A semiconductor memory device includes a memory cell array, latch circuits, first to third circuits and a current control circuit. The memory cell array includes electrically rewritable nonvolatile memory cells arranged therein. The latch circuits temporarily hold data read out from the memory cell array. The first circuit generates a first current which varies in proportion to “1” or “0” of binary logical data of one end of the latch circuits. The second circuit generates a predetermined second current. The current control circuit is connected to the first and second circuits, and configured to determined absolute values of the first and second currents. The third circuit is configured to compare the first and second currents. The number of binary logical data of “1” or “0” of one end of the latch circuits is detected based on the result of comparison between the first and second currents.

Abstract: A three-transistor SRAM device are disclosed. The SRAM device has an NMOS with its source connected to a first voltage source and its substrate connected to a second voltage source. The source of the NMOS is connected either a constant voltage source or a variable voltage source. An PMOS and the NMOS form a common node A. The drain of the NPMOS is connected to the source of the PMOS to form a common node B. A resister is connected between the nodes A and B. Another NMOS is connected between the node B and a bit line. The gate of this NMOS is controlled by a word line. A capacitor type amplifier may be further connected to the node B to form the data latch of the SRAM.

Abstract: In order to preclude unauthorized access to a memory, for example after testing, two EEPROM cells are programmed and their outputs are subjected to a logic operation, the result being stored in a memory element and being evaluated. The cells are arranged in such a manner that they are programmed together in anti-parallel. A well-defined initial condition before a test is established by changing the control gate voltage, which causes both cells to be set to an initial state with similar output signals. The initial state is stored in the storage element and is evaluated. It is not until the initial condition has been established that the EEPROM cells are programmed and the correct programming is tested.

Abstract: The nonvolatile memory includes a nonvolatile memory circuit that possesses a pair of series circuits of load elements and nonvolatile memory transistors, which are connected in a static latch configuration, a program control circuit that writes information into the nonvolatile memory circuit, a volatile latch circuit that latches information read from the nonvolatile memory circuit, and a readout control circuit that makes the volatile latch circuit latch the information read from the nonvolatile memory circuit. In response to the instruction of the readout operation, the readout control circuit supplies the operating voltage for the static latch operation to the nonvolatile memory circuit, and stops the supply of the operating voltage, after completing the latch operation.

Abstract: An apparatus for storing data of a device, in particular of a motor vehicle, which is to be monitored, in which apparatus the data are preferably stored by means of a control unit in a memory unit. In an apparatus which permits a plurality of data which change continuously during the service life of the motor vehicle to be stored in an operationally reliable way and with a high processing speed, the fixed data and the continuously updated data of the apparatus which is to be monitored are stored in the memory unit 15 which contains the open-loop and/or closed-loop control processes.

Abstract: A semiconductor memory device includes a memory cell array, a plurality of latch circuits, first circuit, second circuit and third circuit. The memory cell array has electrically rewritable nonvolatile memory cells arranged therein. The plurality of latch circuits temporarily hold data read out from the memory cell array. The first circuit is configured to generate a first current varying in proportion to “1” or “0” of binary logical data of one end of the plurality of latch circuits. The second circuit is configured to generate a second preset current. The third circuit is configured to compare the first current with the second current. The number of “1” or “0” of binary logical data of one end of the plurality of latch circuits is detected based on the result of comparison between the first current and the second current.

Abstract: According to one embodiment, a nonvolatile circuit (100) can include a volatile circuit portion (102) and a nonvolatile circuit portion (104). A vole portion (102) may have a first data node (114) and a second data node (116). A nonvolatile circuit portion (104) may include a nonvolatile device (128) that is connected to a first data node (114) by a recall device (124) and connected to a second data node (116) by store device (126). A recall device (124) may be enabled to recall the volatile circuit portion (102) to a particular state. A store device (126) may be enabled to program a nonvolatile device (128). Store and recall devices (126 and 124) can enable a recall operation to follow a store operation that does not invert data at first and second data nodes (114 and 116). A control device (122) can be included that enables margin testing of a nonvolatile device (128).

Abstract: A memory device comprises at least one electrically erasable and programmable non-volatile memory cell, a bistable flip-flop, connected in parallel with the memory cell, and a switching device, connected to the flip-flop, to connect at least one data input line to one of the status lines (QP, QN) of the flip-flop, in dependence on a switching signal.

Abstract: A non-volatile latch comprises first and second read/write bias nodes and first and second a complementary output nodes. First and second first conductivity type MOS transistors have sources coupled to a first voltage potential. A drain of the first MOS transistor is coupled to the first complementary output node and a drain of the second MOS transistor is coupled to the second complementary output node. Each of the first and second MOS transistors have a gate cross coupled to the drain of the other one of the first and second MOS transistor. A source of a third MOS transistor is coupled to the first read/write bias node and a source of a fourth MOS transistor is coupled to the second read/write bias node. A drain of the third MOS transistor is coupled to the first complementary output node and a drain of the fourth MOS transistor is coupled to the second complementary output node.

Abstract: A bistable non-volatile latch circuit adapted to store a non-volatile binary data state during a program operation, and to assume one of two stable states in response to a recall operation that correspond uniquely to the data state has first and second circuit sections. The first circuit section has a first non-volatile current path with means to set the impedance of the first current path in a non-volatile manner. A first end of the first current path is connected to provide a logic output signal, which represents a binary logic state depending on a voltage applied to the a first signal input node. The set/reset signal to the first current path varies between at least the power source voltage and a program voltage that is negative with respect to the power source voltage. A second circuit section generates an output voltage on a second output node that represents a binary logic state opposite from the output states of the first circuit section.

Abstract: A non-volatile memory cell comprising a first transistor and a second transistor. The first transistor may be configured to receive an input and a first voltage. The second transistor may be configured to receive said input and a second voltage. The first and second transistors are generally coupled to an output.

Abstract: An improved approach to examining program strength of non-volatile latches is disclosed. The program strength is able to be evaluated by inferring floating gate charge of memory elements of the non-volatile latches as indicated by current characteristics of the memory elements. Access to the program charge or the internal currents is facilitated by monitoring circuitry provided integral with the non-volatile latches.

Abstract: A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, and a set of isolation transistors. The set of isolation transistors is coupled to the first set of cross-coupled transistors such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.

Abstract: A data holding apparatus that is capable of a high speed response and that holds data even when the power source is off. Each memory cell of the data holding apparatus includes first and second transistors, where at least the first transistor is a ferroelectric transistor having a floating gate over the gate insulating film, and a ferroelectric layer between the gate insulating layer and the control gate. The control gate of the first transistor is connected to the drain of the second transistor and the control gate of the second transistor is connected to the drain of the first transistor to provide a positive feedback to each other, and the memory cell holds data defined by the ON or OFF states of the first and second transistors. The memory cell further includes data lines carrying data signals to be written into or read from the memory cell.

Abstract: A memory may include sectional columns so that groups of cells on the same column but coupled to different word lines may be selectively accessed. As a result, only a portion of the cells of a given column is activated at any given time. The remainder of the column may be decoupled, thereby reducing the need to charge up or discharge the rest of the column. Because only a smaller portion of the column is charged or discharged, the lower capacitance associated with a lower number of cells may result in a speed and power consumption improvement.

Abstract: A combination non-volatile latch circuit has a volatile latch circuit having a bit signal and an inverse bit signal. A first and a second non-volatile cell of the split gate floating gate type having a first terminal, a second terminal and a control gate is supplied. A first switch supplies the bit signal to the first terminal of the first cell and the inverse bit signal to the first terminal of the second cell. A second switch supplies the bit signal to the first terminal of the second cell and the inverse bit signal to the first terminal of the first cell. A first voltage can be supplied to the second terminal of the first and second cells and a second voltage supplies a voltage to the control gate of the first and second cells. In this manner, the latch can be operated independently of the non-volatile memory cells, the status of the latch can be restored by the status of the non-volatile memory cells, and the contents of the latch can be stored in the non-volatile memory cells.

Abstract: An electrically erasable memory device includes a substrate and a plurality of single poly layer memory cells in the substrate. Each single poly layer memory cell includes a first MOS transistor in a first region in the substrate and spaced apart source and drain regions. Each single poly layer memory cell further includes a capacitor having a first electrode overlying a second region in the substrate and an insulating layer therebetween, and a third region in the second region defining a second electrode. An erasing circuit selectively erases the single poly layer memory cell by supplying a first voltage reference of a first polarity to the spaced apart source and drain regions, a second voltage reference of a second polarity to the first region, and a third voltage reference of the second polarity to the second electrode of the capacitor.