Abstract: A memory device may include a plurality of memory cells each having elements with at least one solid ion conductor programmable between at least two different impedance states for at least two different data retention times, the plurality of memory cells being dividable into a plurality of portions, each portion being separately configurable for one of the data retention times.

Abstract: A memory device having a plurality of storage locations disposed along a plurality of generally parallel lines includes, connected to the lines, a decoder circuit for selecting one line, and, connected to each line, a line-disabling circuit for selectively preventing the line from being energized during line selection.

Abstract: A system and method to read and write data at a memory cell that includes multiple non-volatile memories is disclosed. In a particular embodiment, a memory device is disclosed that includes a plurality of memory cells, where at least one of the memory cells comprises a first non-volatile memory including a first resistive memory element and a second multi-port non-volatile memory including a second resistive memory element.

Abstract: A sense amplifier scheme for SRAM is disclosed. In accordance with one of the embodiments of the present application, a sense amplifier circuit includes a bit line, a sense amplifier output, a power supply node having a power supply voltage, a keeper circuit including an NMOS transistor, and a noise threshold control circuit. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and maintains a voltage level of the bit line and the noise threshold control circuit lowers a trip point of the sense amplifier output.

Abstract: A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell.

Abstract: The present invention relates to a resistance variable memory device, and more particularly, to a resistance variable memory device capable of preventing an effect of coupling noise. The resistance variable memory device includes: a memory cell connected to a bit line; a precharge circuit precharging the bit line in response to a precharge signal; a bias circuit providing a bias voltage to the bit line in response to a bias signal; and a control logic controlling the precharge signal and the bias signal. The control logic provides the bias signal to the bias circuit at a precharge interval. Accordingly, the resistance variable memory device according to the present invention can prevent an effect coupling noise.

Abstract: A computation processing device executes logic computation based upon input data X(t) and data X(t?1) stored in memory. A ferroelectric capacitor includes a first terminal and a second terminal, and provides a function as memory. A bit line driver switches the voltage to be applied to the first terminal or the second terminal of the ferroelectric capacitor. A sense amplifier outputs a computation result according to the voltage that occurs at either of the first terminal and the second terminal of the ferroelectric capacitor. For example, the bit line driver switches the direction of the voltage to be applied to the ferroelectric capacitor according to the input data X(t).

Abstract: A semiconductor memory device to an exemplary aspect of the present invention includes a plurality of memory cells, a plurality of word lines, a plurality of bit line pairs, a plurality of column selectors, a common signal line pair including one common line commonly connected to one of each of the plurality of bit line pairs, and the other common line commonly connected to the other of each of the plurality of bit line pairs, a sense amplifier amplifying the potential difference of the common signal line pair, and a plurality of capacitance adding circuits that balance with parasitic capacitances of the column selectors which are not selected, the capacitance adding circuits being provided respectively between the one of each of the bit line pairs and the other common line and between the other of each of the bit line pairs and the one common line.

Abstract: Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of the inversion state of the data in the first memory. The original data in the first memory can be reconstructed performing a logical exclusive-OR operation between the data in the first memory and the data in the second memory.

Abstract: Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and memory device configured to perform operations in synchronization with transitions of an externally provided clock signal. A selective edge phase mixing unit for the memory device may include a first logic gate that receives the clock signal at an input port and receives first control signals, and pull-up circuits in communication with an output of the first logic gate and first control signals. A second logic gate receives the clock signal at the input port and receives second control signals. Pull-down circuits are coupled to the second logic gate and the second control signals, wherein the pull-up circuits and the pull-down circuits are coupled to the output port to provide a duty cycle corrected clock signal to the memory device. Additional apparatus, systems, and methods are disclosed.

Abstract: Memory elements are provided that exhibit immunity to soft error upsets. The memory elements may have cross-coupled inverters. The inverters may be implemented using programmable Schmitt triggers. The memory elements may be locked and unlocked by providing appropriate power supply voltages to the Schmitt trigger. The memory elements may each have four inverter-like transistor pairs that form a bistable element, at least one address transistor, and at least one write enable transistor. The write enable transistor may bridge two of the four nodes. The memory elements may be locked and unlocked by turning the write enable transistor on and off. When a memory element is unlocked, the memory element is less resistant to changes in state, thereby facilitating write operations. When the memory element is locked, the memory element may exhibit enhanced immunity to soft error upsets.

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

Abstract: A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first sub-memory-cell area and form a data transfer path by being connected with the second bit line and a sensing and amplifying unit configured to sense and amplify data inputted through the additional bit line and the first bit line.

Abstract: A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.

Abstract: In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the bit lines and stores write data. The data storage circuit includes at least one static latch circuit and a plurality of dynamic latch circuits when setting 2k threshold voltages (k is a natural number equal to 3 or more) in each memory cell in the memory cell array. A control circuit refreshes data by moving the data in one of the plurality of dynamic latch circuits to the static latch circuit and further moving the data in the static latch circuit to one of the plurality of dynamic latch circuits.

Abstract: In a memory device, a bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.

Abstract: To include a first memory cell array area and a second memory cell array area, a peripheral circuit area arranged between these memory cell array areas, a first pad row arranged between the first memory cell array area and the peripheral circuit area, and a second pad row arranged between the second memory cell array area and the peripheral circuit area. No peripheral circuit is arranged substantially between the first memory cell array area and the first pad row as well as between the second memory cell array area and the second pad row. With this arrangement, a memory cell array area and a predetermined pad can be connected within a shorter distance by using a wiring formed in an upper layer that has a lower electrical resistance, and a power potential can be stably supplied to the memory cell array area.

Abstract: Systems and methods for managing a write operation are described. The systems include a logic element (LE) including an N-input look-up table (LUT) having a configurable random access memory (CRAM) including 2N memory cells. The systems further include a write address decoder coupled to the LE and a write address hard logic register that stores an address of one of the memory cells. N is an integer. The hard logic register removes a dependency of a timing relationship between a write address launch and a write to the CRAM on a design of an integrated circuit.

Abstract: A comparator determines the fidelity of a response vector received from a memory under test. The comparator includes a first logic gate configured to output a first value that is the logical OR of a first proper subset of bits of the response vector. A second logic gate is configured to output a second value that is the logical NAND of the proper subset of bits. A first multiplexer is configured to select between the first and second values based on the value of a first bit of a check vector corresponding to the response vector.

Abstract: A semiconductor memory device includes a memory cell array, a page buffer, a data line pair, a differential amplifier and a precharger. The memory cell array includes a plurality of pages in which a plurality of memory cells are arranged. The page buffer is formed adjacent to the memory cell array, and includes a plurality of sense amplifiers configured to temporarily hold page data read from the memory cells in the page. The data line pair is arranged in the page buffer and is connected to the sense amplifiers. The differential amplifier is configured to amplify a potential difference between lines of the data line pair. The precharger is configured to precharge the data line pair to a predetermined potential. At least one of the differential amplifier and the precharger is formed in the page buffer, and the at least one circuit is electrically connected to the data line pair.

Abstract: The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period.

Abstract: A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: A method of generating a test pattern of a memory chip includes generating and outputting a pattern enabling signal according to a first pattern signal and a second pattern signal, generating and outputting a first pre-input-output signal and a second pre-input-output signal according to a memory bank signal, a section signal, and the pattern enabling signal, executing an exclusive-OR logic operation on a third input-output signal and the second pattern signal to generate and output a first enabling signal, generating and outputting a first input-output signal and a second input-output signal according to the first enabling signal, the first pre-input-output signal and the second pre-input-output signal, and writing a predetermined logic voltage to each memory cell of the memory chip according to the first input-output signal and the second input-output signal.

Abstract: An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read commands are issued once per burst access eliminating toggling Read control line at cycle frequency. Control line transition terminates access and initializes another burst access.

Abstract: A system LSI (100) having a logic circuit (104) and a plurality of SRAM macros (103) includes a power supply circuit (102) configured to receive a voltage (VDDP) supplied from the outside of the system LSI (100), and to generate a stabilized voltage (VDDM) lower than the voltage (VDDP). An SRAM memory cell (103a) of each of the plurality of SRAM macros (103) is supplied with the voltage (VDDM) generated by the power supply circuit (102), and an SRAM logic circuit (103b) of each of the plurality of SRAM macros (103) is supplied with a voltage (VDD) supplied from the outside. In addition, the logic circuit (104) is supplied with the voltage (VDD) from the outside.

Abstract: Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of vertically stacked memory planes. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power.

Abstract: A storage device includes a control unit, a first voltage supply unit for supplying a first working voltage to the control unit, N memory units, a second voltage supply unit for supplying a second working voltage to each memory unit, a logic gate, a first voltage detecting unit and a second voltage detecting unit. Once the first voltage detecting unit detects that the first working voltage of the control unit is abnormal, the logic gate outputs a first write protect signal to notify the control unit and control the memory units to enter a write protect mode. Once the second voltage detecting unit detects that the second working voltage of one or more memory units is abnormal, the logic gate outputs a second write protect signal to notify the control unit and control the one or more memory units to enter the write protect mode.

Abstract: In a memory cell, the drive current capabilities of the transistors may be adjusted by locally providing an increased gate dielectric thickness and/or gate length of one or more of the transistors of the memory cell. That is, the gate length and/or the gate dielectric thickness may vary along the transistor width direction, thereby providing an efficient mechanism for adjusting the effective drive current capability while at the same time allowing the usage of a simplified geometry of the active region, which may result in enhanced production yield due to enhanced process uniformity. In particular, the probability of creating short circuits caused by nickel silicide portions may be reduced.

Abstract: Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: A memory module having a high data processing rate and high capacity is provided. The memory module may include a memory chip, a controller controlling an operation of the memory chip, an optical detector converting an external input signal into an internal input signal to transmit the converted signal to the controller, and an optical generator converting an internal output signal received from the controller into an external output signal. The optical detector converts an external input optical signal into an internal input signal to transmit the converted signal to the controller. The optical generator converts an internal output signal received from the controller into an external output optical signal.

Abstract: A synchronous type semiconductor storage device includes an array unit which includes a cell array and sense amplifiers. The synchronous type semiconductor storage device includes a read/write pulse generator which generates a read pulse signal and a write pulse signal according to a clock signal, the clock signal defining one cycle time of a read operation and a write operation with respect to the array unit as one cycle. The synchronous type semiconductor storage device includes a secondary amplifier which is activated according to the read pulse signal to read out data stored in the sense amplifiers through the read/write line. The synchronous type semiconductor storage device includes a write driver which is activated according to the write pulse signal to write data in the sense amplifiers through the read/write line.

Abstract: A data storage system includes a plurality of memory devices for storing data. The plurality of memory devices is classified into a plurality of groups of memory devices. A control circuit is adapted to provide concurrent memory access operations to the plurality of memory devices. Each of a plurality of data channels is configured to provide a data path between the control circuit and one of the groups of memory devices. A plurality of switches is configured to connect and disconnect one of the memory devices in a select one of the groups of memory devices to one of the plurality of data channels and concurrently connect and disconnect another of the memory devices in the select group of memory devices to a different one of the plurality of data channels.

Abstract: A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary lower storage nodes and complementary upper storage nodes. The upper storage nodes act to limit feedback between the lower storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the lower storage nodes act to limit feedback between the upper storage nodes with the same effect. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.

Abstract: A semiconductor memory device includes: a first strobe signal generation unit configured to generate a first rising strobe signal in response to a rising DLL clock signal; a second strobe signal generation unit configured to generate a second rising strobe signal in response to a falling DLL clock signal, the second rising strobe signal having an opposite phase to the first rising strobe signal and being activated at the same timing as the first rising strobe signal; a third strobe signal generation unit configured to generate a first falling strobe signal in response to the falling DLL clock signal; and a fourth strobe signal generation unit configured to generate a second falling strobe signal in response to the rising DLL clock signal, the second falling strobe signal having an opposite phase to the first falling strobe signal and being activated at the same timing as the first falling strobe signal.

Abstract: A dual power rail word line driver for driving a word line of a memory array according to a predecode signal from a decoder powered by a first supply voltage is provided. A signal buffering unit is coupled between the word line and a node. A pull-down unit is coupled between the node and a ground. A pull-up unit is coupled between the node and a second supply voltage higher than or equal to the first supply voltage. The signal buffering unit provides a word line signal corresponding to the predecode signal to the memory array via the word line when the pull-down unit is turned on by the predecode signal and a first pulse signal and the pull-up unit is turned off by a second pulse signal. There is no level shifter on a critical timing path of the dual power rail word line driver.

Abstract: An address decoder that includes a plurality of predecoders configured to (i) receive and logically combine a clock signal and address signals and (ii) generate addresses and complementary addresses. At least one of the plurality of precoders includes a first logic gate configured to receive the clock signal and one of the address signals, and a second logic gate configured to receive the clock signal and an output of the first logic gate. The address decoder further includes a decoder configured to generate a decoder output based on the addresses and complementary addresses.

Abstract: Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.

Abstract: Disclosed herein is a semiconductor memory device which prevents the voltage of a select bit line from being reduced due to the action of coupling capacitance between the select bit line and a non-select bit line, reduces current consumption, and enables high speed reading of bit lines. The semiconductor memory device includes a plurality of memory banks, a plurality of second bit lines, a plurality of selector circuits, a voltage supply circuit. Each of the memory banks includes a plurality of first bit lines, a plurality of word lines, and a plurality of memory banks which are installed between the first bit lines and the word lines. The voltage supply circuit holds non-select bit lines of the first bit lines at the GND level at all times.

Abstract: A nonvolatile semiconductor storage device includes: a first wire and a second wire intersecting each other; a memory cell which is disposed at each intersection of the first wire and the second wire and electrically rewritable and in which a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a control circuit which applies a voltage necessary for writing of data to the first and second wires.

Abstract: Apparatus, systems, and methods are disclosed that operate to encode register bits to generate encoded bits such that, for pairs of addresses, an encoded bit to be coupled to a first address in a memory device may be exchanged with an encoded bit to be coupled to a second address in the memory device. Apparatus, systems, and methods are disclosed that operate to invert encoded bits in logic circuits in the memory device if original bits were inverted. Additional apparatus, systems, and methods are disclosed.

Abstract: A memory circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Configurations of the plurality of memory cells are determined depending on the data (“high” or “low”) which is stored in the memory cells. Data array such as a program stored in the memory circuit is analyzed in advance. In the case where “high” is the majority data, memory cells storing “high” are formed with vacant cells in which a semiconductor element is not formed.

Abstract: Memory design techniques are disclosed that provide a high compression ratio at no loss in speed. The techniques can be embodied, for instance, in heterojunction bipolar transistor (HBT) based ROMs. By embedding compression logic (e.g., XOR) functionality directly into the address decoders and sense amplifiers of the memory device, a high compression ratio is achieved at no loss in speed. For example, the logic-based compression functionality can be directly implemented into the buffers that form the address decoder as well as the sense amplifiers.

Abstract: A non-volatile memory comprising a NOR block with a first sub-block independently addressable from a second sub-block, the two sub-blocks sharing a physical substrate of the NOR block, and a first memory to store execution status information to reflect an erase status of the first sub-block. A method to selectively erase the first sub-block while inhibiting the second sub-block from erasing, comprising updating execution status information associated with the first sub-block and resuming erasing upon an occurrence of an interruption event depending on the indication of the execution status information.

Abstract: A memory error signal detecting system including a signal extracting circuit, a flip-flop, a latch circuit, and a light sign is provided. The signal extracting circuit receives a memory error signal to output a pulse signal when the memory error signal switches from a first level to a second level. When the preset end of the flip-flop receives the pulse signal, and the maintaining time of the pulse signal is maintained for a predetermine time, the flip-flop output end is set to a high voltage level. The latch circuit determines whether to output the state of the flip-flop output according to the reset signal. The light sign operates according to the state of an output end of the latch circuit. Furthermore, a computer apparatus including the memory error signal detecting system is also provided.

Abstract: A semiconductor memory device includes a first cell array including a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells. Each unit cell is provided with a PMOS transistor and a capacitor. Therefore, the semiconductor memory device efficiently operates with low voltage without any degradation of operation speed.

Abstract: A test circuit for a semiconductor memory apparatus of an open bit-line structure includes a compression part configured to, in response to test data read from a plurality of memory cells included in a test target cell mat and a compression control signal generated from a compression control signal generating part, compress the test data that are read from the memory cells that share a sense amplifier block and sequentially output compression test signals.

Abstract: Method and apparatus for initializing a system configured in a programmable logic device (PLD) is described. In some examples, the method includes: initializing memory elements in the system with first data; executing a first iteration of the system to process the first data; partially reconfiguring the PLD, during execution of the first iteration, to initialize shadow memory elements in the PLD with second data, the shadow memory elements respectively shadowing the memory elements in the system; transferring the second data from the shadow memory elements to the memory elements; and executing a second iteration of the system to process the second data.

Abstract: An internal source voltage generating circuit includes a comparison voltage generator which receives reference and internal source voltages, outputs to a second node a comparison voltage differentially amplified responsive to a voltage of a first node according to a difference between the reference and internal source voltages, and allows a driving current to flow from a third node to a fourth node. An internal voltage driver transfers an external source voltage to an output node responsive to the comparison voltage. A driving current generator increases the driving current flowing from the third node to the fourth node responsive to the voltage of the first node which rises when the internal source voltage abruptly drops. The internal source voltage generating circuit is insensitive to variation of an external source voltage, exhibits improved response time when an internal source voltage abruptly drops, and stably generates an internal source voltage.