Abstract: An electric device has a resistor including a phase change material changeable between a first phase and a second phase within a switching zone. The resistor has a first resistance when the phase change material is in the first phase and a different second resistance, when the phase change material is in the second phase. The resistor may conduct a first current. The device has a heating element that may conduct a second current for enabling a transition of the phase change material from the first to the second phase. At the position of the switching zone, the resistor is arranged as a first line and the heating element is arranged as a second line. The first and second line may conduct the first current and the second current respectively, wherein the first line and the second line cross at the position of the switching zone.

Abstract: In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.

Abstract: A tree-structure memory device including a plurality of bit lines formed on a substrate and arranged in at least one plane substantially parallel to a substrate surface and extending substantially in a first direction, a plurality of layers having a plurality of memory cells arranged in a first array, a tree structure corresponding to a plurality of layers and a bit line; and a word-line group including at least one word line crossing with the tree structure, a memory cell of the first array being located at the first intersection region in a layer of said layers.

Abstract: Apparatus and associated systems, methods and computer program products relate to using information stored in a flash memory to adjust the operating voltage supplied to the flash memory. The voltage information indicates a minimum operating voltage at which to operate the flash memory device. In general, operating a flash memory device near a minimal operating voltage may substantially minimize power consumption. The minimum operating voltage for individual flash memory devices may vary from IC to IC, by manufacturing lot, and by manufacturer. In a product, the minimum operating voltage for a particular flash memory may be determined, for example, by a controller built-in to a flash memory reporting (automatically or in response to a query) the minimum operating voltage (e.g., 2.5 V, 3.15 V) to a memory controller or microprocessor. The stored voltage information may further include information to adjust the operating voltage based on temperature.

Abstract: A circuit includes a reference data line configured to receive a reference voltage value, a memory cell, a data line coupled to the memory cell and configured to have a data logic value associated with data stored in the memory cell, a first circuit coupled to the reference data line and to the data line, and an output node configured to selectively receive the data logic value from the data line or receive the data logic value through the first circuit, based on the reference voltage value and a trip point used to trigger the first circuit to provide the data logic value through the first circuit.

Abstract: An interleaved memory circuit includes a first memory bank having a first memory cell. A first local control circuit is coupled with the first memory bank. A second memory bank includes a second memory cell. A second local control circuit is coupled with the second memory bank. An IO block is coupled with the first memory bank and the second memory bank. A global control circuit is coupled with the first and second local control circuits. An interleaving access includes a clock signal having a first cycle and a second cycle for accessing the first memory cell and the second memory cell, respectively, wherein the second cycle is capable of enabling the first local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.

Abstract: A nonvolatile semiconductor memory device includes a memory cell, latch circuits, and an arithmetic operation circuit. The memory cell stores data by a difference in threshold voltage. A read operation is performed twice or more on the memory cell under the same read conditions, and the latch circuits store a plurality of read data. The arithmetic operation circuit takes majority decision of the plurality of data stored in the latch circuits and decides data determined by the majority decision as data stored in the memory cell.

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract: A storage apparatus includes: a plurality of storage sections each of which corresponds to each of a plurality of addresses; a read pointer register that outputs a read pointer indicating an address of a storage section from which data is read; a write pointer register that outputs a write pointer indicating an address of a storage section to which data is written; a control circuit that receives first clock signals of a first frequency and second clock signals of a second frequency that is different from the first frequency, determines selection signals indicating either the first clock signals or the second clock signals on the basis of the read pointer or the write pointer for each of the plurality of storage sections, and outputs the selection signals; and selection circuits selects signals indicated by the selection signals, and outputs the selected signals.

Abstract: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

Abstract: Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory cell and as a complementary state in a second memory cell. Such a method further includes determining the state of the first memory cell using a first self-biased sensing circuit and the complementary state of the second memory cell using a second self-biased sensing circuit, and comparing in a differential manner an indication of the state of the first memory cell to a reference indication of the complementary state of the second memory cell to determine the value.

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.

Abstract: A read operation for a memory device. In response to an input address indicating to read data from a different page, a selected word line, first and second global bit lines and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit lines are kept precharged. A second cell current flowing through the selected word line is generated. A second reference current is generated. A second half page data is read based on the second cell current and the second reference current.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor, a word line, a row decoder, a sense amplifier which determines the data in the memory cell transistor via the bit line, a first bit line clamp transistor connected in series between the bit line and the sense amplifier, a second bit line clamp transistor connected in parallel to the first bit line clamp transistor and having a current driving capability higher than that of the first bit line clamp transistor, and a bit line control circuit which turns on the first bit line clamp transistor and the second bit line clamp transistor using a common gate voltage during a predetermined period from a start of charge of the bit line, and turns off only the second bit line clamp transistor when the predetermined period has elapsed.

Abstract: In a nonvolatile memory, the threshold is restored to a state before changing, without increasing number of writing undesirably. In a system including a nonvolatile memory, a random number generator, and a controller accessible to the nonvolatile memory, every time access to the nonvolatile memory is performed, the controller determines a refresh-targeted area, based on a random number generated by the random number generator. The controller is made to perform refresh control to re-write to the refresh-targeted area. By such refresh control, the threshold is restored to a state before changing, without increasing the number of writing undesirably.

Abstract: A magnetic storage device includes a plurality of MRAM memory cells connected to a data transfer line, a clamp transistor connected between the data transfer line and a reading signal line and configured to fixedly hold the potential of the data transfer line, and a reading circuit which is connected to the reading signal line and which reads the storage information of the memory cell. The reading circuit includes a hold switch connected between the reading signal line and a reading node N and configured to hold the potential of the node N, a capacitor connected between the node N and a ground end, a precharging switch connected between the node N and a power source and configured to charge the capacitor, and an inverter to which the potential of the node N is input to generate a digital signal.

Abstract: A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.

Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. Each memory cell includes a programmable transistor in series with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.

Abstract: A memory device that, in certain embodiments, includes a memory element and a digital filter. The digital filter may include a counter and a divider, where the divider is configured to divide a count from the counter by a divisor.

Abstract: A memory system according to the embodiment comprises a cell array including word lines and plural memory cells operative to store data in accordance with plural different physical levels when selected by the word lines; a register operative to hold first data input from external; and a data converter unit operative to convert the first data held in the register into second data and overwrite the second data in the area of the register for holding the first data, and further operative to convert the second data held in the register into third data to be recorded in the memory cells and overwrite the third data in the area of the register for holding the second data.

Abstract: A circuit comprises a plurality of memory cells in a row, at least one write word line, and a write support circuit coupled to the at least one write word line and to the plurality of memory cells in the row. The write support circuit includes a first current path and at least one second current path. A current path of the at least one second current path corresponds to a respective write word line of the at least one write word line. A write word line of the at least one write word line is configured to select the first current path when the plurality of memory cells in the row operates in a first mode, and to select a second current path of the at least one second current path when the plurality of memory cells in the row operates in a second mode.

Abstract: A semiconductor storage device in accordance with an exemplary aspect of the present invention includes a plurality of memory cells arranged in a matrix pattern, a plurality of word lines each provided so as to correspond to each line of the memory cells, a plurality of bit lines each connected to respective one of the memory cells, and a row selection circuit that, in a read operation, drives the word line to a set potential at a drive speed slower than a discharge speed of the bit line exhibited when the word line is raised roughly vertically to VDD.

Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes applying a negative read voltage to a selected access line of an array of memory cells, applying a pass voltage to a number of unselected access lines of the array, and sensing whether a cell coupled to the selected access line is in a conductive state in response to the applied negative read voltage.

Abstract: Systems and methods to improve reliability of sensing operations of semiconductor memory arrays requiring reading references such as MRAM or any type of phase change memory (PCM), and to improve yield of the memory arrays have been achieved. The memory array is divided into multiple parts, such as sections or segments. Reference word lines or reference bit lines or both are deployed in each of the multiple parts. Thus, the distance between an accessed line and the correspondent reference line is reduced, and hence the parasitic parameter tracking capability is enhanced significantly. Additionally spare reference word lines or spare reference bit lines can be deployed in each of the multiple parts.

Abstract: A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner.

Abstract: A nonvolatile memory device includes a data sense amplifier configured to supply a data detection current to a memory cell and detect a data detection voltage having a voltage level corresponding to a resistance of the memory cell, a first switching element configured to selectively transfer the data detection current to the memory cell, and a second switching element configured to be turned on simultaneously with the first switching element to selectively transfer the data detection current to the memory cell. The first switching element and the second switching element have a complementary voltage transfer characteristic.

Abstract: A method for writing a memory of a block interleaver determines in a bit-wise manner whether to write data into the memory. A method for reading a memory of a block interleaver combines two adjacent columns of the memory into a temporary column and reads data from the temporary column.

Abstract: Phase change based memory devices and methods for operating described herein overcome the performance limitations of slow set speeds and long recovery times commonly associated with phase change memory devices, enabling high speed operation and extending their usefulness into high speed applications typically filled by DRAM and SRAM memory.

Abstract: Memory devices and methods of operating a memory cell are disclosed in which a bitline can be grounded after charge sharing with an electrically floating ground line and before writing data to the memory cell. An electric potential of an upper power supply node of a memory cell can be lowered and an electric potential of a lower power supply node of the memory cell can be raised before writing data to the memory cell.

Abstract: A hardware arrangement for a memory bitcell, including a primary decoder for decoding a common memory address portion among a plurality of memory addresses, and a plurality of secondary decoders each for decoding an uncommon memory address portion of each of the plurality of memory addresses. The memory bitcell is configured to receive the decoded common memory address portion and output data from a memory entry corresponding to the decoded common memory address portion, and includes a single read port for outputting the data. The hardware arrangement includes a modified sense amplifier (SA) configured to receive the data output on the single read port, and directly receive the plurality of decoded uncommon memory address portions. The plurality of decoded uncommon memory address portions is used to determine whether to enable the modified SA. Data output from the memory bitcell is forwarded when the modified SA is enabled.

Abstract: An apparatus and method for providing a read-only memory (ROM) bit cell having one each of a PMOS transistor and an NMOS transistor, which has reduced static and dynamic electric power losses, are described. In particular, the bit cell does not require a pre-charge transistor. The sense amplifier for determining the voltages on ROM bit lines may be a digital inverter, address decoding may be simplified since there are no timing requirements with respect to transistor pre-charge, and chips containing a plurality of ROM bit cell may be readily programmed. In one embodiment of the invention, each bit cell includes one PMOS transistor having its source in electrical connection with a voltage source, its drain connected or unconnected to a bit line, and its gate connected to an inverted version of the word line signal; and one NMOS transistor having its source connected to a lower voltage source, its drain connected or disconnected to the bit line, and its gate connected to the word line.

Abstract: An analog memory having adjustable write bins including a system for writing to the memory. The system includes a write apparatus interpreting one or more write control signals, generating a write signal, and applying the write signal at a selected memory location to store a desired content. The selected memory location is subject to data dependent noise and is capable of storing a range of values grouped into “n” bins configured such that the average cost to write to at least “n-1” of the bins is within a threshold of a target cost for the selected analog memory location. The system also includes a read apparatus. The system further includes write control circuitry that includes a write signal selector selecting the one or more write control signals responsive to the desired content, current content of the selected memory location, and a bin associated with the desired content.

Abstract: A memory circuit includes a plurality of memory cells and a plurality of bit lines and row lines connected to the memory cells for accessing selected memory cells. The memory circuit includes a programmable voltage source adapted for connection to at least one bit line and operative to precharge the bit line to a prescribed voltage level prior to accessing a selected one of the memory cells coupled to the bit line. A control circuit coupled to the bit line is operative to oppose discharge of the bit line during at least a portion of a given memory read cycle. A tracking circuit connected to the control circuit is operative to control a delay in activation of the control circuit and/or a duration of time the control circuit is active as a function of a parameter affecting signal development time of a data signal on the bit line.

Abstract: A data writing method for a magnetoresistive effect element of an aspect of the present invention including generating a write current in which a falling period from the start of a falling edge to the end of the falling edge is longer than a rising period from the start of a rising edge to the end of the rising edge, and flowing the write current through the magnetoresistive effect element which comprises a first magnetic layer having an invariable magnetizing direction, a second magnetic layer having a variable magnetizing direction, and a tunnel barrier layer provided between the first magnetic layer and the second magnetic layer, to change the magnetizing direction of the second magnetic layer.

Abstract: A nonvolatile semiconductor memory device comprising: a memory cell array in which two bit lines are provided to each one bit of input data, and memory cells each including an anti-fuse element are arranged at an intersection point between one of the two bit lines and an even address word line, and an intersection point between the other one of the two bit lines and an odd address word line, respectively; a plurality of booster circuits which are arranged in a plurality of memory banks, respectively, and each of which generates a write voltage and a read voltage to be supplied to a corresponding one of the anti-fuse elements of the respective memory banks, each of the memory banks obtained by dividing the memory cell array; a booster circuit controller to issue an instruction to generate the write voltage and the read voltage to the plurality of booster circuits; a word line selector to activate a different word line at the time of writing from one to be activated at the time of reading, with respect to the s

Abstract: The invention provides a data read method. First, a training sequence stored in a storage unit of a memory is read according to at least one sense voltage to obtain a read-out training sequence. Whether the read-out training sequence is correct is then determined. When the read-out training sequence is not correct, the sense voltage is adjusted.

Abstract: A circuit comprises a control line and a two terminal semiconductor device having first and second terminals. The first terminal is coupled to a signal line, and the second terminal is coupled to the control line. The two terminal semiconductor device is adapted to have a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and to have a smaller capacitance when a voltage on the first terminal relative to the second terminal is below the threshold voltage. The control line is coupled to a control signal and the signal line is coupled to a signal and is output of the circuit. A signal is placed on the signal line and voltage on the control line is modified (e.g., raised in the case of n-type devices, or lowered for a p-type devices). When the signal falls below the threshold voltage, the two terminal semiconductor device acts as a very small capacitor and the output of the circuit will be a small value.

Abstract: Circuits and methods for transmitting and receiving small swing differential voltage data to and from a memory are described. A plurality of memory cells is formed in arrays within a plurality of memory banks. Each memory bank is coupled to a pair of small swing differential voltage global bit lines that extend across the memory. A small signal write driver circuit is coupled to the global bit lines and configured to output a small signal differential voltage on the global bit lines during write cycles. A global sense amplifier is coupled to the global bit line pairs and configured to output a full swing voltage on a data line during a read cycle. Methods for providing small swing global bit line signals to memory cells are disclosed. The use of small swing differential voltage signals across the memory reduces power consumption and shortens memory cycle time.

Abstract: An integrated circuit is provided including at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of bit cells. Each column of the memory cells is coupled to one of a plurality of bit lines. Each row of the memory cells is coupled to one of a plurality of word lines, to control coupling of that row of memory cells to the plurality of bit lines in dependence on a respective word line signal. Word line driver circuitry is configured to group together the word lines of at least three rows of memory calls, such that the word lines of the at least three rows of memory cells share a common word line signal. Thus in a write operation a written data value written into the array of memory cells is written to at least three memory cells having a shared bit line.

Abstract: Provided is a flash memory device including a wordline voltage generating unit, a switch unit, a row decoder and a control circuit. The wordline voltage generating unit generates at least one wordline voltage for read operations of a multi-level cell in the flash memory device. The switch unit receives the at least one wordline voltage and an initialization voltage, and selectively outputs the at least one wordline voltage and the initialization voltage through a switching operation. The row decoder operates the wordline of the multi-level cell based on an output of the switch unit. The control circuit provides at least one control signal to the switch unit, which outputs the initialization voltage in at least one section of the read operation in response to the at least one control signal.

Abstract: An object is to provide a semiconductor device with a novel structure, which can hold stored data even when power is not supplied and which has an unlimited number of write cycles. The semiconductor device is formed using a memory cell including a wide band gap semiconductor such as an oxide semiconductor. The semiconductor device includes a potential change circuit having a function of outputting a potential lower than a reference potential for reading data from the memory cell. When the wide band gap semiconductor which allows a sufficient reduction in of state current of a transistor included in the memory cell is used, a semiconductor device which can hold data for a long period can be provided.

Abstract: A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first line driver configured to output a portion of a output signals from sense amplifier according to a first delay signal; a second line driver configured to output a rest of the output signals from the sense amplifier according to a second delay signal; and a first delay unit configured to output a second delay signal synchronized with a clock to the second line driver.

Abstract: The non-volatile random access memory (RAM) includes a non-volatile RAM array, a buffer configured to buffer data to be programmed in the non-volatile RAM array and configured to buffer data read from the non-volatile RAM array, and a control block configured to read data from at least one of the non-volatile RAM array and the buffer based on whether the data to be read has been stored in the buffer, a temperature when the data was programmed, and a time lapse since the programming of the data.

Abstract: A nonvolatile memory device and a method of operating the same. The nonvolatile memory device includes a memory cell array including memory cells for storing data, a temperature sensor and a controller. The temperature sensor outputs a temperature detection signal according to ambient temperatures while changing one or more pieces of reference voltage information, which are previously stored, when data is programmed into the memory cell array. The controller performs a verify operation of the program using a fast verify method and decides the number of steps which are comprised in step-shaped verify voltage pulse of the fast verify method according to the temperature detection signal.

Abstract: A semiconductor memory device comprises a first memory cell array having a first plane which is composed of a plurality of blocks each having a plurality of memory cells, a sense circuit which reads data the memory cells, a sequencer which receives control signals from outside, a first address register, and a second address register which receives an output address from the first address register and outputs an address signal in response to an address control signal from the sequencer. In reading from the memory cells, the sequencer reads a page n in accordance with the address stored in the second address register, then transfers an address stored in the first address register to the second address register concurrently with outputting data read from the page n to outside and reads data from an arbitrary page m in accordance with the address transferred to the second address register.

Abstract: A multi-bit test circuit for a semiconductor memory is configured to cause an active command to activate active signals. At least two active signals are respectively inputted to a plurality of banks at different timings in a multi-bit test mode.

Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

Abstract: A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command. A starting address for a page including the received address is identified, wherein the page includes multiple rows of memory cells in the array of memory cells. The address register is reset to the starting address for the page. It is determined whether all memory cells in the page are non-programmed. Data indicative of a non-programmed state of the page is output if it is determined that all memory cells in the page are non-programmed.

Abstract: A semiconductor IC device includes a command decoder that provides internal read and internal write command signals in response to external command signals, and a delay control unit that is connected with the command decoder and provides an internal read command delay signal by controlling an activation timing of the internal read command signal in response to a test mode signal in a read mode.

Abstract: This disclosure provides a multiple-plane flash memory device where high voltage programming (setting) or erasing (resetting) pulses are timed to occur simultaneously. By regulating when each memory plane (e.g., each logical or physical partition of memory having its own dedicated array control and page buffer) applies high voltage pulses, the overhead circuitry needed to control multiple concurrent operations may be reduced, thereby conserving valuable die space. Both the “program phase” and the “verify phase” of each state change operation cycle may be orchestrated across all planes at once, with shared timing and high voltage distribution.