Particular Read Circuit Patents (Class 365/189.15)
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Patent number: 8254195Abstract: Embodiments of the present disclosure use one or more gain stages to generate an output voltage representing whether a resistive memory element of a data cell stores a high data value or a low data value. In a particular embodiment, an apparatus includes a sensing circuit. The sensing circuit includes a first amplifier stage that is configured to convert a first current through a first resistive memory element of a memory cell into a first single-ended output voltage. A second amplifier stage is configured to amplify the first single-ended output voltage of the first amplifier stage to produce a second single-ended output voltage.Type: GrantFiled: June 1, 2010Date of Patent: August 28, 2012Assignee: QUALCOMM IncorporatedInventor: Hari M. Rao
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Patent number: 8248838Abstract: A semiconductor device includes a comparison unit for comparing a resistance value of a memory element selectively connected to an input terminal with a resistance value of a reference resistance, and a resistance reference unit capable of selecting one of a plurality of resistance values and capable of being selectively connected to the input terminal.Type: GrantFiled: December 2, 2009Date of Patent: August 21, 2012Assignee: Elpida Memory, Inc.Inventor: Yasuko Tonomura
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Patent number: 8248868Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.Type: GrantFiled: April 1, 2011Date of Patent: August 21, 2012Assignee: Micron Technology, Inc.Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
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Patent number: 8248866Abstract: A semiconductor storage device, in which successive reading and successive writing of data having a predetermined length from and to a memory cell specified by a certain address are performed, includes a plurality of memory cells, address input terminals through which the address is input, data output terminals through which read data having the predetermined length is output, and data input terminals through which write data having the predetermine length is input. Part of the address input terminals are also used as the data output terminals. In this way, the operation of successive reading and successive writing performed in succession at the same address can be made faster without increasing the number of terminals.Type: GrantFiled: June 8, 2010Date of Patent: August 21, 2012Assignee: Renesas Electronics CorporationInventor: Tatsuya Ishizaki
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Publication number: 20120201086Abstract: A configuration for biasing conductive array lines in a two-terminal cross-point memory array is disclosed. The configuration includes applying a read voltage to a selected X-conductive array line while applying an un-select voltage thru a biasing element to a remaining plurality of un-selected X-conductive array lines. A plurality of Y-conductive array lines are initially biased to some voltage (e.g., 0V) and then allowed to float unbiased after a predetermined amount of time has passed, some event has occurred, or both. As one example the event that triggers the floating of the plurality of Y-conductive array lines can be the read voltage reaching a predetermined magnitude. The array can be formed BEOL and include a plurality of two-terminal memory cells with each memory cell including a memory element and optionally a non-ohmic device (NOD) that are electrically in series with each other and with the two terminals of the memory cell.Type: ApplicationFiled: April 17, 2012Publication date: August 9, 2012Applicant: UNITY SEMICONDUCTOR CORPORATIONInventor: Chang Hua Siau
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Patent number: 8238139Abstract: A dynamic RAM which includes a first inverter, a second inverter, a sense amplifier, a first pair of switches, a pair of bit lines, and a dynamic RAM cell. The first inverter receives a first driving signal. A power end of the first inverter is coupled to a first voltage source. The second inverter receives a second driving signal output from the first inverter. A power end of the second inverter is coupled to a second voltage source. The sense amplifier senses and amplifies a voltage difference between a first sensing signal and a second sensing signal. A power end of the sense amplifier is coupled to a third voltage source, wherein a voltage value of the second voltage source is between a voltage value of the first voltage source and a voltage value of the third voltage source.Type: GrantFiled: March 29, 2010Date of Patent: August 7, 2012Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Min-Chung Chou
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Patent number: 8238137Abstract: A ferroelectric random access memory device has a first bit line, a first ferroelectric capacitor, a second bit line, a second ferroelectric capacitor and a first to fourth MOS transistor. The first bit line is changed to a first data potential according to first data stored in the first ferroelectric capacitor, the second bit line is changed to a second data potential according to second data obtained by inverting a logic of the first data, and then the second MOS transistor and the fourth MOS transistor are turned on.Type: GrantFiled: September 17, 2009Date of Patent: August 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Hashimoto, Daisaburo Takashima
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Patent number: 8238173Abstract: An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit without any in-cell comparator circuitry.Type: GrantFiled: July 16, 2009Date of Patent: August 7, 2012Assignee: ZikBit LtdInventors: Avidan Akerib, Oren Agam, Eli Ehrman, Moshe Meyassed
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Publication number: 20120195109Abstract: According to one embodiment, a sense amplifier detects data stored in a memory cell based on potentials of bit lines of a bit line pair where bit line pairs are provided to correspond to columns of a memory cell array, respectively. Dummy cells are provided to correspond to rows of the memory cell array, respectively to simulate a read operation of the memory cells. A dummy bit line pair is driven in a complementary manner based on data read from the dummy cell. A read control unit controls the read operation of the memory cells based on the potential difference between dummy bit lines of the dummy bit line pair.Type: ApplicationFiled: September 20, 2011Publication date: August 2, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiromi Noro
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Patent number: 8233335Abstract: A semiconductor storage device, a first internal bus, a second internal bus, and a third internal bus have bus widths decreasing stepwise from a memory cell array side to a data output circuit side. A first selection circuit and a second selection circuit divide the data, which is input via the first or second internal bus, according to a rate of a decrease in bus width in an input and an output, time-divide the divided data, and output the divided data to the second or third internal bus.Type: GrantFiled: September 16, 2010Date of Patent: July 31, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hisaaki Nishimura, Katsuhiko Hoya
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Patent number: 8233329Abstract: Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.Type: GrantFiled: February 4, 2009Date of Patent: July 31, 2012Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Giovanni Santin, Michele Incarnati, Violante Moschiano
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Patent number: 8233334Abstract: A Code Address Memory (CAM) cell read control circuit of a semiconductor memory device includes a CAM cell read circuit configured to read data stored in a CAM cell and to output the read data, an internal delay circuit configured to delay an externally input reset signal and to generate a number of internal command signals, and a signal generation unit configured to generate an internal ready/busy signal in response to the internal command signals. The internal ready/busy signal is generated after the externally input reset signal has reset the CAM cell read circuit.Type: GrantFiled: December 31, 2009Date of Patent: July 31, 2012Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Nam Kim, Beom Ju Shin
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Patent number: 8233307Abstract: A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states.Type: GrantFiled: November 30, 2010Date of Patent: July 31, 2012Assignee: Radiant Technologies, Inc.Inventors: Joseph T. Evans, Jr., Calvin B. Ward
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Patent number: 8233302Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.Type: GrantFiled: January 4, 2011Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Igor Arsovski, Michael T. Fragano, Rahul K. Nadkarni, Reid A. Wistort
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Patent number: 8228742Abstract: Some embodiments include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to access the second memory cells. The first and second memory cells have a number of threshold voltage values corresponding to a number of states. The states represent values of information stored in the memory cells. During a read operation to read the first memory cells, a first voltage may be applied to the first line and a second voltage may be applied to the second line. At least one of the first and second voltages may include a value based on a change of at least one of the threshold voltage values changing from a first value to a second value. The first and second values may correspond to a unique state selected from all of the states. Other embodiments including additional apparatus, systems, and methods are disclosed.Type: GrantFiled: August 31, 2011Date of Patent: July 24, 2012Assignee: Micron Technology, Inc.Inventor: Seiichi Aritome
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Patent number: 8223584Abstract: An apparatus includes a memory circuit and an interface circuit. The interface circuit is coupled to the memory circuit. The interface circuit selects a phase value of clock signal adapted to clock the memory circuit.Type: GrantFiled: April 29, 2009Date of Patent: July 17, 2012Assignee: Altera CorporationInventor: Philip Clarke
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Patent number: 8223573Abstract: Method and device for controlling a memory access and correspondingly configured semiconductor memory A method and a device for controlling a memory access of a memory comprising memory cells are described. A completion of the memory access is determined by means of at least one dummy bit line. The at least one dummy bit line is connected to a plurality of memory cells of the memory cells of the memory such that a content of the at least one memory cell can be read out via the at least one dummy bit line. The at least one memory cell can be set to a predetermined potential. Each of said plurality of memory cells is connected to the at least one dummy bit line and to at least one dummy word line such that each of said plurality of memory cells can be set to the predetermined potential by means of the at least one dummy bit line and by means of the at least one dummy word line.Type: GrantFiled: February 26, 2009Date of Patent: July 17, 2012Assignee: Infineon Technologies AGInventors: Siegmar Koeppe, Martin Ostermayr
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Patent number: 8223564Abstract: A memory cell (100) includes a read circuit (30) whose output wiring is a read bit line (RBIT) and which has a switching transistor (31), a reset transistor (32), and an output wiring driving transistor (33). The switching transistor (31) connects a data holding node (MD) of a storage circuit (10) and a control line (DR) in accordance with a control signal on a read word line (/RWL0). The reset transistor (32) resets the control line (DR) in accordance with a reset control signal (RST). The output wiring driving transistor (33) has a gate connected to the control line (DR), a drain connected to the read bit line (RBIT), and a source connected to a ground power supply.Type: GrantFiled: February 27, 2009Date of Patent: July 17, 2012Assignee: Panasonic CorporationInventor: Tsuyoshi Koike
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Publication number: 20120176830Abstract: A nonvolatile memory device includes a variable resistance memory element and a read circuit coupled to the variable resistance memory element at a first signal node and configured to provide a read current to the variable resistance memory element via the first signal node, to a provide a mirror current at a second signal node responsive to the cell current and to generate an output signal indicative of a state of the variable resistance memory element responsive to a voltage at the second signal node.Type: ApplicationFiled: January 9, 2012Publication date: July 12, 2012Inventor: Young-Don Choi
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Patent number: 8218380Abstract: In an embodiment, an integrated circuit includes a memory and a control circuit configured to cause an inversion of at least a portion of the data stored in the memory to more evenly balance the amount of time that a given memory cell in the memory stores a binary one or a binary zero. In some implementations, the inversion may be controlled for the memory as a whole via a global indication. In other implementations, data may be inverted on a row-by-row or column-by-column basis. In other embodiments, the global indication may be changed at each boot of a device including the integrated circuit.Type: GrantFiled: October 30, 2009Date of Patent: July 10, 2012Assignee: Apple Inc.Inventor: Date Jan Willem Noorlag
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Patent number: 8218353Abstract: Integrated circuits with memory elements are provided. The memory elements may be arranged in a memory block. The memory block may include cross-coupled inverters that store data. The stored data may be used to program pass transistors. Transistors in the memory block may be stressed. Depending on the type of stress-inducing layer used, a tensile stress or a compressive stress may be built in into the transistors. Stressed transistors may help improve the routing speed of the memory block. Stressed transistors may be implemented using dual gate-oxide process.Type: GrantFiled: September 16, 2009Date of Patent: July 10, 2012Assignee: Altera CorporationInventors: Jun Liu, Shankar Sinha, Qi Xiang, Yow-Juang Liu
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Patent number: 8217641Abstract: A device for reading electric currents including a capacitive element to integrate the current, the terminals of the capacitive element being connected to the mass and to an output branch of the device respectively, and a differential pair including: a first transistor mounted between the input branch of the input stage and the capacitive element, the transistor being controlled by a polarized impulse voltage, capable of putting the first transistor alternately into the off state and then into the on state; and a second transistor mounted between the input branch of the input stage and a potential other than that of the capacitive element, said transistor also being controlled by a polarized impulse voltage, capable of putting the second transistor alternately into the off state and then into the on state, wherein the second transistor is mounted in phase opposition relative to the first transistor.Type: GrantFiled: September 28, 2009Date of Patent: July 10, 2012Assignee: Societe Francaise De Detecteurs Infrarouges-SofradirInventor: Eric Sanson
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Patent number: 8218360Abstract: Phase-change and resistance-change random access memory devices are provided which include a phase-change or resistance-change memory cell array and a sense amplifier that is configured to amplify data read from the phase-change memory cell array. These random access memory devices are configured to read data from a first word line of the phase-change or resistance-change memory cell array and to insert a dummy burst in which no data is read when a first boundary crossing occurs during a burst mode operation. Related methods of operating phase-change and/or resistance-change random access memory devices in burst mode are also provided.Type: GrantFiled: October 21, 2009Date of Patent: July 10, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-Jin Lee, Young-kug Moon, Young-pil Kim
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Publication number: 20120169753Abstract: A memory device is provided which includes a memory circuit that allows a circuit which carries out a refresh operation to suitably carry out an original operation of the circuit even if an off-leakage current occurs in a transfer element used in a transfer section. A memory cell includes a switching circuit, a first retaining section, a transfer section, a second retaining section, a first control section, and a voltage supply, and the first control section is controlled to be in (i) a state in which the first control section carries out a first operation in which the first control section is in an active state or a non-active state and (ii) a state in which the first control section carries out a second operation.Type: ApplicationFiled: April 23, 2010Publication date: July 5, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Yuhichiroh Murakami, Shige Furuta, Yasushi Sasaki, Seijirou Gyouten, Shuji Nishi
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Patent number: 8213242Abstract: A circuit comprises a plurality of memory cells in a row, at least one write word line, and a write support circuit coupled to the at least one write word line and to the plurality of memory cells in the row. The write support circuit includes a first current path and at least one second current path. A current path of the at least one second current path corresponds to a respective write word line of the at least one write word line. A write word line of the at least one write word line is configured to select the first current path when the plurality of memory cells in the row operates in a first mode, and to select a second current path of the at least one second current path when the plurality of memory cells in the row operates in a second mode.Type: GrantFiled: September 23, 2010Date of Patent: July 3, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shreekanth Sampigethaya, Bharath Upputuri
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Patent number: 8208285Abstract: A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain.Type: GrantFiled: July 13, 2009Date of Patent: June 26, 2012Assignee: Seagate Technology LLCInventors: Maroun Georges Khoury, Hyung-Kyu Lee, Peter Nicholas Manos, Chulmin Jung, YoungPil Kim
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Publication number: 20120155196Abstract: A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read circuit that reads data from cells of x bits based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as read address, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.Type: ApplicationFiled: September 1, 2011Publication date: June 21, 2012Applicant: Fujitsu LimitedInventors: Yoshinori Tomita, Hidetoshi Matsuoka, Hiroyuki Higuchi
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Publication number: 20120155197Abstract: A semiconductor memory device includes a page buffer configured to store data read from a memory cell, a counter circuit configured to count the number of first data or second data in the read data for every read operation while the read operations are repeated a set number of times, and a control logic configured to determine the number of read operations and determine the read data of the memory cell based on the counted number.Type: ApplicationFiled: December 20, 2011Publication date: June 21, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Seok Jin JOO
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Publication number: 20120155195Abstract: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.Type: ApplicationFiled: December 17, 2010Publication date: June 21, 2012Applicant: STMicroelectronics Inc.Inventor: David V. Carlson
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Publication number: 20120155189Abstract: In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component.Type: ApplicationFiled: February 29, 2012Publication date: June 21, 2012Applicant: Infineon Technologies AGInventors: Thomas Nirschl, Jan Otterstedt, Michael Bollu, Wolf Allers
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Publication number: 20120159076Abstract: Sense amplifiers in a memory may be activated and deactivated. In one embodiment, a processor may include a memory. The memory may include a number of sense amplifiers. Based on a late arriving address bit of an address used to access data from the memory, a sense amplifier may be activated while another sense amplifier may be deactivated.Type: ApplicationFiled: June 20, 2011Publication date: June 21, 2012Inventors: Abhijeet R. Tanpure, Steven C. Sullivan, William V. Miller, Jason A. Frerich
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Patent number: 8203894Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.Type: GrantFiled: April 6, 2011Date of Patent: June 19, 2012Assignee: Seagate Technology LLCInventors: Chulmin Jung, Insik Jin, YoungPil Kim, Yong Lu, Harry Hongyue Liu, Andrew John Carter
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Patent number: 8203891Abstract: A voltage sensing circuit, which is capable of controlling a pumping voltage to be stably generated in a low voltage environment, is provided. The voltage sensing circuit includes a current mirror having first and second terminals, a first switching element configured to control current on the first terminal of the current mirror by a reference voltage, a second switching element configured to control current from the second terminal of the current mirror in response to a pumping voltage, and a third switching element configured to control current sources of the first and second switching elements to receive a negative voltage.Type: GrantFiled: May 5, 2011Date of Patent: June 19, 2012Assignee: Hynix Semiconductor Inc.Inventors: Woo-Seung Han, Khil-Ohk Kang
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Patent number: 8203888Abstract: A non-volatile semiconductor storage device according to one aspect of the present invention includes a plurality of sense amplifier circuit that are configured to carry out a plurality of read cycles on a plurality of bit lines connected to those memory cells that are selected by a selected one of the word lines. During the second and subsequent read cycles, supply of a read current is ceased to those bit lines when it is determined in the preceding read cycle that a current not less than a certain determination current level flows therethrough, and the read current is supplied only to the remaining bit lines. A setup time of the bit lines in the first read cycle is set shorter than a setup time of the bit lines in the second and subsequent read cycles.Type: GrantFiled: September 3, 2010Date of Patent: June 19, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Fukuda, Makoto Iwai
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Patent number: 8203899Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for sensing a programmed state of a memory cell, such as a spin-torque transfer random access memory (STRAM) cell. A first read current is applied to the memory cell to generate a first voltage. A second read current is subsequently applied to the memory cell to generate a second voltage, with the second read current being proportional in magnitude to the first read current. A comparison is made between the first and second voltages to determine the programmed state of the memory cell.Type: GrantFiled: November 15, 2010Date of Patent: June 19, 2012Assignee: Seagate Technology LLCInventors: Yiran Chen, Hai Li, Wenzhong Zhu, Xiaobin Wang, Ran Wang, Harry Hongyue Liu
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Patent number: 8199556Abstract: Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is applied for a sufficient duration of time; and the reading is conducted with a pulse that is of too short of a time duration to be sufficient for the write operation. In some embodiments, the pulse utilized for the reading may have an absolute value of voltage that is greater than or equal to the voltage utilized for the write operation. In some embodiments, the memory cells may comprise non-ohmic devices; such as memristors and diodes.Type: GrantFiled: September 22, 2009Date of Patent: June 12, 2012Assignee: Micron Technology, Inc.Inventors: Bhaskar Srinivasan, Gurtej S. Sandhu
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Patent number: 8199552Abstract: A One-Time Programmable (OTP) unit cell and a nonvolatile memory device having the same are disclosed. A unit cell of a nonvolatile memory device includes: an anti-fuse connected between an output terminal and a ground voltage terminal; a first switching unit connected to the output terminal to transfer a write voltage to the output terminal; and a second switching unit connected to the output terminal to transfer a read voltage to the output terminal.Type: GrantFiled: February 10, 2009Date of Patent: June 12, 2012Assignee: Magnachip Semiconductor, Ltd.Inventors: Chang-Hee Shin, Ki-Seok Cho, Seong-Do Jeon
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Patent number: 8194477Abstract: A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes a circuit with first and second inputs and an output. The circuit is configured to combined (add or subtract) input signals. The first input may be connected to the analog input. The delta-sigma modulator may also include an integrator connected to the output of the circuit, an analog-to-digital converter with an input connected to an output of the integrator and an output connected to the digital output, and a digital-to-analog converter with an input connected to the output of the analog-to-digital converter and an output connected to the second input of the circuit.Type: GrantFiled: November 22, 2010Date of Patent: June 5, 2012Assignee: Micron Technology, Inc.Inventor: R. Jacob Baker
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Patent number: 8194444Abstract: Self-reference reading a magnetic tunnel junction data cell methods are disclosed. An illustrative method includes applying a read voltage across a magnetic tunnel junction data cell and forming a read current. The magnetic tunnel junction data cell has a first resistance state. The read voltage is sufficient to switch the magnetic tunnel junction data cell resistance. The method includes detecting the read current and determining if the read current remains constant during the applying step. If the read current remains constant during the applying step, then the first resistance state of the magnetic tunnel junction data cell is the resistance state that the read voltage was sufficient to switch the magnetic tunnel junction data cell to.Type: GrantFiled: December 15, 2010Date of Patent: June 5, 2012Assignee: Seagate Technology LLCInventors: Yuankai Zheng, Yiran Chen, Xiaobin Wang, Zheng Gao, Dimitar V. Dimitrov, Wenzhong Zhu, Yong Lu
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Publication number: 20120134198Abstract: A memory system includes a memory cell array including a plurality of memory cells electrically connected to pairs of bit lines once a word line is activated; latch portions connected to respective pairs of bit lines; a sense amplifier connected to the latch portions; and a control circuit configured to control the latch portions for a reading operation in order that data in all memory cells connected to the word line, once selected, come to be held in the corresponding latch portions as a group.Type: ApplicationFiled: November 29, 2011Publication date: May 31, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koichiro Yamaguchi, Jin Kashiwagi
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Patent number: 8189405Abstract: A data readout circuit including a 1st PMOS transistor operating in saturation and including a source connected to a power supply, a drain connected to an input terminal a memory cell, and a gate connected to a 1st bias voltage; a 2nd PMOS transistor including a source connected to the drain of the 1st PMOS transistor, a drain connected to an output terminal, and a gate connected to a 2nd bias voltage; a 1st NMOS transistor including a drain connected to the drain of the 2nd PMOS transistor, a source grounded, and a gate connected to a 3rd bias voltage; and a bias voltage section causing the 2nd PMOS transistor to operate in saturation, and supplying the 2nd bias voltage adjusted so as to keep a reference voltage of the input terminal at a junction point between the drain and the source of the 1st and 2nd PMOS transistors respectively.Type: GrantFiled: July 16, 2009Date of Patent: May 29, 2012Assignee: OKI Semiconductor Co., Ltd.Inventors: Nobukazu Murata, Katsuaki Matsui
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Patent number: 8189402Abstract: An output current of a memory cell is sensed by a sensing circuit for distinguishing a program state and an erase state of the memory cell. The sensing circuit includes a reference transistor, a P-type MOSFET, and an N-type MOSFET. The P-type MOSFET has a gate connected to a memory cell for receiving an output current of the memory cell. The N-type MOSFET has a drain connected to a drain of the first P-type MOSFET, and has a source connected to ground. The inverter has an input terminal connected to the drain of the first N-type MOSFET. The voltage at an output terminal of the inverter is used for indicating the program state or the erase state of the memory cell. The reference transistor has a gate connected to a reference signal, and has a drain connected to the gate of the P-type MOSFET.Type: GrantFiled: June 16, 2010Date of Patent: May 29, 2012Assignee: eMemory Technology Inc.Inventor: Yih-Lang Lin
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Patent number: 8189410Abstract: A first input of a sense amplifier is connected to a first bitline, a second input of the sense amplifier is connected to a second bitline, a third input of the sense amplifier is coupled to a third bitline. The sense amplifier provides at an output an indicator of a storage state of a memory cell connected to the first bitline based upon information provided to the sense amplifier via the first, second, and third bitlines.Type: GrantFiled: April 27, 2010Date of Patent: May 29, 2012Inventor: Bruce Lee Morton
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Patent number: 8189409Abstract: In one embodiment, a readout circuit for rewritable memories comprises a control logic unit with an input for supplying a start signal and with several outputs for providing a respective control signal as a function of start signal, a first terminal for switchable connection to a first memory cell by means of a first switch, and a second terminal for switchable connection by means of a second switch to a second memory cell, and a readout unit coupled to the control logic unit, as well as to the first and second terminals, with an output for providing an output signal as a function of a state of the first and/or the second memory cell and as a function of the control signals, wherein the readout circuit is designed for self-terminating operation in a reading mode and in a test mode. A readout method for rewritable memories is additionally provided.Type: GrantFiled: March 2, 2010Date of Patent: May 29, 2012Assignee: austriamicrosystems AGInventors: Johannes Fellner, Gregor Schatzberger
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Patent number: 8184491Abstract: Methods for reading a memory cell are provided. The method for reading a memory cell includes applying a first read pulse to a memory cell, heating the memory cell to a first temperature and obtaining a first read data. The first read data is converted to a first digital data. The first digital data is stored in a shift register. A second read pulse is applied to the memory cell, heating the memory cell to a second temperature and obtaining a second read data. The second read data is converted to a second digital data. The second digital data is stored in the shift register. A ratio of the first digital data and the second digital data is calculated, obtaining a quotient. The quotient is converted to an analog value. A log amplifier circuit takes the log of the analog value, representing an activation energy state.Type: GrantFiled: August 17, 2009Date of Patent: May 22, 2012Assignee: Industrial Technology Research InstituteInventor: Frederick T Chen
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Patent number: 8184499Abstract: A semiconductor memory apparatus is provided. The semiconductor memory apparatus comprises: first and second memory banks located a predetermined distance from each other in a first direction; a common column selection control unit located at an outside region in the first and second memory banks in the first direction, and configured to commonly control access to column areas in the first and second memory banks and generate a column selection signal that controls data access to the corresponding memory cells in the first and second memory banks; a first data read/write unit configured to sense and amplify read data transferred from the first memory bank and transfer write data to the first memory bank; and a second data read/write unit configured to sense and amplify read data transferred from the second memory bank and transfer write data to the second memory bank.Type: GrantFiled: December 31, 2009Date of Patent: May 22, 2012Assignee: Hynix Semiconductor Inc.Inventor: Heat Bit Park
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Patent number: 8184490Abstract: A self-calibration circuit of a nonvolatile memory includes a trimming data storage module, a sense amplifier module, a logic judgment module, and a scanning module. The nonvolatile memory circuit includes a memory cell array and the self-calibration circuit of the reading circuit of the nonvolatile memory. Without requiring an additional fuse or differential unit, the self-calibration circuit of a nonvolatile memory solves a deadlock problem securely and reliably without increasing circuit area and test cost, and be widely applied to OTP, MTP and EEPROM of various processes or various nonvolatile memories such as Flash EEPROM, MRAM, and FeRAM.Type: GrantFiled: July 20, 2009Date of Patent: May 22, 2012Assignee: Shanghai Hua Hong NEC Electronics Company, Ltd.Inventors: Nan Wang, Xiang Yao
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Patent number: 8179731Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: GrantFiled: August 6, 2009Date of Patent: May 15, 2012Assignee: Analog Devices, Inc.Inventors: Benjamin Vigoda, Eric Nestler, Jeffrey Bernstein, David Reynolds, Alexander Alexeyev, Jeffrey Venuti, William Bradley, Vladimir Zlatkovic
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Publication number: 20120113731Abstract: A unit operator cell includes a plurality of SOI (Silicon on Insulator) transistors, write data is stored in a body region of at least two SOI transistors, and the storage SOI transistors are connected in series with each other to a read port or each of the storage SOI transistors is singly connected to the read port. Therefore, an AND operation result or a NOT operation result of data stored in the unit operator cells can be obtained, and operation processing can be performed only by writing and reading data. A semiconductor signal processing device that can perform logic operation processing and arithmetic operation processing at high speed is implemented with low power consumption and a small occupation area.Type: ApplicationFiled: January 19, 2012Publication date: May 10, 2012Applicant: Renesas Electronics CorporationInventors: Hiroki SHIMANO, Kazutami Arimoto
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Patent number: 8174909Abstract: A nonvolatile semiconductor memory, includes a nonvolatile memory array, a voltage generator circuit that generates a drive voltage which changes depending on a supply voltage and a code, a control circuit that applies the generated drive voltage to the nonvolatile memory array, and a code output circuit that outputs any one of a plurality of codes to the voltage generator circuit, wherein the plurality of codes includes a first code and a second code, wherein the second code is different from the first code, wherein, in a first state, the code output circuit outputs the first code to the voltage generator circuit, and the voltage generator circuit generates the drive voltage according to the first code, and wherein, in a second state, the code output circuit outputs the second code to the voltage generator circuit, and the voltage generator circuit generates the drive voltage according to the second code.Type: GrantFiled: June 22, 2011Date of Patent: May 8, 2012Assignee: Renesas Electronics CorporationInventor: Satoru Oku