Abstract: A memory integrated circuit (IC) includes a read module and a sequence detector module. The read module reads S memory cells (cells) located along one of a bit line and a word line and generates S read signals, where S is an integer greater than 1. The sequence detector module detects a data sequence based on the S read signals and reference signals. The data sequence includes data stored in the S cells. Each of the reference signals includes an interference-free signal associated with one of the S cells and an interference signal associated with another of the S cells that is adjacent to the one of the S cells.

Abstract: One embodiment of the present invention sets forth a clamping circuit that is used to maintain a bit line of a storage cell in a memory array at a nearly constant clamp voltage. During read operations the bit line is pulled high or low from the clamp voltage by the storage cell and a change in current on the bit line is converted by the clamping circuit to produce an amplified voltage that may be sampled to read a value stored in the storage cell. The clamping circuit maintains the nearly constant clamp voltage on the bit line. Clamping the bit line to the nearly constant clamp voltage reduces the occurrence of read disturb faults. Additionally, the clamping circuit functions with a variety of storage cells and does not require that the bit lines be precharged prior to each read operation.

Abstract: A semiconductor memory circuit includes a memory cell array having a plurality of memory cells arranged in a row direction and a column direction; a row selecting unit for selecting the memory cells of the memory cell array aligned in the row direction; a column selecting unit for selecting the memory cells of the memory cell array aligned in the column direction; a plurality of main bit lines for outputting data of the memory cells; a data reading unit for reading data of one of the memory cells selected with the row selecting unit and the column selecting unit; a first multiplexer for connecting one of the main bit lines connected to the memory cell to the data reading unit; and a second multiplexer for connecting an adjacent main bit line situated adjacently outside the main bit line to a charging/discharging voltage source for setting at a specific voltage.

Abstract: Methods, apparatuses, and systems for comparing threshold voltages of a plurality of flash memory cells to a plurality of reference voltages. A number of flash memory cells having threshold voltages that fall within each bin of a plurality of bins is determined. The plurality of bins each represent a plurality of threshold voltage ranges. A threshold voltage distribution of the plurality of flash memory cells is calculated based at least in part on the number of flash memory cells that fall into each of the bins.

Abstract: Providing increased capacity in heterogeneous storage elements including a method for storing data including a write process writing to a memory and a read process reading from the memory. Physical characteristics of memory cells in the memory support different sets of data levels. The write process takes into account the different sets of data levels when writing to the memory. The read process first obtains data in the memory and subsequently determines how to interpret the data.

Abstract: A SRAM READ and WRITE assist apparatus comprises a bit line voltage tracking block, a READ assist timer, a READ assist unit, a WRITE assist unit a WRITE control unit. The bit line voltage tracking block detects a voltage on a tracking bit line coupled to a plurality of tracking memory cells. In response to the voltage drop on the tracking bit line, the READ assist timer generates a READ assist pulse. When the READ assist pulse has a logic high state, an activated word line is pulled down to a lower voltage. Such a lower voltage helps to improve the robustness of SRAM memory circuits so as to avoid READ and WRITE failures.

Abstract: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.

Abstract: A memory controller includes: a first write circuit configured to write a first dummy pattern including a plurality of consecutive first dummy values at a first address of a memory; a second write circuit configured to write a first pattern including a plurality of types of consecutive values at a second address of the memory after a write operation of the first dummy pattern by the first write circuit; a third write circuit configured to write a second dummy pattern including a plurality of consecutive second dummy values at a third address of the memory after a write operation of the first pattern by the second write circuit; a read circuit configured to read the written first pattern based on the second address of the memory; and a timing adjustment circuit configured to adjust a timing at which data is written into the memory based on a read first pattern.

Abstract: Systems (100) and methods (600) for reading data from a memory device (106). The methods involve (606) receiving first read request signals (118, 120, 122, 126, 128) for first data stored in the memory device. In response to the first read request signals, (608) retrieving a first page of data from a cell array (268) of the memory device. The methods also involve (616) receiving second read request signals for second data stored in the memory device. (618) Next, a determination is made as to whether at least a portion of a memory address for the second data is the same as at least a respective portion of a memory address for the first data. (622) If it is determined that the respective portions of the memory addresses are the same, then a read access to the cell array is disabled.

Abstract: A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.

Abstract: A FIFO with data storage implemented with non-volatile third dimension memory cells is disclosed. The non-volatile third dimension memory cells can be fabricated BEOL on top of a substrate that includes FEOL fabricated active circuitry configured for data operations on the BEOL memory cells. Other components of the FIFO that require non-volatile data storage can also be implemented as registers or the like using the BEOL non-volatile third dimension memory cells so that power to the FIFO can be cycled and data is retained. The BEOL non-volatile third dimension memory cells can be configured in a single layer of memory or in multiple layers of memory. An IC that includes the FIFO can also include one or more other memory types that are emulated using the BEOL non-volatile third dimension memory cells and associated FEOL circuitry configured for data operations on those memory cells.

Abstract: A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias compensation unit. The sensing unit includes a sense amplifier, a latch circuit, a first precharged bit line, and a second precharged bit line. The equalizing unit is electrically connected to the first and the second precharged bit line for regulating a voltage of the first precharged bit line and a voltage of the second precharged bit line to the same electric potential. The bias compensation unit is electrically connected to the sense amplifier for compensating an input offset voltage of the current-sense amplifier.

Abstract: A method for reading a memory cell (20) of a semiconductor memory (10) includes initiating a precharge or predischarge operation on a bit line (24) prior to arrival of a triggering edge of a clock signal (32) that initiates a read operation. A word line (22) is activated responsive to the triggering edge of the clock signal (32), and data is read from the memory cell (20).

Abstract: A semiconductor memory device includes a first memory cell array having a first plane which is composed of a plurality of blocks each having a plurality of memory cells, a sense circuit which reads data the memory cells, a sequencer which receives control signals from outside, a first address register, and a second address register which receives an output address from the first address register and outputs an address signal in response to an address control signal from the sequencer. In reading from the memory cells, the sequencer reads a page n in accordance with the address stored in the second address register, then transfers an address stored in the first address register to the second address register concurrently with outputting data read from the page n to outside and reads data from an arbitrary page m in accordance with the address transferred to the second address register.

Abstract: A sense amplifier scheme for SRAM is disclosed. In accordance with one of the embodiments of the present application, a sense amplifier circuit includes a bit line, a sense amplifier output, a power supply node having a power supply voltage, a keeper circuit including an NMOS transistor, and a noise threshold control circuit. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and maintains a voltage level of the bit line and the noise threshold control circuit lowers a trip point of the sense amplifier output.

Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.

Abstract: A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.

Abstract: A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read. window or margin may be improved in some embodiments.

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract: A semiconductor device including a plurality of memory cells arranged in a matrix pattern, a write amplifier which writes write data to the memory cell in synchronization with a clock, a sense amplifier which reads out the write data written in the memory cell in synchronization with the clock, a plurality of column select switches which connect the plurality of the memory cells with the sense amplifier and the write amplifier, a column address decoder which makes the column select switch corresponding to one column among the plurality of the memory cells a conductive state based on a column address, a row address decoder which activates the memory cell of one row based on a row address, and a test write circuit which writes data corresponding to a logical level of a test signal to the memory cell based on a test mode signal.

Abstract: A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

Abstract: A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell.

Abstract: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write strobe to compensate for timing drift at the memory device. The memory controller uses the read strobe as a measure of the drift.

Abstract: A resistance based memory sensing circuit has reference current transistors feeding a reference node and a read current transistor feeding a sense node, each transistor has a substrate body at a regular substrate voltage during a stand-by mode and biased during a sensing mode at a body bias voltage lower than the regular substrate voltage. In one option the body bias voltage is determined by a reference voltage on the reference node. The substrate body at the regular substrate voltage causes the transistors to have a regular threshold voltage, and the substrate body at the body bias voltage causes the transistors to have a sense mode threshold voltage, lower than the regular threshold voltage.

Abstract: A semiconductor device which is capable of high-speed writing with less power consumption and suitable for multi-leveled memory, and verifying operation. A memory cell included in the semiconductor device included a transistor formed using an oxide semiconductor and a transistor formed using a material other than an oxide semiconductor. A variation in threshold value of the memory cells is derived before data of a data buffer is written by using a writing circuit. Data in which the variation in threshold value is compensated with respect to the data of the data buffer is written to the memory cell.

Abstract: A ferroelectric random access memory (FRAM) with reduced cycle time. During a read cycle, plate line voltages are boosted to a voltage to both transfer charge from the selected row of FRAM cells to corresponding bit lines, and to fully polarize a data state in the selected FRAM cells. In one embodiment of the invention, the fully polarized data states is present in those cells that previously stored that data state; for those cells storing the opposite state, a write-back pulse is executed. In another embodiment of the invention, the fully polarized data state results for each of the selected memory cells, by applying a plate line boost voltage of a higher magnitude. Those cells that are to store the opposite data state, as may be determined following error correction, are written back with that data state.

Abstract: A semiconductor device which has a sense amplifier and is supplied with an external power supply voltage includes a drive signal line connected to the sense amplifier, a step up circuit generating a first voltage from the external power supply voltage, the first voltage being higher than the external power supply voltage, and a step down circuit lowering the external power supply voltage into a second voltage. For enabling the sense amplifier to perform sensing operation in a normal mode involving external access, the first voltage is applied to the drive signal line in an initial stage of the sensing operation, and thereafter the second voltage is applied to the drive signal line. In a refresh mode not involving external access, the step up circuit is shut down, and the second voltage is applied to the drive signal line from the initial stage of the sensing operation.

Abstract: A data processing device according to the present invention comprises a nonvolatile memory and a trimming data read control circuit. The nonvolatile memory has a plurality of memory regions in which the same trimming data is stored. The trimming data read control circuit reads the trimming data from a random one of the plurality of memory regions.

Abstract: Memory elements are provided that exhibit immunity to soft error upsets. The memory elements may have cross-coupled inverters. The inverters may be implemented using programmable Schmitt triggers. The memory elements may be locked and unlocked by providing appropriate power supply voltages to the Schmitt trigger. The memory elements may each have four inverter-like transistor pairs that form a bistable element, at least one address transistor, and at least one write enable transistor. The write enable transistor may bridge two of the four nodes. The memory elements may be locked and unlocked by turning the write enable transistor on and off. When a memory element is unlocked, the memory element is less resistant to changes in state, thereby facilitating write operations. When the memory element is locked, the memory element may exhibit enhanced immunity to soft error upsets.

Abstract: A write circuit is adapted to provide a same logical bit to each of a multitude of memory cells for storage. Each of the multitude of memory cells stores either the bit or a complement of the bit in response to the write circuit. A read circuit is adapted to receive the bits stored in the multitude of memory cells and to generate an output value defined by the stored bits in accordance with a predefined rule. The predefined rule may be characterized by a statistical mode of the bits stored in the plurality of memory cells. Storage errors in a minority of the multitude of memory cells may be ignored at the cost of lower memory density. The predefined rule may be characterized by a first weight assigned to bits 1 and a second weight assigned to bits 0.

Abstract: An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the memory channel, and a second memory module to couple to the memory channel. The first memory module may include a first memory having a first ODT circuit to receive the first ODT signal, and a second memory having a second ODT circuit to receive the first ODT signal. The first ODT signal may disable the ODT circuit of the first memory when the first memory is to be ACTIVE.

Abstract: A semiconductor memory device has: memory blocks; and a local bus connected to the memory blocks. Each memory block has: switches respectively provided between bit line pairs and the local bus and each of which is turned ON in response to a selection signal; a dummy local bus; first and second control circuits. The local bus and the dummy local bus are precharged to a first potential before a read operation. In the read operation, the first control circuit outputs the selection signal to a selected switch to electrically connect a selected bit line pair and the local bus, while the second control circuit supplies a second potential lower than the first potential to the dummy local bus. The first control circuit stops outputting the selection signal when a potential of the dummy local bus is decreased to a predetermined set potential that is between the first and second potentials.

Abstract: A method of controlling a plurality of memory cells in a row. The method includes controlling a switching element using at least one write word line signal to raise a voltage of a node connected to the plurality of memory cells in the row when the plurality of memory cells in the row operate in a first mode. The method further includes controlling at least one transistor using the at least one write word line signal to connect the plurality of memory cells in the row to a reference voltage when the plurality of memory cells in the row operate in a second mode.

Abstract: A pair of operator cells each having a series-coupled circuit of first and second transistors is used as a storage unit. To-be-retrieved data and retrieval data are respectively stored in the first and second transistors, and mutually complementary data items are stored in the operator cells of the storage unit. The operator cells supply currents according to the result of an AND operation between the stored data items to corresponding bit lines, and the read data from the storage unit corresponds to the result of an EXOR operation between the retrieval data and the to-be-retrieved data. The currents flowing in the corresponding bit lines are amplified with sense amplifier circuits to drive local match lines. In the individual sub-blocks of an operator cell array, data items having different pattern lengths can be stored. The potentials of the local match lines are selected according to the data pattern lengths, and match retrieval is performed for the data items having the different pattern lengths.

Abstract: In a first aspect, a level shifter circuit for use in a memory array is provided that includes (1) a first voltage domain powered by a first voltage; (2) a second voltage domain powered by a second voltage; (3) level shifter circuitry that converts an input signal from the first voltage domain to the second voltage domain; and (4) isolation circuitry that selectively isolates the first voltage domain from the second voltage domain so as to selectively prevent current flow between the first voltage domain and the second voltage domain. Numerous other aspects are provided.

Abstract: A unit operator cell includes a plurality of SOI (Silicon on Insulator) transistors, write data is stored in a body region of at least two SOI transistors, and the storage SOI transistors are connected in series with each other to a read port or each of the storage SOI transistors is singly connected to the read port. Therefore, an AND operation result or a NOT operation result of data stored in the unit operator cells can be obtained, and operation processing can be performed only by writing and reading data. A semiconductor signal processing device that can perform logic operation processing and arithmetic operation processing at high speed is implemented with low power consumption and a small occupation area.

Abstract: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory cells coupled thereto. Memory cell control circuitry applies one or more read control signals to perform a read operation wherein, in response to the read control signals, a selected memory cell conducts a current which is representative of the data state stored therein. Sense amplifier circuitry senses the data state stored in the selected memory cell using a signal which is responsive to the current conducted by the selected memory cell. Current regulation circuitry is responsively and electrically coupled to the bit line during a portion of the read operation to sink or source at least a portion of the current provided on the bit line.

Abstract: According to one embodiment, in a memory cell array, a plurality of memory cells is arranged in an array. A read circuit reads out data from the memory cells. A word line driver drives a word line of the memory cells. A characteristic control unit controls a specific characteristic of the memory cells. A word-line-potential adjusting unit adjusts a potential of the word line based on a distribution of the characteristic when the specific characteristic of the memory cells is controlled.

Abstract: A method of processing a strobe signal can include oversampling a strobe signal received from a source synchronous device and determining an amount of time between sending a read request to the source synchronous device and detecting a first pulse of the strobe signal according to the oversampling. The method also can include squelching the strobe signal for the amount of time responsive to at least one subsequent read request.

Abstract: A memory interface circuit includes a clock signal supply buffer configured to send a system clock signal which is supplied through a reference node, to a memory through a transmission line; a data strobe buffer configured to receive a data strobe signal supplied from the memory; a system clock synchronizing circuit configured to supply a data read from the memory to a logic circuit in synchronization with the system clock signal; and a delay detecting circuit provided at a front stage to the system clock synchronizing circuit and configured to detect a transmission delay from the clock signal supply buffer to the data strobe buffer. The delay detecting circuit generates a phase difference data indicating the transmission delay based on a difference between a phase of the system clock signal and a phase of the data strobe signal outputted from the data strobe buffer, and supplies the phase difference data to the system clock synchronizing circuit.

Abstract: A data processing device including a nonvolatile memory comprising a plurality of memory regions in which a same trimming data is stored, and a trimming data read control circuit configured to read the trimming data from a random memory region. The trimming data read control circuit comprises a region selection signal generation circuit configured to generate a region selection signal that specifies a random memory region among the memory regions, and a read circuit configured to read the trimming data from the random one memory region in response to the region selection signal. The region selection signal generation circuit comprises a clock counter configured to count a clock signal until a reset signal is input, and a signal generation circuit configured to generate the region selection signal based on a count value of the clock counter. The reset signal is input to the clock counter at a random timing.

Abstract: According to one embodiment, a semiconductor storage device includes cells, and a sense amplifier. Each of the cells is connected to a bit line. The sense amplifier reads out data. The sense amplifier includes a first transistor to third transistor, and a switch. The first transistor has one end of a current path, the other end, and a gate. The second transistor has one end, and the other end. The second transistor has one of a first and a second supply ability. The third transistor has one end, and the other end. The third transistor has one of a third and a fourth supply ability. The switch grounds the second and the third transistors. The sense amplifier turns off the first transistor after transferring the data to an outside, and supplies the second signal to the switch to set gates of the second transistor and third transistor to ground.

Abstract: A memory control method that carries out first-in first-out access control for a memory having a plurality of storage areas, including: selecting, as write positions, an address of a storage area in a storage block having at least one or more storage areas and an address of a storage area in any one of a plurality of redundant blocks that are made redundant with respect to the storage block and have at least one or more storage areas when the write positions are selected to write data to the memory; and selecting, as read positions, an address of a storage area of the storage block and an address selected by the selecting of the write position from among the addresses of a plurality of the redundant blocks when the read positions are selected to read data written by the writing of the data to the memory.

Abstract: A semiconductor memory device includes a memory cell array including an even page cell group and an odd page cell group, and a page buffer configured to read data stored in memory cells of the even page cell group and the odd page cell group and store the read data. The page buffer comprises a first latch configured to store first even page data of the even page cell group when a first read operation is performed, a second latch configured to store odd page data of the odd page cell group when a second read operation is performed, and a third latch configured to store second even page data of the even page cell group when a third read operation is performed.

Abstract: According to one embodiment, a nonvolatile semiconductor storage device having a plurality of operation modes, includes: a plurality of first lines; a plurality of second lines; a plurality of memory cells; a first selection unit that charges the first line to a first selection voltage; and a second selection unit that charges a second line to an unselection voltage and discharges the second line to a second selection voltage after the first line is charged to the first selection voltage by the first selection unit, wherein the second selection unit adjusts at least one of a level of the second selection voltage to which the second line to be selected is to be discharged and a time constant when discharging the second line to be selected, in accordance with an operation mode in which the nonvolatile semiconductor storage device operates among the plurality of operation modes.

Abstract: A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.

Abstract: A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.

Abstract: Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is applied for a sufficient duration of time; and the reading is conducted with a pulse that is of too short of a time duration to be sufficient for the write operation. In some embodiments, the pulse utilized for the reading may have an absolute value of voltage that is greater than or equal to the voltage utilized for the write operation. In some embodiments, the memory cells may comprise non-ohmic devices; such as memristors and diodes.

Abstract: A method and a system for reading from memory cells in a memory device are provided. In one embodiment, the memory device comprises a first plurality of data lines and a second plurality of data lines, at least one first multiplexer coupled to the first plurality of data lines and at least one low reference line, at least one second multiplexer coupled to the second plurality of data lines and at least one high reference line, at least one third multiplexer coupled to the at least one first multiplexer and the at least one second multiplexer, and a reference memory cell coupled to the at least one third multiplexer and at least one sense amplifier.

Abstract: A semiconductor memory device includes a read circuit configured to sequentially output a plurality of compressed data corresponding to all banks which are to be tested in response to a plurality of bank addresses and a read enable signal during a test mode and a pad configured to transfer the compressed data which are sequentially outputted from the read circuit to an outside of the semiconductor memory device.