Temperature Compensation Patents (Class 365/211)
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Patent number: 8446792Abstract: A temperature sensing circuit activates a sensing signal when sensing that a temperature inside a semiconductor integrated circuit is lower than a predetermined temperature. A heat generation control circuit activates a heat generation control signal when the sensing signal is activated. When the heat generation control signal is activated, a current is generated inside a memory circuit to raise the temperature inside the semiconductor integrated circuit.Type: GrantFiled: June 24, 2011Date of Patent: May 21, 2013Assignee: Panasonic CorporationInventors: Yoshifumi Fukushima, Shoji Sakamoto, Hiroyuki Sadakata, Kiyoto Ohta
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Patent number: 8438358Abstract: A system and method are provided for using a system-on-chip (SoC) memory speed control logic core to control memory maintenance and access parameters. A SoC is provided with an internal hardware-enabled memory speed control logic (MSCL) core. An array of SoC memory control parameter registers is accessed and a set of parameters is selected from one of the registers. The selected set of parameters is delivered to a SoC memory controller, to replace an initial set of parameters, and the memory controller manages an off-SoC memory using the delivered set of parameters.Type: GrantFiled: March 22, 2010Date of Patent: May 7, 2013Assignee: Applied Micro Circuits CorporationInventors: Waseem Saify Kraipak, George Bendak
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Patent number: 8437171Abstract: A circuit may include an array having a number of programmable impedance elements that may be placed into at least two different impedance states in a write operation; and a write circuit that applies temperature varying write conditions to the array in a write operation.Type: GrantFiled: December 29, 2010Date of Patent: May 7, 2013Assignee: Adesto Technologies CorporationInventor: Nad Edward Gilbert
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Patent number: 8432722Abstract: A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch the variable resistor; and a clamp voltage generator circuit operative to generate a clamp voltage required for access to the memory cell and applied to the first and second lines. The clamp voltage generator circuit has a temperature compensation function of compensating for the temperature characteristic of the first non-ohmic element.Type: GrantFiled: February 16, 2012Date of Patent: April 30, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Hiroshi Maejima
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Publication number: 20130083616Abstract: A temperature detection circuit of a semiconductor memory apparatus includes a fixed period oscillator, a temperature variable signal generating unit and a counting unit. The oscillator is configured to generate a fixed period oscillator signal when an enable signal is enabled. The temperature variable signal generating unit is configured to generate a temperature variable signal whose enable interval varies based on temperature variations, when the enable signal is enabled. The counting unit is configured to count the oscillator signal during the enable interval of the temperature variable signal to generate a temperature information signal.Type: ApplicationFiled: October 31, 2012Publication date: April 4, 2013Applicant: Hynix Semiconductor Inc.Inventor: Hynix Semiconductor Inc.
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Patent number: 8411505Abstract: The self-powered detection device comprises a Non-Volatile Memory (NVM) unit (52) formed at least by a NVM cell and a sensor which is activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester that transforms energy from said physical or chemical action or phenomenon into an electrical stimulus pulse, said NVM unit being arranged for storing in said NVM cell, by using the electrical power of said electrical stimulus pulse, a bit of information relative to the detection by said sensor, during a detection mode of the self-powered detection device, of at least one physical or chemical action or phenomenon applied to it with at least a given strength or intensity and resulting in a voltage stimulus signal provided between a set control terminal (SET) and a base terminal (SET *) of said NVM unit with at least a given set voltage.Type: GrantFiled: November 12, 2010Date of Patent: April 2, 2013Assignee: EM Microelectronic-Marin SAInventor: David A. Kamp
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Patent number: 8411518Abstract: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit.Type: GrantFiled: December 29, 2010Date of Patent: April 2, 2013Assignee: STMicroelectronics Pvt. Ltd.Inventors: Dhori Kedar Janardan, Rakesh Kumar Sinha, Sachin Gulyani
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Patent number: 8369170Abstract: A method for determining a temperature in a circuit comprises receiving a periodic signal. A frequency of the periodic signal is an increasing function of temperature. A number of oscillations of the periodic signal is determined during a time interval. A length of the time interval is an increasing function of temperature. The temperature is based on the determined number of oscillations.Type: GrantFiled: March 22, 2011Date of Patent: February 5, 2013Assignee: MOSAID Technologies IncorporatedInventor: Chung Zen Chen
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Patent number: 8363492Abstract: Provided is a delay adjustment device for adjusting delay of a strobe signal, which specifies when to read a data signal on a data line, with respect to the data signal in order to perform data transfer with an external memory. A testing unit 150 included in a delay adjustment unit is provided with a memory bandwidth monitoring unit 212 that monitors memory bandwidth in use on the data line used for data transfer with a memory circuit. The testing unit 150 performs delay adjustment when the memory bandwidth in use is lower than a predetermined threshold. Delay adjustment is performed by delaying the strobe signal from the data signal by a variety of predetermined delays and determining whether data transfer is successful at each delay, calculating an optimal delay, and thereafter delaying the strobe signal by the calculated delay.Type: GrantFiled: May 27, 2010Date of Patent: January 29, 2013Assignee: Panasonic CorporationInventors: Kouichi Ishino, Takeshi Nakayama, Masahiro Ishii
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Patent number: 8363443Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations that affect the operation of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point array comprising memory elements disposed among word lines and bit lines, where a parameter can affect the operating characteristics of a memory element. The integrated circuit further includes a data signal adjuster configured to modify the operating characteristic to compensate for a deviation from a target value for the operating characteristic based on the parameter. In some embodiments, the memory element, such as a resistive memory element, is configured to generate a data signal having a magnitude substantially at the target value independent of variation in the parameter.Type: GrantFiled: January 31, 2011Date of Patent: January 29, 2013Assignee: Unity Semiconductor CorporationInventors: Christophe J. Chevallier, Seow Fong Lim, Chang Hua Siau
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Patent number: 8359412Abstract: A data storage device includes a plurality of memory devices and a memory controller. The memory controller exchanges data with the plurality of memory devices via a plurality of channels and adjusts drive strength of the plurality of channels by referring to at least one of the number of the plurality of memory devices and current temperature.Type: GrantFiled: April 28, 2010Date of Patent: January 22, 2013Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Jonggyu Park, Jong-Min Kim
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Patent number: 8355288Abstract: A semiconductor memory device capable of measuring a temperature without the influence of noise includes a temperature sensing device for sensing a current temperature in response to a control signal, wherein the semiconductor memory device enters a power save mode for a predetermined time starting from an activation of the control signal and wherein the power save mode has substantially no power consumption. A method for driving a semiconductor memory device in accordance with the present invention includes sensing a current temperature in response to a control signal and entering a power save mode for a predetermined time starting from an activation of the control signal, wherein the power save mode has substantially no power consumption.Type: GrantFiled: September 22, 2011Date of Patent: January 15, 2013Assignee: Hynix Semiconductor Inc.Inventors: Kyung-Hoon Kim, Patrick B. Moran
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Patent number: 8351289Abstract: A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.Type: GrantFiled: December 30, 2009Date of Patent: January 8, 2013Assignee: Micron Technology, Inc.Inventors: Jason Brand, Jason Snodgress
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Patent number: 8351252Abstract: The data read circuit includes a variable current generation circuit and a data sensing circuit. The variable current generation circuit is configured to generate a variable current that varies in response to an external temperature. The data sensing circuit is configured to sense and amplify data on a bit line connected to a non-volatile memory cell according to the variable current and to configured to output the sensed and amplified data. The data sensing circuit controls a margin for sensing the data according to the variable current.Type: GrantFiled: September 3, 2010Date of Patent: January 8, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Hoe Ju Chung
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Patent number: 8351288Abstract: A flash storage device comprises: a memory module, for storing data; a control unit, electrically connected to the memory module, for accessing the data in the memory module; and a detecting unit, electrically connected to the control unit, for passing a temperature detecting result to the control unit, and the control unit determining whether a data protection operation is activated according to the temperature detecting result.Type: GrantFiled: December 22, 2010Date of Patent: January 8, 2013Assignee: Lite-On It Corp.Inventors: Song-Feng Tsai, Wen-Tsung Yang, Jen-Yu Hsu
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Patent number: 8339854Abstract: A method is for operating a nonvolatile memory device, where the memory device includes a memory cell array and a page buffer block. The method includes loading program data into the page buffer block, loading random sequence data into the page buffer block, generating randomized data by executing a logic operation, such as a bit-wise XOR operation, in the page buffer circuit on the program data and the first random sequence data, and programming the randomized data into the memory cell array.Type: GrantFiled: April 1, 2010Date of Patent: December 25, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Sangyong Yoon
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Patent number: 8339843Abstract: This disclosure describes write current temperature compensation techniques for use in programming a data storage device that includes one or more memory cells. The techniques may include programming a programmable magnetization state of a magnetoresistive device included within a resistance network based on a signal indicative of the operating temperature of a magnetic memory cell. The techniques may further include generating a write current having a magnitude that is determined at least in part by the programmable magnetization state of the magnetoresistive device. The techniques may further include supplying the write current to the magnetic memory cell for programming a programmable magnetization state of the magnetic memory cell.Type: GrantFiled: December 17, 2010Date of Patent: December 25, 2012Assignee: Honeywell International Inc.Inventor: Romney R. Katti
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Publication number: 20120320664Abstract: There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell.Type: ApplicationFiled: August 13, 2012Publication date: December 20, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Masao SHINOZAKI
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Patent number: 8331183Abstract: A memory apparatus includes a temperature detection block configured to detect temperature of an internal circuit and output a temperature detection signal, a current control block configured to receive the temperature detection signal and generate a pulse control signal, and a write driver configured to provide a program pulse having a compensated level and width to a memory cell in response to the pulse control signal.Type: GrantFiled: December 31, 2010Date of Patent: December 11, 2012Assignee: SK Hynix Inc.Inventors: Sung Yeon Lee, Hyun Joo Lee
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Patent number: 8325550Abstract: Auto-refresh of a semiconductor device may be controlled by setting the number of auto-refresh to be performed in a period of time, based on temperature, when an auto-refresh command is detected.Type: GrantFiled: January 20, 2010Date of Patent: December 4, 2012Assignee: Elpida Memory, Inc.Inventor: Kazuhiro Teramoto
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Patent number: 8325540Abstract: A variable reference voltage circuit for performing memory operation on non-volatile memory includes a multi-level voltage source and a selector circuit. The multi-level voltage source generates multiple voltages. The selector circuit includes a selector input and a selector output. The selector input is coupled to the multi-level voltage source to selectively couple any of the multiple voltages to the selector output. The selector output of the selector circuit is coupled to a non-volatile memory array to provide the NV memory array with a selectable program voltage for programming the NV memory array and a selectable erase voltage for erasing the NV memory array.Type: GrantFiled: May 27, 2011Date of Patent: December 4, 2012Assignee: Cypress Semiconductor CorporationInventors: Harold Kutz, Mark Rouse, Eric D. Blom
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Publication number: 20120287731Abstract: A semiconductor memory apparatus includes: a plurality of memory blocks; and a plurality of temperature sensors disposed adjacent to the respective memory blocks and configured to output a plurality of preliminary temperature sensing signals whose voltage levels are controlled in response to temperature change. A preliminary temperature sensing signal indicating the highest temperature among the plurality of preliminary temperature sensing signals is detected and used as a temperature sensing signal.Type: ApplicationFiled: May 10, 2012Publication date: November 15, 2012Applicant: SK HYNIX INC.Inventor: Ju Young KIM
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Patent number: 8310865Abstract: A semiconductor memory device comprises a memory cell, first and second voltage generating circuits generating first and second voltages, and a control circuit. A memory element and a diode included in the memory cell are connected in series between first and second lines. The first voltage has no temperature dependence, and the second voltage has a temperature dependence opposite to that of a forward voltage of the diode. The control circuit detects a resistance state of the memory element in accordance with a change in current flowing in the memory cell in a state where the first/second voltage is applied to the first/second in a read operation of the memory cell.Type: GrantFiled: October 6, 2010Date of Patent: November 13, 2012Assignee: Elpida Memory Inc.Inventor: Shuichi Tsukada
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Patent number: 8305830Abstract: A method for operating a volatile memory supplied with a supply signal arranged either as a first supply signal of a first supply signal source or a second supply signal of a second supply signal source. If an available first supply signal is present it is used otherwise the second supply signal is used. The supply signal is supplied, based on a switch position of a switching element to the volatile memory. During a detected interrupted first supply signal, the switch position of the switching element is for a predetermined period of time such that the supply signal is supplied to the volatile memory. After expiry of the predetermined period of time, the switch position of the switching element is predetermined such that the volatile memory is decoupled electrically from the supply signal.Type: GrantFiled: May 10, 2010Date of Patent: November 6, 2012Assignee: Continental Automotive GmbHInventors: Franz Kimmich, Andreas Lindinger, Gerhard Rombach
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Publication number: 20120275235Abstract: A method and apparatus for a memory device is provided. The memory device includes a memory cell, a memory controller, and a temperature-sensing device that detects a temperature. The memory controller enables adjusting, based on the detected temperature, a parameter associated with a bit-altering operation to the memory cell that changes a threshold voltage of the memory cell such that the threshold voltage to which the memory cell is changed to by the bit-altering operation is compensated for variations in temperature.Type: ApplicationFiled: April 29, 2011Publication date: November 1, 2012Applicant: Spansion LLCInventor: Allan PARKER
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Patent number: 8300486Abstract: A temperature detection circuit of a semiconductor memory apparatus includes a fixed period oscillator, a temperature variable signal generating unit and a counting unit. The oscillator is configured to generate a fixed period oscillator signal when an enable signal is enabled. The temperature variable signal generating unit is configured to generate a temperature variable signal whose enable interval varies based on temperature variations, when the enable signal is enabled. The counting unit is configured to count the oscillator signal during the enable interval of the temperature variable signal to generate a temperature information signal.Type: GrantFiled: December 30, 2009Date of Patent: October 30, 2012Assignee: Hynix Semiconductor Inc.Inventors: Je-Yoon Kim, Jong-Chern Lee
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Patent number: 8300488Abstract: A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.Type: GrantFiled: February 12, 2010Date of Patent: October 30, 2012Assignee: MOSAID Technologies IncorporatedInventor: Hong Beom Pyeon
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Patent number: 8300484Abstract: A semiconductor device comprises a memory cell array including memory cells, a first bit line transmitting data stored in a selected memory cells, a single-ended first sense amplifier amplifying a signal voltage of the first bit line and converting the voltage into an output current, a second bit line selectively connected to the first bit line via the first sense amplifier, a second sense amplifier determining a level of the signal voltage, and a sense amplifier control circuit detecting a temperature of the memory cell array during an operation and controlling an end of an activation period of the first and/or second sense amplifiers in accordance with a detection result of the temperature. In the semiconductor device, the sense amplifier control circuit controls to delay the end of the activation period at least at a predetermined high temperature indicated by the detection result relative to at an ordinary temperature.Type: GrantFiled: December 20, 2010Date of Patent: October 30, 2012Assignee: Elpida Memory, Inc.Inventor: Soichiro Yoshida
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Patent number: 8296540Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes tuning circuitry within the slave device such that the performance of the memory system is improved.Type: GrantFiled: February 25, 2008Date of Patent: October 23, 2012Assignee: Rambus Inc.Inventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Richard M. Barth, Paul G. Davis, Ely K. Tsern
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Patent number: 8289787Abstract: A semiconductor memory device, including a temperature detector configured to output a temperature detection signal in response to a temperature detected in a core region which includes a plurality of memory cells, and a programming voltage generator configured to generate a programming voltage in response to the temperature detection signal and output a generated programming voltage to the core region.Type: GrantFiled: December 21, 2010Date of Patent: October 16, 2012Assignee: Hynix Semiconductor Inc.Inventors: Ji-Hwan Kim, Seong-Je Park
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Patent number: 8284628Abstract: A voltage regulator includes a first transistor, a second transistor, a third transistor, a feedback unit, a comparison unit, a first control unit and a second control unit. The first transistor is controlled by the feedback unit and the comparison unit, for stabilizing the voltage of the output node. When the first control unit turns on the second transistor, the voltage of the output node rises. When the first control unit turns off the second transistor, it triggers the second control unit turning on the third transistor, so the first transistor is turned on completely. Therefore, when the third transistor is turned off, the first transistor can be controlled by the feedback unit and the comparison unit for stabilizing the voltage of the output node.Type: GrantFiled: February 9, 2011Date of Patent: October 9, 2012Assignee: Etron Technology, Inc.Inventors: Chun-Ching Hsia, Yen-An Chang, Der-Min Yuan
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Patent number: 8284624Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.Type: GrantFiled: January 22, 2010Date of Patent: October 9, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Heung Kim, Yong-Ho Cho, Ji-Hoon Lim, Seong-Jin Jang, Tae-Yoon Lee
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Patent number: 8279696Abstract: There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell.Type: GrantFiled: May 6, 2011Date of Patent: October 2, 2012Assignee: Renesas Electronics CorporationInventor: Masao Shinozaki
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Patent number: 8274846Abstract: A reference voltage generation circuit includes a first node settable at a reference voltage to be any one of a plurality of voltage levels, a second node set at a pre-charge voltage, first and second switches connected in series between the first and second nodes, a plurality of capacitors, each capacitor comprising a first end connected to a connection node between the first and second switches and a second end settable at an independent voltage level, a switch controller configured to turn off the first switch and turn on the second switch in an initial state, and then to turn off the second switch, and then to turn on the first switch, and a voltage controller configured to individually set a voltage at the second end of each capacitor after the first switch is turned on.Type: GrantFiled: January 5, 2010Date of Patent: September 25, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hidehiro Shiga, Daisaburo Takashima
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Publication number: 20120236670Abstract: Data is programmed into and read from a set of target memory cells. When reading the data, temperature compensation is provided. The temperature compensation is based on temperature information and the state of one or more neighbor memory cells. In one embodiment, when data is read from set of target memory cells, the system senses the current temperature and determines the differences in temperature between the current temperature and the temperature at the time the data was programmed. If the difference in temperature is greater than a threshold, then the process of reading the data includes providing temperature compensation based on temperature information and neighbor state information. In one alternative, the decision to provide the temperature compensation can be triggered by conditions other than a temperature differential.Type: ApplicationFiled: June 1, 2012Publication date: September 20, 2012Inventors: Gerrit Jan Hemink, Shinji Sato
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Patent number: 8271117Abstract: A manufacturing system which can restrain the margin of a semiconductor integrated circuit. The integrated circuit including a fixed circuit unit and a reconfigurable circuit unit outputs, to a configuration determining server, an operation time which was calculated by a detecting unit and a calculating unit. The configuration determining server, by using the operation time obtained from the integrated circuit, calculates performance data which indicates the characteristics of the fixed circuit unit, selects, based on the performance data, a piece of configuration information indicating a circuit configuration that is optimum for the processing of the reconfigurable circuit unit, and outputs the selected piece of configuration information. The integrated circuit builds a circuit in the reconfigurable circuit unit in accordance with the output piece of configuration information.Type: GrantFiled: November 14, 2008Date of Patent: September 18, 2012Assignee: Panasonic CorporationInventors: Takahiro Ichinomiya, Takashi Hashimoto
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Patent number: 8259488Abstract: A Phase-Change Memory (PCM) having a temperature detector with a dedicated PCM bit programmed to an amorphous state and a circuit to determine that the dedicated PCM bit is no longer in the amorphous state. A temperature exposure signal is asserted to indicate that a high temperature has altered PCM device programming integrity.Type: GrantFiled: May 11, 2009Date of Patent: September 4, 2012Assignee: Micron Technology, Inc.Inventors: Kerry Dean Tedrow, Jahanshir Javanifard
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Patent number: 8248856Abstract: The read channel of a solid state non-volatile memory may be configured to compensate for shifts in the threshold voltages of memory cells of the memory. A log of write time information and write temperature information from one or more write operations is stored in a data unit header. The read channel configuration, which may include reference voltages used for the read operation, is determined using the write time information and the write temperature information. Memory cells of the data unit are read using the configured read channel. A historical profile spanning multiple write operations may also be developed and used to configure the read channel.Type: GrantFiled: October 20, 2010Date of Patent: August 21, 2012Assignee: Seagate Technology LLCInventors: Ryan James Goss, Kevin Gomez
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Patent number: 8243531Abstract: There is provided a reference potential generating circuit of a semiconductor memory, including: a first MOS transistor group that includes a plurality of first MOS transistors that are connected in series; a second MOS transistor that is connected in series to the first MOS transistor group; a third MOS transistor that is connected in parallel to the circuit in which the first MOS transistor group and the second MOS transistor are connected in series, has a gate connected to a connection point of the first MOS transistor group and the second MOS transistor, and corrects a reference potential from a connection point of the first MOS transistors; and a fourth MOS transistor that is connected to the gate of the third MOS transistor, and decreases the potential of the gate of the third MOS transistor when a permission signal to supply power to the semiconductor memory is input.Type: GrantFiled: March 24, 2010Date of Patent: August 14, 2012Assignee: OKI Semiconductor Co., Ltd.Inventor: Akihiro Hirota
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Patent number: 8238185Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes: a voltage generator adjusting a DC voltage supplied into the semiconductor memory device according to a current temperature; and a control logic activating a temperature detection operation of the voltage generator and an adjustment operation of the DC voltage according to an operation mode, wherein the voltage generator adjusts the DC voltage according to offset information about the semiconductor memory device.Type: GrantFiled: October 29, 2009Date of Patent: August 7, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Seungjae Lee, Sungsoo Lee
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Patent number: 8238188Abstract: A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.Type: GrantFiled: February 14, 2011Date of Patent: August 7, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Akinobu Shirota, Kuninori Kawabata
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Patent number: 8228709Abstract: Disclosed is a resistance variable memory device including a memory cell connected with a bit line, a sense amplifier circuit sensing a voltage level on the bit line, and a pseudo-replica providing the sense amplifier circuit with a control signal that compensates for a drop in the sensing capacity of the sense amplifier circuit in relation to process, voltage and temperature (PVT) variations.Type: GrantFiled: November 3, 2009Date of Patent: July 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Youngdon Choi
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Patent number: 8228739Abstract: A circuit and corresponding method for providing a reference voltage are presented. The circuit includes a current source having a magnitude with positive temperature correlation connected to a node, and a diode element connected between the node and ground, where the reference voltage is provided from the node. The circuit also includes a variable resistance connected to receive an input indicative of the circuit temperature and through which the diode element is connected to the node. The value of the variable resistance is adjusted based upon the circuit temperature input. The circuit is useful for application as a peripheral circuitry, such as on a flash or other non-volatile memory and other circuits requiring an on-chip reference voltage source.Type: GrantFiled: July 18, 2011Date of Patent: July 24, 2012Assignee: SanDisk Technologies Inc.Inventors: Feng Pan, Yuxin Wang, Jonathan H. Huynh, Albert Chang, Khin Htoo, Qui Vi Nguyen
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Patent number: 8228736Abstract: A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a predetermined temperature range, the first memory controller controls the first memory so as not to perform a self refresh. When second temperature information received from the temperature sensor indicates that the detected temperature is in the predetermined temperature range, the first memory controller outputs a self refresh command to the first memory.Type: GrantFiled: December 7, 2009Date of Patent: July 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jae Hoon Joo, Sang Seok Kang, Jong Hyoung Lim
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Patent number: 8228720Abstract: A nonvolatile memory device may include a memory cell array having a plurality of nonvolatile memory cells arranged in a matrix including a plurality of rows of the nonvolatile memory cells. Each of a plurality of word lines may be coupled with nonvolatile memory cells of a respective row of the matrix. A row decoder may be coupled to the plurality of word lines with the row decoder being configured to disable at least one of the word lines using a row bias having a level that is adjusted responsive to changes in temperature. Such a nonvolatile memory device may operate with reduced standby currents.Type: GrantFiled: September 10, 2009Date of Patent: July 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Gil Choi, Hye-Jin Kim
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Patent number: 8225031Abstract: A memory apparatus enable operation which is adapted to environmental conditions. The memory apparatus includes a memory module that can store and incorporate environment-dependent optimal operating parameters. The memory module comprises a plurality of volatile memory devices and one or more non-volatile memory devices that store a plurality of environment-dependent device parameters for a device selected from the plurality of volatile memory devices. The stored parameters enable the selected device to function optimally in multiple environmental conditions.Type: GrantFiled: October 30, 2008Date of Patent: July 17, 2012Assignee: Hewlett-Packard Development Company, L.P.Inventors: Teddy Lee, Lidia Warnes, Dan Vu, Dennis Carr, Michael Bozich Calhoun
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Patent number: 8218375Abstract: An oscillation circuit includes an internal voltage generator and an oscillator. The internal voltage generator receives an external voltage and generates an internal voltage based on the external voltage. The internal voltage varies in linearly with an operational temperature. The oscillator generates a variable oscillation signal based on the internal voltage. A period of the variable oscillation signal varies in linearly with the operational temperature.Type: GrantFiled: January 19, 2010Date of Patent: July 10, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Doo Joo, Cheol-Ha Lee, Sang-Seok Lee
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Patent number: 8213255Abstract: Data is programmed into and read from a set of target memory cells. When reading the data, temperature compensation is provided. The temperature compensation is based on temperature information and the state of one or more neighbor memory cells. In one embodiment, when data is read from set of target memory cells, the system senses the current temperature and determines the differences in temperature between the current temperature and the temperature at the time the data was programmed. If the difference in temperature is greater than a threshold, then the process of reading the data includes providing temperature compensation based on temperature information and neighbor state information. In one alternative, the decision to provide the temperature compensation can be triggered by conditions other than a temperature differential.Type: GrantFiled: February 19, 2010Date of Patent: July 3, 2012Assignee: SanDisk Technologies Inc.Inventors: Gerrit Jan Hemink, Shinji Sato
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Patent number: 8213254Abstract: A nonvolatile memory device includes a memory cell array with a matrix of nonvolatile memory cells. The nonvolatile memory cells may store data using variable resistive elements. A plurality of bitlines are coupled to a plurality of nonvolatile memory cell arrays in the memory cell array. A column selection circuit selects among the bitlines in response to a column selection signal. A controller regulates a level of the column selection signal in response to a temperature signal from a temperature sensor. The temperature sensor may be configured to measure temperature outside the nonvolatile memory device to generate the temperature signal.Type: GrantFiled: July 17, 2009Date of Patent: July 3, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Gil Choi, Du-Eung Kim
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Patent number: 8208332Abstract: A compensation circuit includes a comparator and an emulation circuit. The comparator has a first terminal, and a second terminal for receiving a reference voltage. The emulation circuit is coupled to the first terminal of the comparator. The emulation circuit responses to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot.Type: GrantFiled: August 27, 2010Date of Patent: June 26, 2012Assignee: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Ji-Yu Hung, Chun-Hsiung Hung, Shuo-Nan Hung