Temperature Compensation Patents (Class 365/211)
Semiconductor (Class 365/212)
Magnetic (Class 365/213)
  • Semiconductor device having single-ended sensing amplifier
    Patent number: 7990793
    Abstract: A semiconductor device has a DRAM cell configured from an information charge accumulating capacitor and a memory cell selecting transistor, the threshold voltage value of a MOS transistor that constitutes a sense circuit is monitored, and the monitored threshold voltage value of the MOS transistor is converted through the use of a transfer ratio that is determined based on the capacitance of the information charge accumulating capacitor and the parasitic capacitance of the bit line. The converted voltage value is level-shifted so that the pre-charge voltage of a pre-charge circuit is a pre-set voltage, a current feeding capability is added to the level-shifted voltage value, and the voltage is fed as the pre-charge voltage.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: August 2, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Kazuhiko Kajigaya
  • Memory device and method thereof
    Patent number: 7986579
    Abstract: A device, and corresponding method, includes a temperature dependent bias generator to generate a voltage that is applied to a control gate of a sense amplifier. By applying the temperature dependent bias signal to the sense amplifier, a substantially temperature independent discharge time can be achieved at a sense node of a sense amplifier.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: July 26, 2011
    Assignee: Spansion LLC
    Inventor: Takao Akaogi
  • TEMPERATURE DETECTOR IN AN INTEGRATED CIRCUIT
    Publication number: 20110170366
    Abstract: A method for determining a temperature in a circuit comprises receiving a periodic signal. A frequency of the periodic signal is an increasing function of temperature. A number of oscillations of the periodic signal is determined during a time interval. A length of the time interval is an increasing function of temperature. The temperature is based on the determined number of oscillations.
    Type: Application
    Filed: March 22, 2011
    Publication date: July 14, 2011
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventor: Chung Zen Chen
  • On-chip temperature sensor
    Patent number: 7978556
    Abstract: A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant physical quantity changes in response to a temperature of the integrated circuit. A temperature sensor circuit generates a voltage that is linearly dependent on the temperature. A level generator circuit generates 2n?1 voltage levels from the reference voltage. A comparator circuit, such as an analog-to-digital circuit, compares the voltage from the temperature sensor to the 2n?1 voltage levels to determine which level is closest. An n-bit digital output of the resulting level is proportional to the temperature of the integrated circuit.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: July 12, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Macerola, Giulio-Giuseppe Marotta, Marco-Domenico Tiburzi
  • Wordline temperature compensation
    Patent number: 7974146
    Abstract: A nonvolatile memory includes a temperature dependent read window. One or more temperature compensated wordline voltage supply circuits provide temperature compensated wordline signal(s) to the nonvolatile memory. The temperature compensated wordline signals change as the temperature dependent read window changes.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: July 5, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Gerald J Barkley
  • Negative voltage generator for use in semiconductor memory device
    Patent number: 7969795
    Abstract: A negative voltage generator of a semiconductor memory device includes: a flag signal generation unit for receiving a temperature information code from an On Die Thermal Sensor (ODTS) to output a plurality of flag signals containing temperature information of the semiconductor memory device; and a negative voltage detection unit for detecting a negative voltage to output a detection signal for determining whether to pump a negative voltage, wherein a detection level of the negative voltage is changed according to the flag signals.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: June 28, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kang-Seol Lee
  • On die thermal sensor
    Patent number: 7965571
    Abstract: An on die thermal sensor (ODTS) for use in a semiconductor memory device includes: a temperature information code generation unit for sensing an internal temperature of the semiconductor memory device in response to first and second enable signals and for generating a temperature information code which includes the sensed temperature information; and a flag signal logic determination unit for generating a plurality of first flag signals having temperature information and determining whether the plurality of first flag signals have a predetermined logic level or a variable logic level in response to the first and second enable signals.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: June 21, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chun-Seok Jeong, Kee-Teok Park
  • Semiconductor device
    Patent number: 7961500
    Abstract: There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: June 14, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Masao Shinozaki
  • Method and apparatus for generating temperature-compensated read and verify operations in flash memories
    Patent number: 7957215
    Abstract: Methods and an apparatuses for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable current source, adjustable current sink, and a voltage converter, all operably coupled to a current sum node. The first current source generates a first current having a temperature coefficient substantially equal to a temperature coefficient of at least one-bit cell. The adjustable current source generates a second current that is substantially independent of a temperature change. The adjustable current sink sinks a third current that is substantially independent of a temperature change. The voltage converter is configured for generating a word-line signal having a word-line voltage proportional to a reference current, wherein the reference current comprises the first current, plus the second current, and minus the third current.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: June 7, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Drift compensation in a flash memory
    Patent number: 7957189
    Abstract: A plurality of memory cells are managed by obtaining values of one or more environmental parameters of the cells and adjusting values of one or more reference voltages of the cells accordingly. Alternatively, a statistic of at least some of the cells, relative to a single reference parameter that corresponds to a control parameter of the cells, is measured, and the value of the reference voltage is adjusted accordingly. Examples of environmental parameters include program-erase cycle count, data retention time and temperature. Examples of reference voltages include read reference voltages and program verify reference voltages. Examples of statistics include the fraction of cells whose threshold voltages exceed initial lower bounds or initial medians.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: June 7, 2011
    Assignee: SanDisk IL Ltd.
    Inventors: Meir Avraham, Amir Ronen
  • Three-dimensional memory-based three-dimensional memory module
    Patent number: 7952904
    Abstract: Three-dimensional-memory-based three-dimensional memory module (3D2-M2) is a three-dimensional memory module (3D-MM) comprising a plurality of three-dimensional mask-programmable memory (3D-mM) chips. It is an ultra-low-cost, ultra-large-capacity and small-form-factor memory module. By further incorporating a usage-control (UC) block, 3D2-M2 enables a pricing model more acceptable to consumers, i.e. the hardware is sold at a low initial selling price (ISP) and the user only pays for the selected usage(s).
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: May 31, 2011
    Inventor: Guobiao Zhang
  • Semiconductor device having variable parameter selection based on temperature and test method
    Patent number: 7953573
    Abstract: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, or a word line low voltage. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: May 31, 2011
    Assignee: Agersonn Rall Group, L.L.C.
    Inventor: Darryl G. Walker
  • Variable reference voltage circuit for non-volatile memory
    Patent number: 7952942
    Abstract: A variable reference voltage circuit for performing memory operation on non-volatile memory includes a multi-level voltage source and a selector circuit. The multi-level voltage source generates multiple voltages. The selector circuit includes a selector input and a selector output. The selector input is coupled to the multi-level voltage source to selectively couple any of the multiple voltages to the selector output. The selector output of the selector circuit is coupled to a non-volatile memory array to provide the NV memory array with a selectable program voltage for programming the NV memory array and a selectable erase voltage for erasing the NV memory array.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: May 31, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventors: Harold Kutz, Mark Rouse, Eric D. Blom
  • Multimedia three-dimensional memory module (M3DMM) system
    Patent number: 7952903
    Abstract: Multimedia three-dimensional memory module (M3DMM) is an ideal storage for pre-recorded multimedia library (PML). Among all semiconductor storage technologies, (3D)2-MM (i.e. three-dimensional memory-based M3DMM), particularly mask-programmable (3D)2-MM, has the largest storage capacity and is the only one that can store a pre-recorded movie library (PmL) at a reasonable price.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: May 31, 2011
    Inventor: Guobiao Zhang
  • REPLACING DEFECTIVE COLUMNS OF MEMORY CELLS IN RESPONSE TO EXTERNAL ADDRESSES
    Publication number: 20110122717
    Abstract: Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device in place of a defective column of memory cells of the memory device in response to receiving an address of the defective column of memory cells from the memory device. In another embodiment, a memory device has columns of memory cells and is configured to receive an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective column replaces the defective column. The non-defective column is a proximate non-defective column following the defective column in the sequence of columns that is available to replace the defective column.
    Type: Application
    Filed: January 31, 2011
    Publication date: May 26, 2011
    Inventors: Vishal Sarin, William H. Radke, Dzung H. Nguyen
  • Temperature compensation in memory devices and systems
    Patent number: 7948793
    Abstract: Devices, methods, and systems for temperature compensation in memory devices, such as resistance variable memory, among other types of memory are included. A memory device can include a table with an output that is used to create a multiplication factor for a current to compensate for temperature changes in the memory device, where the output depends on an operating temperature of the memory device and a difference in the current between a highest specified operating temperature and a lowest specified operating temperature of the memory device.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: May 24, 2011
    Assignee: Micron Technology, Inc.
    Inventors: John David Porter, Jennifer E. Taylor
  • Integrated circuit having a memory with process-voltage-temperature control
    Patent number: 7948819
    Abstract: Certain embodiments of the inventions provide an integrated circuit (IC) having a processor operatively coupled to a PVT (process-voltage-temperature) source and an adjustable memory. The processor receives from the source an input characterizing the present PVT condition and generates a command for the memory based on that input. In response to the command, the memory adjusts its internal circuit structure, clock speed, and/or operating voltage(s) to optimize its performance for the present PVT condition. Advantageously, the ability to adjust the memory so that it can maintain its functionality and deliver an acceptable level of performance under unfavorable PVT conditions provides additional flexibility in choosing circuit design options, which can produce area savings and/or increase the yield of acceptable ICs during manufacture.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: May 24, 2011
    Assignee: Agere Systems Inc.
    Inventors: Mathew R. Henry, Douglas D. Lopata, Richard J. McPartland, Hai Quang Pham, Wayne E. Werner
  • Memory device having strobe terminals with multiple functions
    Patent number: 7944761
    Abstract: A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device and transfer output data from the memory device. The write strobe transceivers transfer timing information of the input data. The read strobe transceivers transfer timing information of the output data. The memory device also has an auxiliary circuit for generating auxiliary information. The auxiliary information includes information different from the timing information of the input data and the output data. The auxiliary circuit uses the write and read transceivers to transfer the auxiliary information to and from the memory device.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: May 17, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Joo S. Choi, Troy A. Manning
  • Semiconductor integrated circuit device minimizing leakage current
    Patent number: 7940577
    Abstract: The semiconductor integrated circuit device includes a voltage control circuit that generates a control voltage for deactivating a field effect transistor by a gate voltage. The voltage control circuit controls a voltage so as to substantially minimize the leakage current which flows when the field effect transistor is inactive with respect to a device temperature.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: May 10, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kenjyu Shimogawa, Hiroshi Furuta
  • Semiconductor device
    Patent number: 7940112
    Abstract: To include a first X decoder constituted by a transistor whose off-leakage current has a first temperature characteristic, a pre-decoder circuit and a peripheral circuit constituted by a transistor whose off-leakage current has a second temperature characteristic, a power supply control circuit that inactivates the X decoder when a temperature exceeds a first threshold during a standby state, and a power supply control circuit that inactivates the pre-decoder and the peripheral circuit when a temperature exceeds a second threshold during the standby state. According to the present invention, whether power supply control is performed on a plurality of circuit blocks is determined based on different temperatures, therefore optimum power supply control can be performed on each of circuit blocks.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: May 10, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Shinya Okuno, Kiyohiro Furutani
  • Methods and apparatuses for controlling fully-buffered dual inline memory modules
    Patent number: 7940591
    Abstract: Methods and apparatuses are presented for controlling a fully buffered dual inline memory module. In one embodiment, the memory module may include at least two memory chips, a buffer coupled to the at least two memory chips (the buffer serially receiving data to be stored in the at least two memory chips), and a heat sink thermally coupled to the at least two memory chips and thermally coupled to the buffer such that heat generated by the buffer is coupled to a first memory chip within the at least two memory chips. The may be configured such that it operates at a higher temperature than the first memory chip and the refresh rate of the first memory chip may be adjusted when the temperature of the first memory chip is outside of a predetermined range.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: May 10, 2011
    Inventor: Paul Michael Mitchell, Jr.
  • Temperature detector in an integrated circuit
    Patent number: 7929366
    Abstract: A temperature detector in an integrated circuit comprises a temperature-dependent voltage generator, a ring oscillator, a timer and a clock-driven recorder. The temperature-dependent voltage generator is configured to generate at least one temperature-dependent voltage. The ring oscillator is configured to generate a clock signal, which is affected by one of the at least one temperature-dependent voltage. The timer is configured to generate a time-out signal, which is affected by one of the temperature-dependent voltage. The clock-driven recorder has a clock input terminal in response to the clock signal and time-out signal.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: April 19, 2011
    Assignee: Mosaid Technologies Incorporated
    Inventor: Chung Zen Chen
  • NONVOLATILE MEMORY DEVICE, STORAGE SYSTEM HAVING THE SAME, AND METHOD OF DRIVING THE NONVOLATILE MEMORY DEVICE
    Publication number: 20110080775
    Abstract: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells each having a resistance corresponding to one of a plurality of first resistance distributions, a temperature compensation circuit including one or more reference cells each having a resistance corresponding to one among one or more second resistance distributions, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit being adapted to supply compensation current to a sensing node, an amount of the compensation current varying based on the resistance of each reference cell, and the sense amplifier being adapted to compare the level of the sensing node with a reference level and to output a comparison result.
    Type: Application
    Filed: September 29, 2010
    Publication date: April 7, 2011
    Inventors: Jun-Soo Bae, Kwang-Jin Lee, Beak-Hyung Cho
  • Semiconductor memory device
    Patent number: 7920417
    Abstract: A semiconductor memory cell includes a plurality of memory cells configured to store data having polarity corresponding to a direction of current flowing in first and second driving lines, a current generator configured to generate a predetermined read current, apply the predetermined read current to the plurality of memory cells, and generate a data current corresponding variation of the read current according to the data and a current controller connected to a current path of the read current and configured to control a current amount of the read current.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: April 5, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Woo-Hyun Seo, Kwang-Myoung Rho
  • Semiconductor memory device changing refresh interval depending on temperature
    Patent number: 7916568
    Abstract: A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: March 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Akinobu Shirota, Kuninori Kawabata
  • Semiconductor memory device
    Patent number: 7911864
    Abstract: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix, a read unit which reads out data from the memory cells in the memory cell array, a write unit which writes data in the memory cells in the memory cell array, a read voltage generating unit which generates a read voltage and supplies the read voltage to the read unit, and a voltage control unit which controls the read voltage in accordance with temperatures.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: March 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mikihiko Itoh
  • Temperature compensation of memory signals using digital signals
    Patent number: 7911865
    Abstract: A temperature sensor generates a digital representation of the temperature of the integrated circuit. A logic circuit reads the digital temperature and generates a multiple bit digital representation of an operational voltage and a multiple bit digital representation of a timing signal, both being functions of the integrated circuit temperature. A voltage generator converts the digital representation of the operational voltage to an analog voltage that biases portions of the integrated circuit requiring temperature compensated voltages. In one embodiment, the temperature compensated voltages bias memory cells. A timing generator converts the multiple bit digital representation of the timing signal to a logic signal.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: March 22, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Michele Incarnati, Giovanni Santin
  • Core voltage discharger and semiconductor memory device with the same
    Patent number: 7907462
    Abstract: A core voltage discharger is capable of adjusting an amount of a current discharged according to temperature. The discharger for decreasing a level of a predetermined voltage receives temperature information from an on die thermal sensor and discharges a different amount of current in response to the temperature information.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: March 15, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Jin Byeon
  • Integrated circuit, memory cell array, memory module, and method of operating an integrated circuit
    Patent number: 7903454
    Abstract: According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: March 8, 2011
    Assignees: Qimonda AG, ALTIS Semiconductor, SNC
    Inventors: Dietmar Gogl, Rainer Leuschner, Ulrich Klostermann
  • Nonvolatile semiconductor memory device
    Patent number: 7898840
    Abstract: A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch the variable resistor; and a clamp voltage generator circuit operative to generate a clamp voltage required for access to the memory cell and applied to the first and second lines. The clamp voltage generator circuit has a temperature compensation function of compensating for the temperature characteristic of the first non-ohmic element.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: March 1, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Maejima
  • Semiconductor Device having variable parameter selection based on temperature and test method
    Publication number: 20110044118
    Abstract: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, or a word line low voltage. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.
    Type: Application
    Filed: December 10, 2009
    Publication date: February 24, 2011
    Inventor: Darryl G. Walker
  • Circuit and method for retrieving data stored in semiconductor memory cells
    Patent number: 7889586
    Abstract: A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: February 15, 2011
    Inventors: Luca Crippa, Giancarlo Ragone, Miriam Sangalli, Rino Micheloni
  • On-chip bias voltage temperature coefficient self-calibration mechanism
    Patent number: 7889575
    Abstract: Techniques and corresponding circuitry for deriving a supply a bias voltage for a memory cell array from a received reference voltage is presented. The circuit includes a voltage determination circuit, which is connected to receive the reference voltage and generate from it the bias voltage, a temperature sensing circuit, and a calibration circuit. The calibration circuit is connected to receive the bias voltage and to receive a temperature indication from the temperature sensing circuit and determine from the bias voltage and temperature indication a compensation factor that is supplied to the voltage determination circuit, which adjusts the bias voltage based upon the compensation factor.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: February 15, 2011
    Assignee: SanDisk Corporation
    Inventors: Yuxin Wang, Feng Pan, Byungki Woo, Trung Pham, Khin Htoo
  • Semiconductor memory device enhancing reliability in data reading
    Patent number: 7885132
    Abstract: An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: February 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Kubo, Takashi Itoh, Yasuhiro Kashiwazaki, Taku Ogura, Kiyohiro Furutani
  • VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM THEREOF
    Publication number: 20110026303
    Abstract: A nonvolatile memory device comprising: a plurality of memory banks, each of which operates independently and includes a plurality of resistance memory cells, each cell including a variable resistive element having a resistance varying depending on stored data; a plurality of global bit lines, each global bit line being shared by the plurality of memory banks; a temperature compensation circuit including one or more reference cells; and a data read circuit which is electrically connected to the plurality of global bit lines and performs a read operation by supplying at least one of the resistance memory cells with a current varying according to resistances of the reference cells.
    Type: Application
    Filed: October 8, 2010
    Publication date: February 3, 2011
    Inventors: Byung-Gil Choi, Beak-hyung Cho, Jun Soo Bae, Kwang-Jin Lee
  • Semiconductor memory device with temperature sensing device and operation thereof
    Patent number: 7881139
    Abstract: A semiconductor memory device includes a thermosensor that senses present temperatures of the device and confirms whether the temperature values are valid. The thermosensor includes a temperature sensing unit, a storage unit and an initializing unit. The temperature sensing unit senses temperatures in response to a driving signal. The storage unit stores output signals of the temperature sensing unit and outputs temperature values. The initializing unit initializes the storage unit after a predetermined time from an activation of the driving signal. A driving method includes driving the thermosensor in response to the driving signal, requesting a re-driving after a predetermined time from the activation of the driving signal, and re-driving the thermosensor in response to the driving signal input again.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: February 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyung-Hoon Kim, Patrick B. Moran
  • Semiconductor memory device and method for driving the same
    Patent number: 7876636
    Abstract: A semiconductor memory device performs a refresh operation stably even while a temperature continuously changes at near a specific temperature. The semiconductor memory device includes an on die thermal sensor (ODTS) and a control signal generator. The on die thermal sensor (ODTS) outputs a thermal code corresponding to a temperature of the semiconductor memory device. The control signal generator generates a self refresh control signal in response to the thermal code, wherein a state of the self refresh control signal does not change when the temperature variation is less than a predetermined value.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: January 25, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chun-Seok Jeong, Kee-Teok Park
  • Bias Temperature Instability-Influenced Storage Cell
    Publication number: 20110013445
    Abstract: In a method of using a memory cell employing a field effect transistor (FET), the FET is heated to a first temperature sufficient to support bias temperature instability in the FET. The bit line is driven to a high voltage state. The word line is driven to a predetermined voltage state that causes bias temperature instability in the FET. The temperature, the high voltage state on the bit line and the predetermined voltage state on the word line are maintained for an amount of time sufficient to change a threshold voltage of the FET to a state where a desired data value is stored on the FET. The FET is cooled to a second temperature that is cooler than the first temperature after the amount of time has expired.
    Type: Application
    Filed: July 17, 2009
    Publication date: January 20, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas M. Dewanz, Peter T. Freiburger, David P. Paulsen, John E. Sheets, II
  • Thermal code transmission circuit and semiconductor memory device using the same
    Patent number: 7864613
    Abstract: Disclosed are a thermal code transmission circuit and a semiconductor memory device using the same. The thermal code transmission circuit includes a select signal generator which generates a select signal in response to a first enable signal, a level signal generator which receives the first enable signal to generate a level signal, an update signal generator which receives the level signal and a first update signal to generate a second update signal, a latch unit which receives a thermal code in response to the second update signal and outputs the thermal code as an output thermal code, and a thermal code output unit which selectively outputs the output thermal code in response to the select signal.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: January 4, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sun Mo An, Youk Hee Kim
  • Semiconductor memory device
    Patent number: 7864614
    Abstract: A semiconductor memory device includes a memory cell array which includes a plurality of memory cells which are arrayed in a matrix at intersections between a plurality of word lines and a plurality of bit lines and a power supply circuit which includes a first band gap reference circuit which outputs a first output voltage, and a second band gap reference circuit which outputs a second output voltage having lower temperature characteristics than the first output voltage on a low temperature side, and generates a power supply voltage on the basis of the second output voltage at a time of a data write operation of the memory cells.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: January 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuro Midorikawa, Yasuhiko Honda, Gyosho Chin
  • Energy adjusted write pulses in phase-change memory cells
    Patent number: 7859894
    Abstract: An integrated circuit that includes a plurality of phase-change memory cells, at least one write pulse generator, and at least one temperature sensor. The plurality of phase-change memory cells are each capable of defining at least a first and a second state. The write pulse generator generates a write pulse for the plurality of phase-change memory cells. The temperature sensor is capable of sensing temperature. The write pulse generator adjusts the write pulse for at least some of the phase-change memory cells in accordance with the temperature sensed by the temperature sensor.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: December 28, 2010
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Zaidi Shoaib
  • Circuit and method for controlling refresh periods in semiconductor memory devices
    Patent number: 7843752
    Abstract: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: November 30, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Sook Noh, Young-Hun Seo, Jong-Hyun Choi
  • Integrated circuit including memory refreshed based on temperature
    Patent number: 7843753
    Abstract: An integrated circuit includes an array of memory cells and a first circuit. The array includes word lines. Each word line is coupled to a plurality of memory cells. The first circuit is configured to refresh memory cells along a first number of word lines in response to a refresh command. The first number of word lines is based on a sensed temperature.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: November 30, 2010
    Assignee: Qimonda AG
    Inventors: Peter Mayer, Nicholas Heath, Rom-Shen Kao, Jason Parrish
  • Internal voltage generating circuit and semiconductor memory device using the same
    Patent number: 7839700
    Abstract: An internal voltage generating circuit includes a voltage divider for generating a level signal by voltage-dividing first internal voltage, a pull-down signal generator for generating a pull-down signal, which has a level adjusted according to a temperature, in response to the level signal, a pull-up signal generator for generating a pull-up signal, which has a level adjusted according to the temperature, in response to the level signal, and a driving unit for driving second internal voltage in response to the pull-down signal and the pull-up signal. Driving force of the driving unit for driving the second internal voltage is changed according to the temperature.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: November 23, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Gyo Soo Chu
  • VOLTAGE GENERATION CIRCUIT AND NONVOLATILE MEMORY DEVICE INCLUDING THE SAME
    Publication number: 20100284226
    Abstract: A voltage generation circuit for providing a read or verification voltage of a nonvolatile memory device includes a first voltage generation unit configured to output a first voltage using a first reference voltage, a bouncing compensation unit configured to change the first voltage using a first control signal, the first voltage, and a voltage of a global source line when a read or verification operation is performed on the nonvolatile memory device, and to output a changed first voltage as a second voltage, a second reference voltage generation unit configured to generate a second reference voltage, and an amplification unit configured to amplify a difference between the second voltage and the second reference voltage according to a set resistance ratio and to output a result of the amplification as a third voltage.
    Type: Application
    Filed: February 9, 2010
    Publication date: November 11, 2010
    Inventor: Yu Jong Noh
  • METHODS AND APPARATUS FOR EXTENDING THE EFFECTIVE THERMAL OPERATING RANGE OF A MEMORY
    Publication number: 20100271894
    Abstract: Apparatus and systems are provided for thermal regulation of a memory integrated circuit (“IC”). The apparatus and systems may include a thermal sensor on a memory IC, and a heating element coupled to the thermal sensor. The heating element is adapted to heat the memory IC in response to a signal from the thermal sensor. Other aspects are also provided.
    Type: Application
    Filed: July 1, 2010
    Publication date: October 28, 2010
    Inventors: Tyler Thorp, Roy E. Scheuerlein
  • ANALOG READ AND WRITE PATHS IN A SOLID STATE MEMORY DEVICE
    Publication number: 20100271872
    Abstract: A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage.
    Type: Application
    Filed: July 2, 2010
    Publication date: October 28, 2010
    Inventors: Frankie F. Roohparvar, Vishal Sarin
  • Stable temperature adjustment for refresh control
    Patent number: 7821860
    Abstract: A refresh control circuit and method generates a refresh signal in response to one of a plurality of clock signals and a temperature signal. The clock signals and temperature signal may be synchronized to prevent an incomplete refresh operation at a trip point of a temperature sensor. In one embodiment, a pulse generator may generate a temperature sensor enable signal in response to the clock signals when the clock signals are synchronized. In other embodiments, the temperature signal may be latched to prevent a transition in the refresh signal during a refresh operation. The temperature signal may be latched in response to one of the clock signals or the refresh signal.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: October 26, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hiu-Kap Yang, Myung-Gyoo Won
  • Drift compensation in a flash memory
    Patent number: 7817469
    Abstract: A plurality of memory cells are managed by obtaining values of one or more environmental parameters of the cells and adjusting values of one or more reference voltages of the cells accordingly. Alternatively, a statistic of at least some of the cells, relative to a single reference parameter that corresponds to a control parameter of the cells, is measured, and the value of the reference voltage is adjusted accordingly. Examples of environmental parameters include program-erase cycle count, data retention time and temperature. Examples of reference voltages include read reference voltages and program verify reference voltages. Examples of statistics include the fraction of cells whose threshold voltages exceed initial lower bounds or initial medians.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: October 19, 2010
    Assignee: SanDisk IL Ltd.
    Inventors: Meir Avraham, Amir Ronen
  • System and method for asynchronous clock regeneration
    Patent number: 7818528
    Abstract: The present invention is a method of asynchronous clock regeneration. The method includes synchronizing a first write pointer and a second write pointer, the first write pointer being an offline write pointer, the second write pointer being an online write pointer. The method further includes swapping at least one bit from the first write pointer with at least one bit of the second write pointer when the bits are static. The method further includes regenerating a DQS (Data Strobe Signal) clock.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: October 19, 2010
    Assignee: LSI Corporation
    Inventor: Thomas Hughes