Abstract: A signal processing circuit includes a first signal latch circuit, a second signal latch circuit, and a decoder. The first signal latch circuit receives a command address signal and is driven by an even clock; the second signal latch circuit receives the command address signal and is driven by an odd clock; and the decoder is connected to the first signal latch circuit and the second signal latch circuit, and outputs a control signal. Both the even clock and the odd clock have a frequency equal to that of a reference clock, and both the even clock and the odd clock have a rising edge aligned with a rising edge of the reference clock.

Abstract: A memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips include a first storage chip set and a second storage chip set, the storage chips in the first storage chip set are configured to perform information interaction with the control chip by adopting a first clock signal, the storage chips in the second storage chip set are configured to perform information interaction with the control chip by adopting a second clock signal, and phase of the first clock signal is different from phase of the second clock signal.

Abstract: A semiconductor memory device includes a mode register set and a clock correction circuit. The mode register set stores a first control code set. During a duty training interval based on a duty training command, the clock correction circuit may divide the duty training interval into a first interval, a second interval and a third interval which are consecutive, may correct a phase skew of a first clock signal and a third clock signal during the first interval, may correct a phase skew of a second clock signal and a fourth clock signal during the second interval, and may correct a phase skew of the first clock signal and the fourth clock signal during the third interval. The semiconductor memory device may enhance signal integrity of clock signals by correcting duty errors and phase skews of the clock signals having multi-phases during the duty training interval.

Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.

Abstract: A semiconductor device includes: a first transfer path outputting a first preliminary signal; a second transfer path outputting a second preliminary signal; a third transfer path outputting a third preliminary signal; a first calibration circuit generating a first calibration code corresponding to a difference in delay values between the first transfer path and a selected transfer path having a largest delay value among the first to third transfer paths; a second calibration circuit generating a second calibration code corresponding to a difference in delay values between the second transfer path and the selected transfer path; a third calibration circuit generating a third calibration code corresponding to a difference in delay values between the third transfer path and the selected transfer path; a first delay control circuit generating a first signal; a second delay control circuit generating a second signal; and a third delay control circuit generating a third signal.

Abstract: A serial NOR memory device receives serial input data using a single data rate (SDR) mode and transmits serial output data using a double data rate (DDR) mode. In some embodiments, a serial NOR memory device includes an input-output circuit including a transceiver coupled to receive a clock signal and serial input data and to provide serial output data. The transceiver is configured to receive serial input data using the single data rate mode and is configured to transmit serial output data using the double data rate mode.

Abstract: A semiconductor system includes a memory controller and a memory apparatus. The memory controller provides at least first to third command address signals. The memory apparatus performs a burst read operation based on the first and second command address signals, and terminates the burst read operation by receiving the third command address signal twice. The memory apparatus continuously initializes an internal circuit that is performing the burst read operation in a section the third command address signal is received twice.

Abstract: A non-volatile semiconductor memory device including: a first pad transmitting/receiving a data signal transmitted via a first signal line to/from a memory controller; a second pad transmitting/receiving a strobe signal transmitted via a second signal line to/from the memory controller, the strobe signal specifying a timing of transmitting/receiving the data signal; and a third pad receiving an output instruction signal via a third signal line from the memory controller, the output instruction signal instructing a transmission of the data signal; wherein the non-volatile semiconductor memory device outputs the data signal from the first pad to the memory controller, outputs the strobe signal from the second pad to the memory controller, performs a first calibration operation calibrating the data signal, and performs a second calibration operation calibrating the strobe signal, based on a toggle timing of the strobe signal associated with the output instruction signal.

Abstract: Disclosed are devices, systems and methods for improving a quality of service of an adaptive soft decoder in a non-volatile memory device. An example method includes selecting, based on current operating conditions of the non-volatile memory device, a first decoder parameter set from an ordered plurality of decoder parameter sets, each decoder parameter set corresponding to a distinct operating condition of the non-volatile memory device and comprising parameters related to a soft decoding operation; performing, based on the first decoder parameter set, the soft decoding operation; upon a determination that the soft decoding operation has succeeded, reordering the ordered plurality of decoder parameter sets to place the first decoder parameter set at a start of the ordered plurality of decoder parameter sets, and otherwise, performing the soft decoding operation based on a second decoder parameter set selected from the ordered plurality of decoder parameter sets.

Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.

Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

Abstract: A memory access interface device that includes a clock generation circuit that generates reference clock signals according to a source clock signal and access signal transmission circuits are provided. Each of the access signal transmission circuits includes a first and a second clock frequency division circuits, a phase adjusting circuit and a duty cycle adjusting circuit. The first and the second clock frequency division circuits sequentially divide the frequency of one of the reference clock signals to generate a first and a second frequency divided clock signals respectively. The phase adjusting circuit adjusts the phase of an access signal according to the second frequency divided clock signal to generate a phase-adjusted access signal. The duty cycle adjusting circuit adjusts the duty cycle of the phase-adjusted access signal to be a half of the time period to generate an output access signal to access a memory device.

Abstract: An output control circuit may include a period setting signal generation unit configured to output a setup signal enabled during a designated period, in response to a delayed locked loop (DLL) locking signal and an output enable reset signal. The output control circuit may also include a clock division unit configured to divide an internal clock at a preset division ratio in response to the setup signal, and output a divided clock. In addition, the output control circuit may include a shift unit configured to shift the setup signal by a preset first time in response to the divided clock, and output a first delayed setup signal. Further, the output control circuit may include an output unit configured to receive and process the first delayed setup signal in response to the divided clock, and output the output enable reset signal.

Abstract: A multiport SRAM has an array of cells, a first port, and a second port. During a period of different row addresses for the ports, the first port uses first word lines and first bit lines. The second port uses second word lines and second bit lines. In response to the second port switching to the same address as the first port to make a row match, the second port and the first port use the first plurality of word lines, but the first port uses the first plurality of bit lines and the second port uses the second plurality of bit lines. If the row match is removed by the first port changing row addresses, a correlation swap is performed so that the first port performs accesses using the second word lines and bit lines and the second port performs accesses using the first word lines and bit lines.

Abstract: A distributed phase-correction circuit is described. This distributed phase-correction circuit reduces jitter in a delay line by averaging edge delay through local feedback of signals internal to the delay line. In particular, the distributed phase-correction circuit includes a delay line with multiple cascaded first phase-alignment elements that each delay the input signal by a fraction of the period (i.e., that perform distributed phase correction) based on feedback signals from a second delay line.

Abstract: A memory controlling method adapted for driving a memory within a computer system is disclosed. When the computer system is booted, the memory is driven and tested via the BIOS. The memory controlling method performs tests on multiple controlling signals of the memory. The memory controlling method includes steps of: detecting an active window of each controlling signal; determining whether the active windows is larger than a predetermined window; performing a parameter adjustment on the controlling signals if one of the active windows is smaller than the predetermined window; performing a phase range test between two of the control signals if the active windows are larger than the predetermined window; performing a phase adjustment on the active windows of the controlling signals if the controlling signals fails in the phase range test; and driving the memory according to the adjusted controlling signals.

Abstract: A phase-locked loop includes a first semiconductor layer and a second semiconductor layer spaced apart from the first semiconductor layer. The first semiconductor layer has formed thereon a phase frequency detector circuit having a reference frequency input, a feedback frequency input, an up output and a down output, a charge pump circuit having a first input coupled to the up output and a second input coupled to the down output, and an output, and a loop filter circuit coupled to the charge pump. The second semiconductor layer has formed thereon a voltage controlled oscillator having an input and an output, and a feedback frequency divider circuit having an input coupled to the output of the voltage controlled oscillator and an input. A first interlayer via couples the loop filter circuit to the input of the voltage controlled oscillator circuit. A second interlayer via couples the output of the feedback frequency divider circuit to the feedback input of the phase frequency detector.

Abstract: A memory controller transmits a data signal, a data strobe signal and a mask signal to a memory, wherein each transition of the data strobe signal indicates a sample point for the data signal and the mask signal indicates a validity of the data signal. A mask signal training procedure is carried out comprising three steps. Writing first and second values to the memory for a predetermined plurality of transitions of the data strobe signal with the mask signal set to indicate that the first data signal is valid and the second data signal is valid except for a selected transition of the predetermined plurality. Reading from the memory for the predetermined plurality of transitions of the data strobe signal. Determining a timing offset for the mask signal for which the value read at the selected transition matches the first value.

Abstract: A method and an apparatus for testing a memory are provided, and the method is adapted for an electronic apparatus to test the memory. In the method, a left edge and a right edge of a first waveform of a clock signal for testing the memory are scanned to obtain a maximum width between two cross points of the left edge and the right edge. A central reference voltage of a data signal outputted by the memory is obtained, and a data width between two cross points of the central reference voltage and a left edge and a right edge of a second waveform of the data signal is obtained. Whether a difference between the data width and the maximum width is greater than a threshold is determined; if the difference is greater than the threshold, the memory is determined to be damaged.

Abstract: A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.

Abstract: Systems and methods are provided for timing read operations with a memory device. A system for timing read operations with a memory device includes a gating circuit configured to receive a timing signal from the memory device. The gating circuit is further configured to pass through the timing signal as a filtered timing signal during a gating window. The gating window is generated by the gating circuit based on a control signal. The system further includes a timing control circuit configured to generate the control signal after receiving a read request from a memory controller. The timing control circuit is further configured to adjust the control signal to account for temporal variations in the timing signal from the memory device.

Abstract: A semiconductor memory device includes a delay locked loop configured to generate a delay locked loop (DLL) clock signal by delaying an external clock signal by a first delay time and generate a feedback clock signal by delaying the DLL clock signal by the second delay time, wherein the first delay time corresponds to a phase difference between the external clock signal and the feedback clock signal and an output enable control circuit configured to generate an output enable signal in response to CAS latency information and the first and second delay times after the delay locked loop performs a locking operation.

Abstract: According to at least one example embodiment, a method and corresponding system for calibrating an amplifier offset include applying an input value to both input leads of an amplifier. The amplifier includes one or more digital-to-analog converters (DACs) used to calibrate an offset of the amplifier. A digital value, provided as input to the DAC, is updated over a number of iterations, by a control logic coupled to the amplifier, based on an output of the amplifier. A final value of the digital value being updated, e.g., associated with the last iteration, is employed as input to the DAC of the one or more DACs in the amplifier for calibrating the offset of the amplifier during a data reception phase.

Abstract: A method is provided for relaying data to a memory array operating in synchronization with a clock signal having a first transition edge. A data strobe signal having a second transition edge corresponding to the first transition edge is provided. A first signal is provided. The data is latched into the first signal at a first time point lagged behind the first transition edge by a first time interval until a second time point in response to the first transition edge for relaying the data of the first signal to the memory array when the second transition edge appears earlier than the first transition edge.

Abstract: A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for byte lanes. In the system, control settings for the read data delay circuits for providing CAS latency compensation are determined and set using controller circuits according to a dynamic calibration procedure performed from time to time. In the system, determining and setting the control settings for the read data delay circuits for providing CAS latency compensation is performed independently and parallely in each of a plurality of byte lanes.

Abstract: A semiconductor apparatus includes: a clock receiving unit configured to receive an external clock signal and output the received clock signal as a reference clock signal; a delay locked loop (DLL) configured to delay the reference clock signal by a variable delay amount and generate a data latch clock signal; a data receiving unit configured to receive external data in synchronization with the data latch clock signal and output the received data as internal data; and a determination unit configured to detect a phase difference between the reference clock signal and the data latch clock signal and generate a determination signal, when the DLL is locked.

Abstract: A device includes an output circuit, a DLL (Delay Locked Loop) circuit including a first delay line receiving a first clock signal and outputting, in response to receiving the clock signal, a second clock signal supplied to the output circuit, and an ODT (On Die Termination) circuit receiving an ODT activation signal and outputting, in response to receiving the ODT activation signal, an ODT output signal supplied to the output circuit to set the output circuit in a resistance termination state, and the ODT circuit including a second delay line configured to be set by the DLL circuit in an equivalent delay amount that is equivalent to a delay amount of the first delay line, the ODT output signal being, in a first time-period during which the ODT activation signal is in an active state, generated by being conveyed via the second delay line in which the equivalent delay amount has been set.

Abstract: A secondary memory unit includes a first substrate that has a non-volatile memory unit mounted thereon that is configured to receive power from an external power supply. A second substrate has an energy storage and supply medium mounted thereon. An energy transfer medium is provided that electrically connects the first substrate and the second substrate. The energy storage and supply medium is configured to supply an operating power to the non-volatile memory unit when power from the external power supply to the non-volatile memory unit is cut off.

Abstract: Such a device is disclosed that includes a clock generation circuit generating a first clock signal and having an output node, and a drive circuit coupled to the output node of the clock generation circuit. The clock generation circuit outputs the first clock signal from the output node to the drive circuit in a clock output mode, fixes a potential of the output node to a first level in a first clock stop mode, and fixes the potential of the output node to a second level that is different from the first level in a second clock stop mode.

Abstract: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.

Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.

Abstract: A write leveling calibration system and method for double data-rate dynamic random access memory includes performing write leveling at two different frequencies to determine to which of two successive rising clock cycle edges each data strobe signal would be aligned as a result of applying the write leveling delay determined by the write-leveling procedure. The determination can then be used to ensure that the data strobe signals of all source synchronous groups are aligned with the same edge of the clock signal.

Abstract: A parallel-serial conversion circuit includes an adjustment circuit that receives a parallel input signal having a plurality of bits and generates and outputs a parallel output signal having a plurality of bits. A conversion circuit coupled to the adjustment circuit generates a plurality of clock signals having mutually different phases with respect to a reference clock signal on the basis of the reference clock signal and serially selects the plurality of bits of the parallel output signal in accordance with the generated plurality of clock signals to convert the parallel output signal to serial 1-bit output signals. The adjustment circuit adjusts the output timing of each of the plurality of bits of the parallel output signal in time unit of half of one cycle of the reference clock signal.

Abstract: A semiconductor memory device includes a bit line; two or more word lines; and a memory cell including two or more sub memory cells that each include a transistor and a capacitor. One of a source and a drain of the transistor is connected to the bit line, the other of the source and the drain of the transistor is connected to the capacitor, a gate of the transistor is connected to one of the word lines, and each of the sub memory cells has a different capacitance of the capacitor.

Abstract: A method of monitoring signals is disclosed, wherein a plurality of command signals and address signals are consecutively expressed, as a measurement target. The method includes setting a strobe timing that has a predetermined initial value; calculating an error rate by monitoring the plurality of command signals, in accordance with the strobe timing; monitoring the plurality of address signals, and calculating a burst rate from a difference between the consecutive plurality of address signals, in accordance with the strobe timing; identifying timing where the calculated error rate and calculated burst rate are both optimized; and in the event the timing where both the calculated error rate and calculated burst rate are optimized cannot be identified, altering a predetermined value of the set strobe timing, and repeating the calculating, monitoring, and identifying.

Abstract: An elapsed time with respect to a programming operation on a memory cell of a nonvolatile memory is determined, a read voltage is adjusted based on the determined elapsed time and a read operation is performed on the memory cell using the adjusted read voltage. Determining the elapsed time may be preceded by performing the programming operation in response to a first access request and determining the elapsed time may include determining the elapsed time in response to a second access request. Memory systems supporting such operations are also described.

Abstract: A semiconductor memory apparatus includes a shared pad which is configured to output a read operation control signal in a read operation and receive a write operation control signal in a write operation.

Abstract: A method of testing a semiconductor memory device includes writing first data to a memory cell array in the semiconductor memory device, loading second data from the memory cell array onto a plurality of data pads of the semiconductor memory device, rewriting the second data to the memory cell array, and outputting test result data through one or more test pads. The first data is received from an external device through the one or more test pads, which correspond to one or more of the plurality of data pads. The test result data is based on the rewritten data in the memory cell array.

Abstract: A method of monitoring signals is disclosed, wherein a plurality of command signals and address signals are consecutively expressed, as a measurement target. The method includes setting a strobe timing that has a predetermined initial value; calculating an error rate by monitoring the plurality of command signals, in accordance with the strobe timing; monitoring the plurality of address signals, and calculating a burst rate from a difference between the consecutive plurality of address signals, in accordance with the strobe timing; identifying timing where the calculated error rate and calculated burst rate are both optimized; and in the event the timing where both the calculated error rate and calculated burst rate are optimized cannot be identified, altering a predetermined value of the set strobe timing, and repeating the calculating, monitoring, and identifying.

Abstract: In a training mode, per-bit de-skew (PBDS) values for a datamask signal in a synchronous dynamic random access memory are iteratively adjusted in conjunction with writing test patterns to the memory and reading back test patterns from the memory until optimum datamask PBDS values are determined.

Abstract: Disclosed herein is a device that includes: a frequency division circuit that divides a frequency of a first clock signal to generate a second clock signal; a first logic circuit that receives a first chip select signal and the second clock signal to generate a second chip select signal; and a command generation circuit that is activated based on the second chip select signal, and generates a second command signal based on a first command signal.

Abstract: A write leveling calibration system and method for double data-rate dynamic random access memory includes performing write leveling at two different frequencies to determine to which of two successive rising clock cycle edges each data strobe signal would be aligned as a result of applying the write leveling delay determined by the write-leveling procedure. The determination can then be used to ensure that the data strobe signals of all source synchronous groups are aligned with the same edge of the clock signal.

Abstract: Systems and methods are disclosed relating to semiconductor memory devices. According to some exemplary implementations, there are provided innovations associated with power and ground pads in devices such as static random access memory (“SRAM”) devices and dynamic random access memory (“DRAM”) devices. Moreover, the systems and/or methods may include features such as minimization of simultaneous switching outputs (SSO) effects relating to echo clock circuitry.

Abstract: Power management of an embedded dynamic random access memory (eDRAM) by receiving an eDRAM power state transition event and determining both the current power state of the eDRAM and the next power state of the eDRAM from the power states of: a power-on state, a power-off state, and a self-refresh state. Using the current power state and the next power state to determine whether a power state transition is required, and, in the case that a power state transition is required, transition the eDRAM to the next power state. Power management is achieved because transitioning to a power-off state or self-refresh state reduces the amount of power consumed by the eDRAM as compared to the power-on state.

Abstract: In a training mode, per-bit de-skew (PBDS) values for a datamask signal in a synchronous dynamic random access memory are iteratively adjusted in conjunction with writing test patterns to the memory and reading back test patterns from the memory until optimum datamask PBDS values are determined.

Abstract: Disclosed herein is a device that includes a command decoder and a latency counter. The command decoder generates a first internal command in response to a first internal clock signal. The latency counter includes: a gate control signal generation unit generating output gate signals in response to a second internal clock signal; delay circuits each receiving an associated one of the output gate signals and generating an associated one of input gate signals; and a command signal latch unit fetching the first internal command in response to one of the input gate signals and outputting the first internal command in response to one of the output gate signals. Each of the delay circuit includes a first delay element that operates on a first power supply voltage and a second delay element that operates on a second power supply voltage different from the first power supply voltage.

Abstract: A memory controller is connected to a double-data-rate dynamic random access memory (DDR DRAM) and an accessing unit. The memory controller includes: a processing unit, configured to receive a system address generated by the accessing unit; and a mapping unit, located in the processing unit, configured to convert the system address to a memory address and transmitting the memory address to the DDR DRAM. When a burst length of the DDR DRAM is L and L=2x (where L and x are positive integers), an (x+1)th bit of the memory address from a least significant bit (LSB) is included in a bank group address of the memory address.

Abstract: A method for outputting data in a semiconductor device includes receiving an external clock signal, synchronizing, in a delay locked loop of the semiconductor device, a first internal clock signal to the external clock signal during a read period, synchronizing, in the delay locked loop, a second internal clock signal to the external clock signal during an active period, the second internal clock signal having a period longer than the first internal clock signal, and outputting data synchronized with the first internal clock signal during the read period.

Abstract: Multiple timing reference signals (e.g., clock signals) each cycling at the same frequency are distributed in a fly-by topology to a plurality of memory devices in various embodiments are presented. These multiple clock signals each have a different phase relationship to each other (e.g., quadrature). A first circuit receives a first of these clocks as a first timing reference signal. A second circuit receives a second of these clocks as a second timing reference signal. A plurality of receiver circuits receive signals synchronously with respect to the first timing reference signal and the second timing reference signal, such that a first signal value is resolved using the first timing reference signal and a second signal value is resolved using the second timing reference signal.