Abstract: A delay control circuit includes a delay locked loop configured to delay an external clock by a first delay amount and generate an internal clock, a first delay unit configured to delay an input signal by a first delay amount, a first replica delay unit having a replica delay amount corresponding to a modeled delay amount of a system, a delay control unit configured to control the replica delay amount in response to a latency of an input signal, a measurement unit configured to measure the first delay amount and the controlled replica delay amount and generate path information, an operation unit configured to generate delay information in response to the latency of the input signal and the path information, and a latency delay unit configured to delay the delayed input signal of the first delay unit by the delay information and generate a latency signal.

Abstract: To suppress a timing window from being narrowed undesirably by the harmonic component of a signal output from a semiconductor component without imposing a burden on the semiconductor component that controls access. A capacitor element is arranged in series with a specific transmission path branching from a predetermined node of a signal transmission path and reaching to a ground plane, the signal transmission path supplying an enable control signal that indicates the validity of a clock signal and a command and address signal output from a semiconductor component that controls access on a substrate to another semiconductor component to be accessed on the substrate. The capacitor element functions as a short-circuit path to the ground plane for the harmonic component of the enable control signal and makes smaller the through rate and makes larger the timing window of the enable control signal compared to those when the capacitor element is not provided.

Abstract: Methods and systems for detection and correction of timing signal drift in memory systems are provided. A start time and an end time of a first time interval is determined with control circuitry such that a last falling edge in a first of a plurality of data strobe sequences received from the memory occurs outside of the first time interval. A start time and an end time of a close-enable time interval is adjusted based at least in part on determining whether a second of the plurality of data strobe sequences occurs within the first time interval. Sampling of data received from the memory is disabled in response to determining that the last falling edge in the second received data strobe sequence occurs within the close-enable time interval.

Abstract: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.

Abstract: The invention provides an electronic apparatus. The electronic apparatus includes a Dynamic Random Access Memory (DRAM) and a DRAM controller. The DRAM receives at least one control and address signal and a clock signal, delays the clock signal by a predetermined value to obtain a delayed clock signal, samples the control and address signal according to the clock signal to obtain a first sample signal, samples the control and address signal according to the delayed clock signal to obtain a second sample signal, and compares the first sample signal with the second sample signal to obtain a status signal. The DRAM controller sends the control and address signal and the clock signal to the DRAM, receives the status signal from the DRAM, and adjusts a phase difference between the clock signal and the control and address signal according to the status signal.

Abstract: Systems and methods are disclosed relating to semiconductor memory devices. According to some exemplary implementations, there are provided innovations associated with power and ground pads in devices such as static random access memory (“SRAM”) devices and dynamic random access memory (“DRAM”) devices. Moreover, the systems and/or methods may include features such as minimization of simultaneous switching outputs (SSO) effects relating to echo clock circuitry.

Abstract: A self clocking data extraction method is shown that is tolerant of timing jitter, data skew and the presence of multiple edges per data bit. The data is sampled when the following criterion are met: There is at least one edge across any track (the clock assures this criteria is met), followed by no edges in any track for a defined period of time (T), and all edge activity must occur in a period of time less than T (to keep from detecting false samples). This method enables the handling of trace data signals with poor electrical characteristics that can not be recorded by methods known in the prior art.

Abstract: A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches, each of which latches an external address in response to the activation of an external command and outputs an internal address in response to the activation of an internal command corresponding to the external command. A pipe latch control unit is configured to control the pipe latch unit to sequentially enable the plurality of pipe latches. An output drive unit is configured to selectively output the internal address or the external address. The internal command is activated after a predetermined latency from an activation timing of the external command.

Abstract: A data input circuit includes a valid strobe signal generation circuit and a data strobe signal counter. The valid strobe signal generation circuit is configured to remove a pulse of an internal strobe signal generated and generate a valid strobe signal. The pulse may have been generated during a preamble period. The data strobe signal counter is configured to count the valid strobe signal according to burst length information and generate a write latch signal for aligning data at a time of a write operation.

Abstract: A method provides improved signal quality in a computer memory system. In one embodiment, a digital signal is generated having a voltage interpreted with respect to a reference voltage. The reference voltage is dynamically adjusted as a function of the traffic intensity at which the digital signal is directed to a particular receiver. A training phase may be performed for each DIMM of the memory system, to construct a lookup table correlating suitable reference voltages with different traffic intensities. The lookup table may be referenced during a subsequent execution phase, to dynamically select a reference voltage according to changing traffic intensity. The dynamically selected reference voltage value may be enforced by using transistors to selectively recruit resistors of a resistor network.

Abstract: The amount of data that may be transferred between a processing unit and a memory may be increased by transferring information during both the high and low phases of a clock. As one example, in a graphics processor using a general purpose register file as a memory and a mathematical box as a processing unit, the amount of data that can be transferred can be increased by transferring data during both the high and low phases of a clock.

Abstract: A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.

Abstract: A delay locked loop circuit is disclosed. The circuit includes a phase detector for comparing the phase of an input clock signal with the phase of a feedback clock signal that is fed back into the phase detector, and for outputting a detection signal. The circuit also includes a control circuit unit for controlling a delay line in response to the detection signal, a delay line for delaying the input clock by a predetermined amount of delay in response to output impedance calibration codes applied to the delay line, and a replica circuit configured to have the same delay conditions as those of an actual clock path to a circuit of the semiconductor device, to receive a delay clock signal of the delay line, and to generate the feedback clock signal.

Abstract: A strobe signal is received in a device and execution of an operation in the device is delayed when the strobe signal includes a preamble. Additional apparatus, systems, and methods are disclosed.

Abstract: A semiconductor memory device using system clock with a high frequency can maintain a constant operation margin even in the change of operation environments including voltage level, temperature, and process. The semiconductor memory device includes an output control signal generator configured to be responsive to a read pulse that is activated in response to a read command, to generate an odd number of first output source signals corresponding to a rising edge of a system clock and a even number of second output source signals corresponding to a falling edge of the system clock, and an output enable signal generator configured to generate a first rising enable signal and a falling enable signal on the basis of the first output source signal and generate a second rising enable signal on the basis of the second output source signal, according to column address strobe (CAS) latencies, the first rising enable signal being activated earlier than the second rising enable signal by a half cycle of the system clock.

Abstract: A semiconductor device according to the present invention includes plural controlled chips CC0 to CC7 that hold mutually different layer information, and a control chip IF that supplies in common layer address signals A13 to A15 and a command signal ICMD to the controlled chips. Each bit that constitutes the layer address signals A13 to A15 is transmitted via at least two through silicon vias that are connected in parallel for each controlled chip out of plural first through silicon vias. Each bit that constitutes the command signal ICMD is transmitted via one corresponding through silicon via that is selected by an output switching circuit and an input switching circuit. With this configuration, the layer address signals A13 to A15 reach the controlled chips earlier than the command signal ICMD.

Abstract: A semiconductor device includes a plurality of semiconductor memories, a clock signal synchronization circuit, and a first circuit. The clock signal synchronization circuit is electrically coupled to the plurality of semiconductor memories. The first circuit is electrically coupled to the plurality of semiconductor memories. The first circuit changes a bit width of data. The data is transferred between the first circuit and the plurality of semiconductor memories.

Abstract: The data access apparatus comprises a phase locked loop (PLL) and a data receiving circuit. The PLL provides a plurality of internal clocks and selecting a strobe clock from the plurality of internal clocks according to a phase selection signal. The data receiving circuit comprises a latching module, for latching of the data signal according to trigger of the strobe clock and a calibrating circuit, for generating the phase selection signal for matching the data with a predetermined data according to the plurality of internal clocks in a training mode and finally determining the phase selection signal corresponding to a preferred clock used in a normal mode.

Abstract: A system and method for increasing DDR memory bandwidth in DDR SDRAM modules are provided. DDR memory has an inherent feature called the Variable Early Read command, where the read command is issued on CAS latency before the completion of the ongoing data burst and the effect of the CAS latency is minimized in terms of the effect on bandwidth. The system and method optimizes the remaining two access latencies (tRP and tRCD) for optimal bandwidth.

Abstract: A controller for a DDR PSRAM is provided. The controller includes a single rate processing unit, a double rate processing unit and a selector. The signal rate processing unit obtains a single data rate data according to a first data and a first clock. The double rate processing unit obtains a double data rate data according to a second data and a second clock that is two times the frequency of the first clock. The selector selectively provides any of the single data rate data and the double data rate data to the DDR PSRAM via a common bus according to a control signal.

Abstract: A method for calibrating a data strobe (DQS) signal and associated circuit is provided. The calibrating method includes determining N buffers from a delay chain having M buffers to delay a predetermined phase during a first period; serially connecting the N buffers of the delay chain during a second period; and inputting the DQS signal to the N serially connected buffers to delay the DQS signal by the predetermined phase.

Abstract: A method for training an electronic memory may include receiving a first delay value and a second delay value. The first delay value and the second delay value may be associated with a first data strobe indicating when to sample data on a first memory lane of the electronic memory. The method may also include determining a difference between the first delay value and the second delay value. The method may further include receiving a third delay value associated with a second data strobe indicating when to sample data on a second memory lane of the electronic memory. The method may also include determining a fourth delay value for the second memory lane of the electronic memory utilizing the third delay value and the determined difference between the first delay value and the second delay value.

Abstract: According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit that includes both a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information for an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.

Abstract: Multi-rank memories and methods for self-refreshing multi-rank memories are disclosed. One such multi-rank memory includes a plurality of ranks of memory and self-refresh logic coupled to the plurality of ranks of memory. The self-refresh logic is configured to refresh a first rank of memory in a self-refresh state in response to refreshing a second rank of memory not in a self-refresh state in response to receiving a non-self-refresh refresh command for the second rank of memory.

Abstract: A synchronous signal generating circuit. The synchronous signal generating circuit includes a delay locked loop (DLL), an emulator and a multiplexer. The DLL is operative to delay a reference clock signal according to a count value to generate a first output clock signal. The count value is generated according to phase difference between the first output clock signal and the reference clock signal. The emulator is operative to provide a function of the DLL and includes a programmable delay line which is operative to receive the reference clock signal and a reference count value, wherein the reference clock signal is delayed according to the reference count value to generate a second output clock signal. The multiplexer is operative to receive the first and second output clock signal and selectively output the first or second output clock signal. The first output clock signal is outputted in a first mode and the second output clock signal is outputted in a second mode.

Abstract: A semiconductor apparatus has a plurality of chips stacked therein. Read control signals for controlling read operations of the plurality of chips are synchronized with a reference clock such that the time taken from the application of a read command to the output of data for each of the plurality of chips is maintained substantially the same.

Abstract: A latching element latches incoming data into an integrated circuit. The latching element (for example, a latch or flip-flop) can be considered to include a data path portion, a clock path portion, and an ideal latching element. In one embodiment, an open-loop replica of the data path portion is disposed in a clock signal path between a clock input terminal of the integrated circuit and a clock input lead of the latching element. In a second embodiment, an additional replica of the clock path portion is disposed in a data signal path between a data terminal of the integrated circuit and a data input lead of the latching element. The replica circuits help prevent changes in skew between a data path propagation time to the ideal latching element and clock path propagation time to the ideal latching element. Setup times remain substantially constant over PVT (process, supply voltage, temperature).

Abstract: A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.

Abstract: A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.

Abstract: Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals.

Abstract: To provide a semiconductor memory device including a mode register in which a mode signal is set, a data amplifier that amplifies read data read from a memory cell array, a data bus onto which the read data amplified by the data amplifier is transmitted, a data input/output circuit that outputs a signal on the data bus to outside, and a mode signal output circuit that outputs the mode signal set in the mode register onto the data bus. Because the mode signal is not caused to interrupt halfway along the data input/output circuit, but supplied onto the data bus that connects the data amplifier to the data input/output circuit, no collision of the read data with the mode signal occurs in the data input/output circuit.

Abstract: Provided is a synchronous dynamic random access memory (DRAM) semiconductor device including multiple output buffers, a strobe control unit and multiple strobe buffers. Each of the output buffers is configured to output one bit of data. The strobe control unit is configured to output multiple strobe control signals in response to an externally input signal. The strobe buffers are connected to the output buffers and the strobe control unit, and each of the strobe buffers is configured to output at least one strobe signal. At least some of the strobe buffers are activated in response to the strobe control signals, and the output buffers are activated in response to the strobe signals output by the activated strobe buffers.

Abstract: A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal.

Abstract: Techniques pertaining the designs of memory controller are disclosed. According to one aspect of the present invention, a memory controller reduces delays in a data strobe signal of a DDR memory relative to a clock signal of a memory controller thereof. In one embodiment, the memory controller employs four IO ports, two inverters, six edge triggers and a multiplexer. By feeding back an inverted clock signal and utilizing the rising and filing edges of the clock signal, the delays in a data strobe signal of a DDR memory relative to a clock signal of a memory controller are considerably reduced or minimized.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.

Abstract: A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.

Abstract: A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.

Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

Abstract: Systems and methods to set a voltage value associated with a memory controller coupled to a memory device are disclosed. A particular method includes comparing test data of a test path to functional data of a functional path. The functional data may be generated based on device data received at a memory controller from a memory device. The test data may be affected by a voltage value applied to a resistor arrangement in electronic communication with the test path. The voltage value may be applied to the resistor arrangement based on the comparison.

Abstract: Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.

Abstract: A memory module according to certain aspects has a plurality of memory devices arranged into one or more logical ranks. Each logical rank may correspond to a set of at least two physical ranks. The memory module can include a circuit operatively coupled to the plurality of memory devices and configured to be operatively coupled to a memory controller of a computer system to receive a logical rank refresh command. In response, the circuit can initiate a first refresh operation for one or more first physical ranks and then initiate a second refresh operation for one or more second physical ranks. The memory module can further include a memory location storing a refresh time (tRFC) value accessible by the memory controller and based at least in part on a calculated maximum amount of time for refreshing the logical rank.

Abstract: A method is provided for writing data to a memory array operating in synchronization with a clock signal having a transition edge. A data strobe signal having a transition edge corresponding to the transition edge of the clock signal is provided. The transition edge of the clock signal is used to relay the data corresponding to the transition edge of the data strobe signal if the transition edge of the data strobe signal is coming in earlier than the transition edge of the clock signal, wherein the clock signal has a rising edge and a falling edge, the data strobe signal has a rising edge and a falling edge respectively corresponding to the rising and the falling edges of the clock signal, and the transition edge of the clock signal is one of the rising and the falling edges of the clock signal.

Abstract: Disclosed is a method for tuning control signals associated with one or more memory devices. The method includes performing a number of memory access operations on at least one memory device and recording results of the memory access operations. Specifically, the memory access operations are performed with different time delays for a first edge of a control signal. The control signal used for capturing data is provided by the at least one memory device. The method further includes selecting a time delay from the time delays used in the memory access operations. Moreover, the method includes utilizing the selected time delay in performing subsequent memory access operations on the at least one memory device. Also disclosed is a system including at least one memory device and an integrated circuit operatively coupled to the at least one memory device. The system incorporates the method for tuning control signals.

Abstract: A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command and blocks application of sampling and transmission clock signals to the FIFO register.

Abstract: Various embodiments of the present invention provide systems, methods and circuits for power management and/or EMI reduction. As one example, a method for memory system access is disclosed that includes providing a first bank of memory; providing a second bank of memory; receiving a memory access request that includes assertion of a reference memory clock; accessing the first bank of memory using a first sub memory clock asserted relative to the reference memory clock; delaying a phase offset; and accessing the second bank of memory using a second sub memory clock asserted the phase offset after assertion of the first sub memory clock.

Abstract: A semiconductor storage device, a first internal bus, a second internal bus, and a third internal bus have bus widths decreasing stepwise from a memory cell array side to a data output circuit side. A first selection circuit and a second selection circuit divide the data, which is input via the first or second internal bus, according to a rate of a decrease in bus width in an input and an output, time-divide the divided data, and output the divided data to the second or third internal bus.

Abstract: Provided is a delay adjustment device that contributes to downsizing the circuit that adjusts a flight time. The delay adjustment device is connected to a memory, and adjusts a timing to retrieve data with a data signal and a data strobe signal output from the memory. The delay adjustment device includes a data retrieve unit that receives the data signal and the data strobe signal, and outputs a data value of the data signal in accordance with the data strobe signal; and a control unit that issues a read command to the memory, calculates a flight time, and controls a valid period of the data strobe signal based on the flight time.

Abstract: A memory apparatus enable operation which is adapted to environmental conditions. The memory apparatus includes a memory module that can store and incorporate environment-dependent optimal operating parameters. The memory module comprises a plurality of volatile memory devices and one or more non-volatile memory devices that store a plurality of environment-dependent device parameters for a device selected from the plurality of volatile memory devices. The stored parameters enable the selected device to function optimally in multiple environmental conditions.

Abstract: According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit includes a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock, and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information concerning an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.