Abstract: An apparatus for data strobe and timing variation detection of an SDRAM interface includes a differential-signal to single-end signal converter, a first phase delay circuit, a data latch circuit. The differential-signal to single-end signal converter receives a differential data strobe signal from the SDRAM interface and converts the signal into a single-end data strobe signal. The first phase delay circuit is connected to the differential-signal to single-end signal converter to delay the phase of the single-end data strobe signal for producing a delayed data strobe signal. The data latch circuit is connected to the phase delay circuit to latch synchronous data from the SDRAM interface according to the delayed single-end data strobe signal.

Abstract: Disclosed is a shift register including a plurality of flip-flops configured in series to shift input data in response to an applied clock, and a drive operation controller.

Abstract: A strobe signal is received in a device and execution of an operation in the device is delayed when the strobe signal includes a preamble. Additional apparatus, systems, and methods are disclosed.

Abstract: A method for operating a memory device with pseudo double clock signals comprises the steps of: generating an even clock signal and an odd clock signal, wherein the clock rates of both the even clock signal and the odd clock signal are half that of the input clock signal, and the even clock signal is the inverse signal of the odd clock signal; if the logic level of the even clock signal is 1 when receiving a trigger of a control signal, applying the even clock signal to a memory device; and if the logic level of the odd clock signal is 1 when receiving another trigger of the control signal, applying the odd clock signal to the memory device.

Abstract: Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs from the first set. Either the first set of periodic signals or the second set of periodic signals may be selected and used to generate a set of data capture signals. The selection of either the first set or the second set may be made on the basis of the number of serial data digits in a previously captured burst of data. The data capture signals may then be used to capture a burst of serial data digits.

Abstract: A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: A DRAM and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the controller to yield improvements in timing margins. The coupling of the components on a shared electrical bus through adjustment of the termination values during training removes known offset issues.

Abstract: A double data rate memory device comprises first and second sense amplifiers, a data selection circuit, and a data processing circuit. The first sense amplifier is configured to provide even data loaded on a first input and output data line, and the second sense amplifier is configured to provide odd data loaded on a second input and output data line. The data selection circuit is connected to the first and second sense amplifiers and is configured to provide output data loaded on a single data line, and the data processing circuit connected to the data selection circuit and configured to transfer the even data and the odd data in first and second data paths. The even data and the odd data are combined into the output data of the data selection circuit, and the data selection circuit selects the output data in response to a least significant bit of a column address and transfers the selected data on the single data line in response to a clock signal.

Abstract: In one embodiment, a memory circuit includes one or more memory cells that include transistors having a first nominal threshold voltage, and interface circuitry such as word line drivers and bit line control circuitry that includes one or more transistors having a second nominal threshold voltage that is lower than the first nominal threshold voltage. For example, the word line driver circuit may be driven by signals from a lower voltage domain than the memory circuit's voltage domain. Lower threshold voltage transistors may be used for those signals, in some embodiments. Similarly, lower threshold voltage transistors may be used in the write data driver circuits. Other bit line control circuits may include lower threshold voltage transistors to permit smaller transistors to be used, which may reduce power and integrated circuit area occupied by the memory circuits.

Abstract: A semiconductor memory device includes a controller, a plurality of substrates, and a plurality of stacked memories that are spaced apart and sequence on each of the substrates. Each of the stacked memories includes an interface chip that is connected to the respective substrate and a plurality of memory chips that are stacked on the interface chip. The controller is configured to control the stacked memories. The interface chips are configured to forward a command signal from the controller through each interface chip in the sequence of stacked memories that is intervening between the controller and a selected stacked memory to which the command signal is directed.

Abstract: A chip system that has reduced power consumption under specific operational modes includes: a DDR3 chip that includes: a plurality of pads, disposed at the center of the DDR3 chip; and an array of banks, each bank having a specific logical address, surrounding the pads. The chip system further includes: a clock, coupled to the DDR3 chip, for controlling a rate of data transmission; and a memory controller, coupled to the clock, for coordinating transmitted data with relevant processes, and for selectively reassigning the bank logical addresses according to a specific operational mode.

Abstract: A memory structure is described. In one embodiment, the memory structure comprises a memory controller configured to receive a clock signal and to be coupled to a plurality of memory modules via a single address/control bus. The memory controller couples to each of the plurality of memory modules via a separate chip select signal for each memory module. The memory controller issues commands across the address/control bus to the memory modules in an interleaved fashion in accordance with the timing supplied by the clock. During a waiting period after issuance of a command to one memory module, the memory controller can issue commands to a different memory module.

Abstract: A buffered DRAM that can be utilized in a DIMM or RDIMM package to reduce the load on the data lines connected to the package is presented. A buffered DRAM can include a DRAM memory cell; and a buffer coupled to receive data lines and strobe signals, the buffer further coupled to receive address and command signals. If data access is directed to a second DRAM, the buffer buffers the data and strobe signals for access by the second DRAM. If data access is directed to the buffered DRAM the buffer buffers the data and strobe signals for access by the DRAM memory cell.

Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated at least in part to a first number of chip-select signals. The circuit is configurable to receive address signals and a second number of chip-select signals from the computer system. The circuit is further configurable to generate and transmit phase-locked clock signals to the first number of ranks, and to generate the first number of chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of chip-select signals.

Abstract: A memory controller may implement variable delay elements, on a per-bit basis, in both the read and write paths. The memory controller may include multiple adjustable delay circuits associated with data lines and a strobe line, each of the adjustable delay circuits inserting an adjustable amount of delay into a signal destined to or received from one of the data lines or the strobe line. The memory controller may additionally include control logic to determine the delay amount for each of the adjustable delay circuits, the delay amount being determined to reduce static skew between each of the data lines and the strobe line.

Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system and to provide the first number of chip-select signals to the first number of ranks in response to the phase-locked clock signals, the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.

Abstract: A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory circuits activated by a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals smaller than the first number of chip-select signals. The circuit is further configurable to generate phase-locked clock signals, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response at least in part to the set of signals, and to generate the first number of chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of chip-select signals.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory devices configured to be activated concurrently with one another in response to a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals, the address signals comprising bank address signals. The circuit is further configurable to monitor command signals received by the memory module, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response to the command signals, and to provide the first number of chip-select signals to the first number of ranks in response at least in part to the received bank address signals and the received second number of chip-select signals.

Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

Abstract: A memory access control apparatus includes a memory controller controlling a memory adopting a DDR format; a DDR-PHY adjusting the timing of an interface signal between the memory controller and the memory; a DDR-PHY controller controlling the DDR-PHY; and a clock controller controlling the frequency of a clock signal. A first request signal for controlling the operation of the memory in a self-refresh mode is supplied to the memory controller, a second request signal for resetting the DDR-PHY is supplied to the DDR-PHY controller, a third request signal for changing the clock frequency is supplied to the clock controller, a fourth request signal for setting a parameter for the DDR-PHY is supplied to the DDR-PHY controller, and a fifth request signal for canceling the operation of the memory in the self-refresh mode is supplied to the memory controller in order to change the clock frequency of the memory.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: A memory system (250) includes a plurality of memory devices (260) adapted to be coupled to an interface (140), an indicator (272) for indicating a type of the plurality of memory devices (260), and an override circuit (280) having a first terminal adapted to be coupled to the interface (140), a second terminal coupled to the plurality of the memory devices (260), and a control input for receiving a control signal. The override circuit (280) is responsive to the control signal to alter an operation of the memory system (250).

Abstract: A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference clock signal via the vertical connection path, wherein each one of the stacked plurality of memory chips is characterized by a process variation and actively compensates for said process variation in relation to the reference signal.

Abstract: A semiconductor memory device includes a memory cell array divided into a plurality of areas, a common data bus connected to an input/output circuit, a plurality of individual data buses connected to different areas of the memory cell array through different paths respectively, and a bidirectional buffer connected to the common data bus and the individual data buses. In the semiconductor memory device, the bidirectional buffers transmit data bidirectionally between the common data bus and a selected one of the individual data buses.

Abstract: A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.

Abstract: A memory controller comprises a multiplexer, a first-in, first-out memory (FIFO), a comparator, and a detection and adjustment circuit. The multiplexer receives a clock signal, a reference voltage, and a gating signal. The FIFO has a clock input coupled to an output of the multiplexer and a data input that receives data from a memory. The comparator has a first input coupled to an output of the FIFO, and a second input coupled to receive a calibration pattern. The calibration pattern is predetermined to match with a first portion of data from the FIFO, and is predetermined to not match with a second portion of data from the FIFO. The detection and adjustment circuit detects if a transition from the first portion to the second portion occurs within a predetermined time period. If the transition is not detected within the time period, a timing of the gating signal is adjusted.

Abstract: A memory device can be directly mounted on a motherboard supporting DDR3 SDRAM, and then the memory device have advantages of the fly-by bus topology and the T branch topology established by the joint electron device engineering council (JEDEC). Thus, the system performance of a desktop computer in a unit interval can be enhanced.

Abstract: A double data rate memory device comprises first and second sense amplifiers, a data selection circuit, and a data processing circuit. The first sense amplifier is configured to provide even data loaded on a first input and output data line, and the second sense amplifier is configured to provide odd data loaded on a second input and output data line. The data selection circuit is connected to the first and second sense amplifiers and is configured to provide output data loaded on a single data line, and the data processing circuit connected to the data selection circuit and configured to transfer the even data and the odd data in first and second data paths. The even data and the odd data are combined into the output data of the data selection circuit, and the data selection circuit selects the output data in response to a least significant bit of a column address and transfers the selected data on the single data line in response to a clock signal.

Abstract: A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices.

Abstract: A burst length control circuit capable of performing read and write operations in high speed according to a burst length and a semiconductor memory device using the same includes a clock signal generating unit for generating first and second internal clock signals from a clock signal in response to a first and second burst signals, a control signal generating unit for driving in response to the first and second internal clock signals, wherein the control signal generating unit for generating first and second control signals, enable sections of the first and second control signals being controlled according to the first and second burst signals at a read operation or write operation, and a burst termination signal generating unit for generating a burst termination signal in response to the first and second burst signals. The first control signal is disabled in response to the burst termination signal.

Abstract: A method is disclosed for operating a memory device, including providing a timing signal comprising a plurality of clock cycles, providing an activate signal, and providing a bank address signal. An activate command executes on every first duration of clock cycles, and the bank address signal is high for at least a portion of the first duration of clock cycles. In one embodiment, the first duration of the activate signal is at least four clock cycles, and the bank address signal is at least one clock cycle. A memory device having a row decoder and an active driver is also provided.

Abstract: A semiconductor memory device includes a plurality of memory cell matrixes each of which contains plural memory cell arrays whose number is lager than 2n and smaller than 2n+1, n being a natural number. The semiconductor memory device includes normal memory cell arrays including 2m numbers of memory cell arrays of the plurality of memory cell matrixes, m being a bit of addresses, wherein a data access operation is performed on normal memory cells in the normal memory cell arrays as normal word lines corresponding to the normal memory cells are activated in response to the addresses, and additional redundancy memory cell arrays in the plurality of memory cell matrixes, wherein repair-expected memory cells in the normal memory cell arrays are replaced with the additional redundancy memory cell arrays as redundancy word lines corresponding to the additional redundancy memory cells are activated in response to the addresses corresponding to the repair-expected memory cells.

Abstract: A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.

Abstract: Described herein are a method and apparatuses for providing DDR memory access. In one embodiment, an apparatus includes a data storage unit to store and synchronize a plurality of data line signals with a clock signal. The apparatus includes a selector unit that receives the plurality of data line signals and selects two data line signals. The apparatus also includes a double data rate (DDR) output unit that receives the two data line signals from the selector unit and generates a DDR data line signal having a time period substantially one half of a clock time period of the clock signal. The apparatus also includes an input/output (I/O) pad coupled to and locally positioned with respect to the DDR output unit. The data storage unit, the selector unit, and the DDR output unit in combination form an I/O buffer which is locally coupled to the I/O pad.

Abstract: A semiconductor device in the present invention includes a DLL circuit which determines a phase shift amount, an arithmetic circuit which shifts the phase shift amount by a predetermined phase at test mode time, registers which set the phase shift amount, and a transmission circuit which shifts a phase to the set phase to transmit or receive a signal. The transmission circuit has a first phase shifter which shifts a first signal to the set phase, a first bidirectional buffer which loops back the first signal at the test mode time, a second phase shifter which phase-shifts the signal outputted from the first bidirectional buffer, a third phase shifter which phase-shifts a third signal, a second bidirectional buffer which loops back the third signal at the test mode time, a fourth phase shifter which phase-shifts the signal outputted from the second bidirectional buffer, and a FIFO which takes out an output signal of the second phase shifter or the fourth phase shifter.

Abstract: Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.

Abstract: The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.

Abstract: A memory device and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the memory device to yield improvements in timing margins. The coupling of the components on a shared electrical bus through adjustment of the termination values during training removes known offset issues.

Abstract: The memory system, memory device, memory controller and method may have a reduced power consumption. The memory system, memory device, memory controller and method may transition a data strobe signal to a valid logic level during a standby state. The valid logic level may be less than a logic level associated with a higher impedance level, such as when a bus may be turned off or connected to a ground voltage. A delay locked circuit need not be used in the memory device.

Abstract: A memory device is connected through an interface to a memory controller. The memory device's reference voltage is set based on a driver's impedance of the memory device and the controller driver drive strength during driver training. The voltage is applied to a reference resistor pair at the memory device and changed until the voltage level switches. The voltage is then set at the reference resistor pair of the memory device.

Abstract: A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal.

Abstract: Systems and methods for reading data from or writing data to a memory device. The methods involve receiving a first pulse signal having a first pulse frequency at the memory device. The methods also involve generating, at the memory device, a second pulse signal using the first pulse signal. The second pulse signal is a compliment of the first pulse signal. The second pulse signal has a second pulse frequency that is equal to the first frequency. The fist pulse signal is used to control first read/write operations so that first data is output from or input to the memory device at a first data rate. The first and second pulse signals are used to control second read/write operations so that second data is output from or input to the memory device at a second data rate. The second data rate is twice the first data rate.

Abstract: A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers.

Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system and to provide the first number of chip-select signals to the first number of ranks in response to the phase-locked clock signals, the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.

Abstract: A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory devices configured to be activated concurrently with one another in response to a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals, the address signals comprising bank address signals. The circuit is further configurable to monitor command signals received by the memory module, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response to the command signals, and to provide the first number of chip-select signals to the first number of ranks in response at least in part to the received bank address signals and the received second number of chip-select signals.

Abstract: A dual data rate (DDR) memory controller and method are provided. The method includes: receiving a first data strobe at a first terminal from a first memory having a first rank; receiving a first data signal at a second terminal from the first memory having the first rank; calibrating the first data signal with the first data strobe to produce a first calibration value; receiving a second data strobe at the first terminal from a second memory having a second rank; receiving a second data signal at the second terminal from the second memory having the second rank; calibrating the second data signal with the second data strobe to produce a second calibration value; determining a final calibration value using the first and second calibration values; and using the final calibration value to time the first data signal and the second data signal during a read operation of the memories.

Abstract: An invention is provided for determining write leveling delay for a plurality of memory devices having command signals lines connected in series to each memory device is disclosed. The invention includes determining a device delay value for each memory device. Each device delay value indicates a period of time to delay a DQS signal when accessing a related memory device. Once these delay values are determined, the delay values are examined sequentially and a prior device delay value is set to a lower value, for example zero, when a subsequent device delay value of a memory device connected subsequently along the command signal lines is greater than the prior device delay value.

Abstract: A circuit for generating a read end signal includes a clock transferring unit which receives a clock signal, a write/read status signal and an all bank precharge signal and outputs a delayed clock signal, a read signal detecting unit which receives a read pulse signal and the delayed clock signal and generates a read detection signal having a pulse width corresponding to a certain clock, and a read end signal generating unit which receives a first signal, the delayed clock signal and the read detection signal and generates a read end signal.