Abstract: A semiconductor memory device includes an array of memory cells and an adjustment circuit for adjusting the pulse width of an address transition detect equalizer (ATDEQ) signal. The adjustment circuit receives an address transition detection (ATD) signal and is responsive to the level changes of voltages Vp and Vn to adjust the pulse width of the ATDEQ signal accordingly. The resulting signal ATDEQ is supplied to a power supply circuit for a bit line selector for selecting a bit line of the array of memory cells. The device can thus accomplish the readouts of bit “0” and bit “1” in a state less liable to delay.

Abstract: Within a programmable logic device (PLD), a DDR SDRAM interface for a DDR SDRAM is provided, the DDR SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface including: a first register adapted to capture data associated with the falling edges of the DQS signal; a second register adapted to capture data associated with the rising edges of the DQS signal; and clock edge selection logic circuitry coupled to clock inputs of the first and second registers and adapted to select between the rising or falling clock edges of an internal PLD clock to clock the first and second registers and thereby transfer the captured data into core logic for the PLD, the selection of the clock edge based on a phase relationship between the internal PLD clock and the DQS signal.

Abstract: A delay-locked loop (DLL) is disclosed with a phase detector configured to detect a phase difference between an external clock signal and an internal clock signal, a variable delay line configured to variably delay the external clock signal in relation to the phase difference to generate an intermediate clock signal, a selection unit configured to select between the intermediate clock signal and an inverted version of the intermediate clock signal in relation to an inversion control signal, and to generate an internal clock signal according to the selection, and an inversion determination unit configured to generate the inversion control signal in relation to transition of the external clock signal within a duty error margin.

Abstract: A test mode control device using a nonvolatile ferroelectric memory enables a precise test of characteristics of a memory cell array by changing a reference voltage and timing regulated for a memory cell test in a software system without extra processes. In an embodiment, test modes and arrangement of data pins are programmed using a nonvolatile ferroelectric memory, and addresses, control signals and arrangement of data pins are regulated in a software system depending on a programmed code. As a result, characteristics of a cell array can be precisely tested without extra processes.

Abstract: A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.

Abstract: A page access circuit of a semiconductor memory device comprises a page address detecting unit configured to detect transition of a page address in response to a page address control signal so as to generate a page address detecting signal, a page control unit configured to control the page address control signal depending on transition of a sense detecting signal for notifying end of operation of a bit line sense amplifier, and a column control unit configured to generate a column selecting signal in response to the page address control signal when the page address detecting signal is activated.

Abstract: To allow a memory controller to synchronize strobe to clock relationship for a DRAM, a register, such as, a flip flop, is incorporated within the DRAM to facilitate the sampling of SCLK with DQS. Likewise, while the DRAM is in a test mode of operation, the memory controller advances or retards the clock to DQS at the memory controller hub (MCH) to achieve the proper DRAM relationship. In one embodiment, the memory controller advances DQS if a binary zero value is read. In contrast, the memory controller retards DQS if a binary one value is read.

Abstract: An apparatus and method for generating a control pulse for closing an active wordline in a memory device is provided. A timeout generator circuit having a time delay portion and a reset portion may be used to generate a close signal. The time delay portion may define a predetermined time delay interval. The timeout generator may be used in combination with an address transition detector in a refresh controller for a memory device. A method is given in which a control pulse is generated in response to an active mode signal, a timer measuring a predetermined time delay interval is activated in response to the control pulse, a close signal is produced in response to the expiration of the predetermined time delay interval, and the active wordline is closed in response to the close signal.

Abstract: A drive circuit of a FRAM (Ferroelectric Random Access Memory) includes an address buffer circuit that buffers an applied external address signal and generates an internal address signal, and detects a transition of the internal address signal and generates address transition detection signals for respective internal address signals. The FRAM includes a composite pulse signal generating circuit which limits a subsequent generation of a composite pulse signal for a delay interval provided after a generation of a previous composite pulse signal, in generating the second composite pulse signal obtained by totaling the respective address transition detection signals. The FRAM includes an internal chip enable buffer circuit which generates an internal chip enable signal to generate an internal control signal, in response to the composite pulse signal.

Abstract: An internal voltage generator for generating a back bias voltage includes a back bias voltage pumping block for comparing a reference voltage with a feedback back bias voltage to generate a back bias enable signal and the back bias voltage in response to an activated self refresh signal and a back bias voltage discharge controlling unit for discharging the back bias voltage into a ground voltage in response to the activated self refresh signal and the back bias enable signal.

Abstract: A semiconductor memory device includes a word drive line, and a word line connected with memory cells. A first drive circuit drives the word drive line to a first voltage based on a main word signal, and resets the word drive line to a ground voltage in a time period for transition of an address signal. A second drive circuit outputs a signal of the first voltage to the word line based on a sub-word signal such that a data is read out from one of the memory cells. The main word signal and the sub-word signal are obtained from an address signal, and are signals taking the ground voltage or a second voltage which is lower than the first voltage.

Abstract: Provided are a semiconductor memory device and a driving method thereof, which can reduce power consumption and operation delay time by preventing an overlapped driving of word lines. The pseudo SRAM includes: an address input unit for receiving an address through a pin and outputting the received address as an internal address; a transition detecting unit for detecting a transition of the internal address; a word line (WL) driving signal generating unit for generating a WL driving signal in response to an output signal of the transition detecting unit; and a control signal generating unit, in response to a pin select signal, for generating a first control signal for controlling the address input unit to output only an valid address as the internal address, and a second control signal for controlling the WL driving signal generating unit to activate the WL driving signal.

Abstract: To provide a control circuit of power supply unit, power supply unit and control method thereof capable of setting and adjusting a voltage value of output voltage flexibly corresponding to an instruction from outside, a voltage adjusting portion AD for adjusting first voltage setting information inputted from outside to real voltage information is provided and the voltage value of the output voltage of the power supply unit is controlled based on real voltage information outputted from the voltage adjusting portion AD. The first voltage setting information inputted from outside enables a desired output voltage to be set up by adjusting the real voltage information flexibly even if information relating to the setting of voltage set as output voltage to an external device which is a supply destination is different from actually necessary voltage value.

Abstract: A data output controller of a high-speed memory device and a method therefore. The data output controller includes a first section for detecting a unit delay multiple of an external clock signal based on the external clock signal and a delay circuit of the external clock signal, a second section for analyzing data in an information storage unit, in which an internal timing is defined, by using values detected by the first section, and a third section for adjusting a data output timing in accordance with predetermined CAS latency based on analyzed values obtained through the second section. The data output controller to indicate an optimal point of a data output indicated by CAS latency information.

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

Abstract: A method generates a sampling clock signal in a communication block of a memory device having a plurality of communication blocks which are distributed in the memory device. The method includes receiving an input clock signal in the communication block, generating, only in response to the input clock signal, a local clock signal having a predetermined phase relationship with respect to the input clock signal, and generating the sampling clock signal based on the local clock signal.

Abstract: A circuit for adjusting a signal length is adapted for a memory device. The circuit adjusts a signal length of an ATD signal. The circuit includes a timing module, an encoding module and a logical control unit. Wherein, the timing module generates a plurality of timing signals according a pulse generated by the ATD signal. The encoding module is coupled to one of the data lines of the memory device. The timing signals are registered and encoded to generate a time value according to the status of the data output from the memory device. In addition, the logic control unit compares the present time value and the previous time value to generate a comparison result. The signal length of the ATD signal is adjusted according to the comparison result.

Abstract: The present invention relates to a semiconductor memory device. When a device exits from power mode, after a time until an instruction/address receive control signal substantially turns on or off an address and instruction input buffer unit and a time until the address and instruction buffer unit is turned on to synchronize an external command signal to an internal clock signal are compensated for, an internal clock-generating control signal for controlling generation of the internal clock signal is sensed at a high phase of a buffered clock signal and is generated at a low phase of the buffered clock signal. Further, when a device enters power mode, an internal clock-generating control signal for controlling generation of an internal clock signal is sensed at a high phase of a buffered clock signal and is then generated at a low phase of the buffered clock signal.

Abstract: A control unit for a semiconductor memory device, a semiconductor memory device and a method for controlling the same. The control unit of a semiconductor memory device includes control signal circuits, each control signal circuit to receive a master signal and to generate at least one of a plurality of control signals in response to the master signal, each of the plurality of core control signals to be generated after a delay specific to the core control signals after a transition of the master signal, the plurality of control signals to control the semiconductor memory device.

Abstract: A pseudo-dual port memory performs both a first memory access operation and a second memory access operation in a single period of an externally supplied clock signal CLK. The signal CLK is used to latch a first address for the first operation and a second address for the second operation. Control circuitry generates first control signals that initiate the first operation. The time duration of the first operation depends upon a delay through a delay circuit. A precharge period follows termination of the first operation. The time duration of the precharge period depends upon a propagation delay through the control circuit. The memory access of the second operation is initiated following termination of the precharging. The time duration of the second memory access depends on a delay through the delay circuit. The time when the second operation is initiated is independent of the duty cycle of CLK.

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

Abstract: An automatic ATD control circuit operates with a first delay circuit accepting a system clock pulse as an input and producing a delayed version of the system clock pulse as an output. The delay to the system clock is performed to allow a frequency comparison in a later part of the circuit. An edge detection circuit operates when the delayed system clock is received and senses an edge of the delayed system clock pulse. A pulse output from the edge detection circuit feeds into a second delay circuit; the second delay circuit produces an output pulse where a period of the pulse is determined by delay characteristics of the sense amplifier and is thus independent of system clock frequency. The pulse is compared to the system clock frequency. If the system clock frequency is above a determined frequency, the automatic ATD control circuit is disabled.

Abstract: The present invention relates to a clock control circuit that can reduce power consumption in the input operation of an address signal and control signals and semiconductor memory device including the same, and an input operation method of the semiconductor memory device. The clock control circuit accordance to the present invention generates a control clock signal only when external address signals or external control signals are substantially input. Therefore, unnecessary power consumption a power noise phenomenon can be reduced.

Abstract: In a single data rate (SDR) mode, logic level transitions of a data condition prior-determination signal RDYO are outputted to an output terminal (O) in response to an internal clock signal CKI. A ready signal RDY is outputted in synchronization with the internal clock signal CKI following a logic level transition of the data condition prior-determination signal RDYO. In a double data rate (DDR) mode, on the other hand, a toggle signal is outputted to the output terminal (O) in correspondence with the internal clock signal CKI following a logical level transition of the data condition prior-determination signal RDYO. After the internal clock signal CKI following the logical level transition of the data condition prior-determination signal RDYO, a strobe signal DQS is outputted in synchronization with the internal clock signal CKI.

Abstract: In a DDR operation mode, (L?1) count signal BRDYB is inverted to a low level when 1 is subtracted from initial latency (e.g., L=3). As a result, a delayed signal S (N1BD)/S (N1D) in reverse phase to signal S (N1)/S (N1B) is provided and internal clock signal CKI becomes high during the high level period of the second cycle. This is operated in synchronization with both edges of the external clock signal CLK, and output of double the frequency is started. In the external clock signal cycle immediately before completion of counting of initial latency in a count period for initial latency, the internal clock signal CKI is changed over to double the frequency. Validity flag RDY is changed to a high level during a second cycle of the double frequency.

Abstract: A semiconductor memory device, wherein an access to a first memory portion is made by referring to an address transformation table stored in a second memory portion, so that an access to a defective block is prevented; the second memory portion and the first memory portion are mounted on the same semiconductor chip, so that a part or all of address data input from outside the semiconductor chip can be made corresponding to an address of the second memory portion and input to the second memory portion without executing any calculation, and a stored pointer can be taken out at a high speed; and an access can be made to a memory at a high speed by following the address transformation table.

Abstract: A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to be coupled to the memory cell array; a data transfer circuit disposed between the sense amplifier circuit and data input/output ports; a control signal generation circuit configured to generate a plurality of control signals based on a reference clock signal externally supplied, the control signals serving for controlling data input and output of the sense amplifier circuit and data transferring timing in the data transfer circuit; and an internal clock signal generation circuit configured to generate an internal clock signal based on the reference clock signal for serving as the basis of the control signals, the internal clock signal having the same clock cycle as the reference clock signal and a constant duty ratio without regard to the duty ratio of the reference clock signal.

Abstract: An address latch signal generation circuit and an address decoding circuit may generate an address latch signal capable of latching pre-decoded internal address signals. The circuits may include a plurality of address transition detectors, each of the address transition detectors receiving a plurality of internal address signals pre-decoded by a pre-decoder, detecting level transition states of the internal address signals, and generating a control signal which has a predetermined enable period; a first logic unit for performing a logic operation on the control signals received from the plurality of address transition detectors, and generating the result signal; and a latch signal output unit for performing synchronization with a disable time point of the result signal from the first logic unit, thereby generating the address latch signal.

Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines. The clock signal lines comprise two differential clock signal lines which, at their end opposite to the memory controller device are either open or connected to one another by a short-circuiting bridge. The memory chips, during a write operation, synchronize the write data with the clock signal running from the memory controller device to the end of the clock signal line and, during a read operation, output the read data synchronously with the clock signal reflected from the open or short-circuited end of the clock signal lines.

Abstract: A memory system comprising a semiconductor memory for storing digital data, said memory being connectable to a control device in order to receive an address signal and to make data selected through the output-available address signal. The system is characterised in that it comprises a generating circuit for activating a wait signal to be forwarded to the control device during reading operations in such a way as to indicate the non-availability of the data to be read. The generating circuit is such to deactivate the wait signal, in such a way as to indicate the availability of the data to be read, following a waiting time interval correlated with an effective access time for said memory.

Abstract: A semiconductor memory device including a clock buffer, a column selection line decoder, a control signal generation circuit, and a column selection line driver is provided. The clock buffer receives an external clock signal and information about a column address strobe (CAS) latency and generates either a first clock signal which synchronizes with rising edges of the external clock signal or a second clock signal which synchronizes with falling edges of the external clock signal depending on the type of CAS latency information. The column selection line decoder receives and decodes a column selection address and outputs a decoding address used to select either a column selection line signal synchronized with the first or second clock signal. The control signal generation circuit outputs control signals that synchronize with one of the first and second clock signals.

Abstract: A Delayed Lock Loop (DLL) circuit includes an inversion control circuit. The inversion control circuit includes an inversion decision circuit to determine the inversion of reproduction clock signal by comparing phases of an external clock signal and a reproduction clock signal, and to produce an inversion decision signal including a duty error margin for the reproduction clock signal. The inversion control circuit also includes an output latch to latch the inversion decision signal in synchronization with a start signal to produce an inversion control signal.

Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.

Abstract: A ferroelectric memory device characterized in comprising: a voltage source for generating a predetermined voltage; a first bit line and a second bit line; a first ferroelectric capacitor having one end electrically connected to the first bit line; a first resistance provided between the first bit line and the voltage source; a second ferroelectric capacitor having one end electrically connected to the second bit line; a second resistance provided between the second bit line and the voltage source; and a sense amplifier that judges data written in the first ferroelectric capacitor based on a potential on the first bit line, according to a timing at which a potential on the second bit line changes when the predetermined voltage is supplied to the first bit line and the second bit line.

Abstract: A test method and a test circuit which enable operations to be checked when the time interval between a refresh operation and a read or write operation is forcibly reduced. Timings for a read or write operation in a normal operation mode and in a test mode are determined on the basis of an address transition detection circuit. A timing for a refresh operation in the normal operation mode is set on the basis of a normal refreshing pulse signal generated by a refresh pulse generating circuit in response to a timing signal generated by a timer circuit. A timing for a refresh operation in the test mode is set on the basis of a first testing refresh pulse generation signal generated by a first testing refresh pulse generating circuit in response to the address transition detection signal.

Abstract: A sense amplifier and a latch for sense data output the former 4 words of sense data to a latch for page data, and during a page mode reading period of the former 4 words of data as external data by the latch for page data, a selector circuit and an output buffer, perform a sense amplifying operation and a latch operation on the latter 4 words of memory cell information output from a Y gate under control of a sense signal and a latch signal.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.

Abstract: A semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cells store data and are selected according to address signals. The control circuit is configured to receive a clock signal and a first control signal, and output a plurality of data in response to the clock signal after the first control signal is asserted. After the first control signal is asserted, an internal signal which responds to the clock signal transits N times (N is a positive integer and greater than or equal to 2), then output of the data is started. At least one of the data is output at the transition after the output begins.

Abstract: An aspect of the present invention provides a ferroelectric memory comprising a cell block having a plurality of unit cells connected in series, one end of the cell block being connected to a plate line and the other end of the cell block being connected to a bit line through a block selecting transistor, a sense amplifier connected to the bit line, and a block selector decoder which controls ON/OFF of the block selecting transistor. The timing for operating the sense amplifier and block selector decoder is changed corresponding to a position of a selected unit cell objective for data read of the plurality of unit cells.

Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.

Abstract: A register file method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.

Abstract: The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on internal address buses based upon a function being performed by the memory. As such, some, all or none of the externally provided address signals are allowed to transition past address buffer circuitry.

Abstract: Integrated circuit memory devices support write and read burst modes of operation with uniformly short interconnect paths that provide high-speed memory access timing characteristics. These memory devices include a semiconductor chip having a memory core therein and at least N bond pads thereon. The memory core is configured to support a xN burst-M write mode of operation at QDR and/or DDR rates, where N is greater than four and M is greater than one. The memory core is further configured to support one-to-one mapping between burst-M write data received at each of the N bond pads and corresponding ones of N memory blocks in the memory core during the xN burst-M write mode of operation.

Abstract: An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.

Abstract: An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal which causes the start timing of the operation of a row-system circuit to be synchronized with the input timing of a second command. The third circuit is configured to select the first signal when a normal operation mode is specified by the operation mode specifying signal, select the second signal when a test mode is specified, and generate a third signal used to activate at least part of the memory cells in a memory cell array based on a selected one of the first and second signals and the selection signal.

Abstract: A memory device includes a memory cell array, an addressing circuit, a data communication circuit and a control circuit. The addressing circuit receives first signals that are indicative of an address associated with a write command, decodes the address to provide column select signals that are indicative of a column address in the memory cell array, and uses the column address to perform a column redundancy check. The data communication circuit latches data signals that are associated with the write command in response to a data strobe signal. The control circuit causes the addressing circuit to perform the column redundancy check during a delay to accommodate variations in the timing of the data strobe signal and begins providing the column select signals to the memory cell array after performing the column redundancy check. The memory device may be a double data rate (DDR) synchronous dynamic random access memory (SDRAM), for example.

Abstract: A flash memory device is disclosed that includes a control circuit for generating a count-up pulse signal notifying a generation of an address required for a burst read operation. An address generator circuit generates an address in response to the count-up pulse signal, and a discharge circuit discharges global bit lines in response to the count-up pulse signal. According to this control scheme, the global bit lines may be discharged before the local and global bit lines are selected.

Abstract: A control method of a semiconductor memory device which enables control of an operation mode including an operation that might become a noise source by using an operation mode including an operation from which the influence of noise should be eliminated, and a semiconductor memory device are provided. First and second operation sections performing independent operations are provided, and a signal output section for outputting a second signal S2 and a mode controller section for supplying a control signal C1 are provided in the second operation section. The control signal C1 is outputted from the mode controller section and the signal output section outputs the second signal S2 to a memory cell array, thus performing a second operation. A predetermined first signal SS1 is supplied to the signal output section from the first operation section, thus delaying an output response of a predetermined second signal.

Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.