Abstract: A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.

Abstract: A memory device includes an anti-fuse cell array including a plurality of anti-fuse cells. Each anti-fuse cell includes a first cell transistor connected to a common node, a second cell transistor connected to the common node, and an access transistor connected to the common node. The first cell transistor is configured to store data and the second cell transistor is configured to store data when the first cell transistor has defect data.

Abstract: A one-time programmable (OTP) memory cell includes two transistors including a dual gate transistor. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate.

Abstract: A low density One-Time Programmable (OTP) memory is disclosed to achieve low gate count and low overhead in the peripheral circuits to save the cost. A maximum-length Linear Feedback Shift Register (LFSR) can be used to generate 2n?1 address spaces from an n-bit address. The registers used in the address generator can have two latches. Each latch has two cross-coupled inverters with two outputs coupled to the drains of two MOS input devices, respectively. The inputs of the latch are coupled to the gates of the MOS input devices, respectively. The sources of the MOS input devices are coupled to the drains of at least one MOS device(s), whose gate(s) are coupled to a clock signal and whose source(s) are coupled to a supply voltage. The two latches can be constructed in serial with the outputs of the first latch coupled to the inputs of the second latch.

Abstract: Circuits, systems and techniques for testing a One-Time Programmable (OTP) memory are disclosed. An extra OTP bit can be provided as a test sample to be programmed. The programmed extra OTP bit can be read with any virgin cells in the OTP memory alternatively to generate a stream of logic 0 and logic 1 data so that every row or column path can be tested and the outcome can be observed in a pseudo-checkerboard pattern or other predetermined pattern. By carefully setting control signals, checkerboard-like pattern can be generated without actual programming any OTP cells in the memory array.

Abstract: A semiconductor memory device provided with a new bit line hierarchization method that enables further reduction of power consumption is provided. The semiconductor memory device includes multiple memory blocks provided in a matrix configuration and multiple main bit lines provided in correspondence with the memory blocks. Each of the memory blocks includes: multiple memory cells provided in a matrix configuration; multiple sub bit lines provided on a column-by-column basis; multiple word lines provided with respect to each of columns and rows and common to multiple memory blocks; and a switch circuit that couples a corresponding main bit line to any of the sub bit lines. In the operation of reading a target cell as the target of read, a main bit line corresponding to the target cell is selected, a sub bit line corresponding to the column of the target cell is selected through the switch circuit; and a word line corresponding to the column and the row of the target cell is selected from among the word lines.

Abstract: An array of one time programmable (OTP) devices includes a first set of pre-configurable memory devices appended to one or more columns of me array and a second set of pre-configurable memory devices appended to one or more rows of the array. The pre-configurable memory devices may be additional OTP devices or read only memory (ROM) devices that can be configured to store a predetermined test pattern for the array. Rows, columns and functionalities of the array can be tested based on the stored test pattern. OTP devices in the array may then be programmed after successful testing based on the test pattern stored.

Abstract: Described herein is a method for identifying an aberrant feature on a nucleic acid array. In general terms, the method comprises: a) obtaining a log transformed normalized value indicating the amount of hybridization of a test sample to a first feature on the nucleic acid array; b) calculating a z-score for the first feature using: the log transformed normalized value; and the distribution of reference log transformed normalized values that indicate the amount of hybridization of control samples to the same feature on a plurality of reference arrays; and c) identifying the test feature as aberrant if it has a z-score that is above or below a defined threshold.

Abstract: The present invention pertains to the technical field of one-time programmable memory (OTP), and in particular to a one-time programmable memory unit, OTP, and method of fabricating the same. The OTP unit comprises a lower electrode, an upper electrode and a storage medium layer placed between the upper electrode and the lower electrode, the storage medium layer comprises a first metal oxide layer and a second metal oxide layer, wherein an adjoining area for programming is formed between the first metal oxide layer and the second metal oxide layer. The OTP comprises a plurality of the above-described one-time programmable memory units arranged in rows and columns. The OTP unit and the OTP have such characteristics as low programming voltage, small unit area, being able to integrate into a back-end structure of integrated circuit, great process flexibility, and the method of fabricating the OTP unit and the OTP is relatively simple and low in cost.

Abstract: The present invention relates to a method, system and software arrangement for determining the co-associations of allele types across consecutive loci and hence for reconstructing two haplotypes of a diploid individual from genotype data generated by mapping experiments with single molecules, families or populations. The haplotype reconstruction system, method and software arrangement of the present invention can utilize a procedure that is nearly linear in the number of polymorphic markers examined, and is therefore quicker, more accurate, and more efficient than other population-based approaches. The system, method, and software arrangement of the present invention may be useful to assist with the diagnosis and treatment of any disease, which has a genetic component.

Abstract: Systems, methods, and apparatus for determining at least a portion of fetal genome are provided. DNA fragments from a maternal sample (maternal and fetal DNA) can be analyzed to identify alleles at certain loci. The amounts of DNA fragments of the respective alleles at these loci can be analyzed together to determine relative amounts of the haplotypes for these loci and determine which haplotypes have been inherited from the parental genomes. Loci where the parents are a specific combination of homozygous and heterozygous can be analyzed to determine regions of the fetal genome. Reference haplotypes common in the population can be used along with the analysis of the DNA fragments of the maternal sample to determine the maternal and paternal genomes. Determination of mutations, a fractional fetal DNA concentration in a maternal sample, and a proportion of coverage of a sequencing of the maternal sample can also be provided.

Abstract: Multi-time programmable memory elements are disclosed. The disclosed memory elements extend the capability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmability. The disclosed memory elements significantly reduce area requirements and control circuitry complexity of memory elements. The disclosed memory elements can be used in non-volatile memory storage, and are suitable for use in system on chip (SoC) products.

Abstract: A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.

Abstract: A method of generating a ROM bit cell array layout including the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, the memory architecture including a plurality of columns of memory cells, each column of memory cells being located between associated bit lines and virtual ground lines. Adjacent memory cells in each column of memory cells share a common connection to either the associated bit line or the associated virtual ground line. The further steps of evaluating the width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating the layout according to said final width of active area.

Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

Abstract: A one time programming (OTP) memory array is divided into a user section and a test section. The cells in the user section and in the test section are configured to form a checkerboard pattern, that is, having repeats of one user cell and one test cell in both column and row directions. Programming the test section and various additional tests are performed to both the user and test sections and other circuitry of the memory array while the user section is not programmed. Even though the OTP user section is not programmed or tested, the provided tests in accordance with embodiments of the invention can provide a very high probability that the OTP memory including the user section is of high quality, i.e., the OTP cells in the user section can be programmed and function appropriately.

Abstract: A gene assaying method includes the steps of: acquiring two or more data which should be compared and represents expression levels of a plurality of target genes; converting the expression levels represented by the acquired two or more data into ratios based on the expression level of one of the two or more data; extracting a minimum ratio and a maximum ratio of each target gene; and classifying the plurality of target genes using as a classification border at least one of a first ratio with the peak in a frequency distribution of the minimum ratios and a second ratio with the peak in a frequency distribution of reciprocals of the maximum ratios.

Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.

Abstract: Read and write operations of a non-volatile memory (NVM) bitcell have different optimum parameters resulting in a conflict during design of the NVM bitcell. A single bitline in the NVM bitcell prevents optimum read performance. Read performance may be improved by splitting the read path and the write path in a NVM bitcell between two bitlines. A read bitline of the NVM bitcell has a low capacitance for improved read operation speed and decreased power consumption. A write bitline of the NVM bitcell has a low resistance to handle large currents present during write operations. A memory element of the NVM bitcell may be a fuse, anti-fuse, eFUSE, or magnetic tunnel junction. Read performance may be further enhanced with differential sensing read operations.

Abstract: A bit cell of the PROM-device comprises a carbon nanotube having a tilted portion comprising a free end and a fixed portion which is to the reference node. The carbon nanotube comprises a structural defect between the fixed and the tilted portion which causes the carbon nanotube to tilt such that the free end is electrically connected to either the storage electrode or an opposite release electrode.

Abstract: The field programmable read-only memory device comprises a memory cell having a switching element for storing bit information. The switching element provides a switchable electrical connection between word line and a bit line and comprises a static body and a moveable connecting element. The switchable electrical connection is non-volatile.

Abstract: A writing circuit includes storage to store writing data to be written to an OTP macro; a controller to apply a first signal that causes the OTP macro to execute writing of the writing data, and apply a second signal that causes the OTP macro to execute reading of data the OTP macro stores; and a comparator to compare the data read from the OTP macro in response to the second signal with the data stored in the storage and output a comparison result, wherein the controller ends a process associated with the writing data if the comparison result indicates a match, and applies the first and second signals again if the comparison result indicates a mismatch.

Abstract: An apparatus includes a bit cell of a programmable memory circuit. The bit cell includes a programmable device. The bit cell includes a first device having a first type. The first device is configured to conduct a first current between a first node and a second node in response to a first value of a signal on the word line and a signal on a bit line. The programmable device is configured to be programmed in response to a first level of the first current. The bit cell includes a circuit coupled to the second node. The circuit is configured to reduce a leakage current through the first device in response to a second value of the signal on the word line and based on a feedback signal. In at least one embodiment of the apparatus, the feedback signal is based on a signal on the bit line.

Abstract: A method, apparatus, and computer program product for analyzing gene expressions is presented. An operation is performed for determining a gene expression pattern for a condition, wherein the gene expression pattern comprises a gene expression. Next, a spatial-expression pattern is formed by selecting a chromosomal region having an exon; and associating the gene expression within the gene expression pattern with its corresponding exon. A further operation may be performed, where in the forming of the spatial-expression pattern, a spatial-expression pattern signal is created as a representation of the spatial-expression pattern. The magnitude of the spatial-expression pattern signal at any point is determined by an expression level of the corresponding exon. Spatial patterns may be identified in the signal by means of various signal processing techniques such as Fourier or Wavelet transforms.

Abstract: According to embodiment, systems and methods for processing a physiological measurement and generating alarms based on the measurement are provided. Multiple features of a single physiological measurement may be concurrently monitored to generate alarms. One or more of the features may be based on a trend of the physiological measurement. One or more of the features may be based on a wavelet transform of the physiological measurement. Different features may be used in different combinations to lower the percentage of false alarms while still recognizing valid alarm events.

Abstract: A highly safe system for processing information includes: (a) receiving requested information for en object and/or service; (b) obtaining positional information in accordance with the requested information from a memory having positional information representing a position in a nucleotide sequence memorized therein and transmitting the obtained positional information; (c) receiving, from among nucleotide sequence-related information associated with positional information, nucleotide sequence-related information corresponding to the positional information transmitted in step (b) and then obtaining semantic information implied by the received nucleotide sequence-related information and/or information associated with the semantic information; and (d) transmitting the semantic information and/or information associated with the semantic information obtained in step (c) in association with the positional information corresponding thereto to the party to which the positional information had been transmitted in step

Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

Abstract: Aspects of the present invention describe an apparatus and method for generating genotype calls for a sample. The genotyping initially models allelic signal response into an allelic model having one or more model parameters for an identified one or more sources of systematic variation. The model and parameters are then used to transform the allelic signals to a normalized normalized allelic space that serves to compensate for the one or more sources of systematic variation. By compensating for the systematic variation in this manner, the genotype for the sample is readily determined based upon its relationship to the representation of the allelic signals in normalized allelic space and in accordance with the allelic model.

Abstract: A method and system are disclosed for identifying partial order patterns of a set of motifs in a data sequence. The method comprises the steps of obtaining the data sequence, identifying a set of motifs in the data sequence, identifying a plurality of partial orders of the motifs in the data sequence, and using the identified partial orders to identify functions of the motifs. In the preferred embodiment of the invention, the step of identifying the plurality of partial orders of the motifs includes the step of converting the identified motifs to an (n×m) incidence matrix, I, of expressions. Also, in this preferred embodiment, the step of identifying the plurality of partial orders of the motifs includes the steps of computing a partial order description of each of the expressions, and computing a redescription of each of the partial order descriptions.

Abstract: An anti-fuse memory with coupling channel is provided. The anti-fuse memory includes a substrate of a first conductive type, a doped region of a second conductive type, a coupling gate, a gate dielectric layer, an anti-fuse gate, and an anti-fuse layer. The substrate has an isolation structure. The doped region is disposed in the substrate. A channel region is defined between the doped region and the isolation structure. The coupling gate is disposed on the substrate between the doped region and the isolation structure. The coupling gate is adjacent to the doped region. The gate dielectric layer is disposed between the coupling gate and the substrate. The anti-fuse gate is disposed on the substrate between the coupling gate and the isolation structure. The anti-fuse gate and the coupling gate have a space therebetween. The anti-fuse layer is disposed between the anti-fuse gate and the substrate.

Abstract: A storage device contains a smart-card device and a memory device, both connected to a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data in various partitions. One of these partitions may be a read-only partition that is normally accessible only for read accesses. However, it may sometimes be necessary to update or supplement the data stored in the read-only partition. This is accomplished by a host issuing an appropriate command to the storage device, which may be accompanied by an identifier for an appropriate level of authorization. The controller then changes the attribute of the read-only partition from “read-only” to “read/write” to allow data to be written to the partition. Upon completion, the controller changes the attribute of the partition back to read-only.

Abstract: In a memory having a word line driver and a ROM having N bit positions and a plurality of rows in which each row is coupled to a corresponding word line of the word line driver and stores a unique N bit value, a method includes activating, by the word line driver, a selected word line, and, for each bit position, determining whether a value of a true bit line of the bit position is at a same logic state as a value of a complementary bit line of the bit position when the word line driver activates the selected word line. In response to determining that a value of the true bit line is at the same logic state as the value of the complementary bit line for any of the N bit positions, providing a multiple word line fault indicator indicating that multiple word lines are activated simultaneously.

Abstract: A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.

Abstract: This description relates to a circuit including a bit line. The circuit further includes at least one memory bank. The at least one memory bank includes at least one memory cell, a first device configured to provide a current path between the bit line and the at least one memory cell when the at least one memory cell is activated, and a second device configured to reduce current leakage between the bit line and the at least one memory cell when the at least one memory cell is deactivated. The circuit further includes a tracking device configured to receive a minor current substantially equal to a current along the current path, the tracking device configured to have a resistance substantially equal to a cumulative resistance of all memory cells of the at least one memory cell.

Abstract: To include a superlattice laminate having laminated thereon a first crystal layer of which crystal lattice is a cubic crystal and in which positions of constituent atoms are reversibly replaced by application of energy, and a second crystal layer having a composition different from that of the first crystal layer, and an orientation layer that is an underlaying layer of the superlattice laminate and causes a laminated surface of the first crystal layer to be (111)-orientated. According to the present invention, the laminated surface of the first crystal layer can be (111)-orientated by using the orientation layer as an underlaying layer. In the first crystal layer of which laminated surface is (111)-orientated, a crystal structure reversibly changes when a relatively low energy is applied. Therefore, characteristics of a superlattice device having this crystal layer can be enhanced.

Abstract: Provided is a memory device in which the circuit structure is simplified while the functions of a memory including an OTP memory and a memory including a pseudo-MTP memory are maintained. A memory device includes a plurality of memory sets each including a mark bit storage area for storing a mark bit, which indicates that an object is deleted data, and a data bit storage area for storing data to be stored, the memory device being built from a one time programmable (OTP) memory including an OTP memory block and a pseudo-MTP memory block, the OTP memory block containing a given number of memory sets selected out of the plurality of memory sets to operate as an OTP memory, the pseudo-MTP memory block containing the rest of the plurality of memory sets which remains after the memory sets of the OTP memory block are excluded and operates as a pseudo-MTP memory. The mark bit is written in advance in the mark bit storage area of the OTP memory block.

Abstract: Systems and methods are provided for defining a nucleic acid construct for integration at locus L of an organism. Nucleic acid requests are received, each such request specifying a genetic change to L. The request are expanded into component polynucleotides which are then arranged into {AR1, . . . , ARm} different arrangements, each ARi in {AR1, . . . , ARm} defining a different arrangement of the component polynucleotides. A score Si for each ARi in {AR1, . . . , ARm} is determined based on whether source constructs encoding a portion ofARi are physically present. An ARf in {AR1, . . . , ARm} is selected based on the score for ARf. Primer pairs are calculated to amplify the portions of ARf not represented in the source constructs. The portions of ARf amplified by the primer pairs and the portions of ARf in the source constructs, ordered by ARf, define the nucleic acid construct.

Abstract: An information processing apparatus includes: an acquisition mechanism acquiring information on biological time of a user and information on a time difference between a movement source of the user and a movement destination; a storage mechanism storing model information produced by modeling a sunshine pattern, an expression pattern of a clock gene of a neuron of a ventrolateral area of a suprachiasmatic nucleus, and an expression pattern of a clock gene of a neuron of a dorsomedial area; and when a sunshine pattern of the movement source is changed in accordance with the time difference so as to become a sunshine pattern of the movement destination, a simulation mechanism simulating the expression pattern of the ventrolateral area and the expression pattern of the dorsomedial area on the basis of the model information using a state identified by the biological time as a starting state.

Abstract: Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line.

Abstract: A gene classifying method is provided and includes acquiring expression levels of a plurality of genes at a plurality of observation points, generating a binary string by taking a positive or negative difference in expression level in a temporal passage direction of the observation points for each gene, and classifying the genes on the basis of all plus and minus patterns that the binary strings can have and the generated binary strings.

Abstract: A memory circuit includes a plurality of bit lines. A first memory cell and a second memory cell are coupled in series. Each of the first memory cell and the second memory cell is capable of storing a first type datum. The first memory cell and the second memory cell share a first common source/drain (S/D) region. The first common S/D region is electrically isolated from all of the bit lines.

Abstract: An apparatus includes a bit cell of a programmable memory circuit. The bit cell includes a programmable device. The bit cell includes a first device having a first type. The first device is configured to conduct a first current between a first node and a second node in response to a first value of a signal on the word line and a signal on a bit line. The programmable device is configured to be programmed in response to a first level of the first current. The bit cell includes a circuit coupled to the second node. The circuit is configured to reduce a leakage current through the first device in response to a second value of the signal on the word line and based on a feedback signal. In at least one embodiment of the apparatus, the feedback signal is based on a signal on the bit line.

Abstract: Methods and apparatus are provided for a solid state non-volatile storage sub-system of a computer. The storage sub-system includes a write-once storage sub-system memory device and a write-many storage sub-system memory device. The write-once storage sub-system memory device includes a recoverable system configuration. Numerous other aspects are provided.

Abstract: An OTP memory array includes a bit line coupled to a plurality of memory banks. Each memory bank includes a plurality of memory cells, a footer, and a bias device, and is associated with a current mirror. When a memory cell is activated (e.g., for reading) the memory bank including the activated memory cell is referred to as an activated memory bank and other banks are referred to as deactivated memory banks. A current tracking device serves to compensate for bit line leakage current in deactivated memory cells in the activated memory bank. Further, footers and bias devices in deactivated memory banks and associated current mirrors are configured to reduce/eliminate bit line current leakage through deactivated memory cells in deactivated memory banks.

Abstract: A gene expression level analyzing method includes the steps of: acquiring expression levels of a plurality of target genes in a target cell every measurement time; extracting a maximum expression level and a minimum expression level from the expression levels of the target genes every measurement time; calculating a correlation coefficient of a frequency distribution of the gene having the maximum expression level at each measurement time and a frequency distribution of the gene having the minimum expression level at each measurement time; and comparing the correlation coefficient with a threshold value of the correlation coefficient.

Abstract: A method of operation of a programmer actuator system includes: placing a programming assembly, having socket boxes, in the programming actuator system; and clamping the programming assembly in the programming actuator system using a pivoting arm bracket.

Abstract: Embodiments relate to a manufacturing method of a one time programmable (OTP) memory device including: forming a common source in a linear configuration on a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate at both sides of the source; forming a gate over the gate dielectric layer; forming a spacer between the gates and at both side walls of the gate; and forming a drain on the semiconductor substrate at both sides of the spacer. With embodiments, the OTP memory device can be formed together with the logic part using the logic process and can increase the storage capacity of the OTP memory device by improving density of memory arrays.

Abstract: Provided are a memory device where data may be recorded one time and/or reproduced repeatedly, and a method and display apparatus for operating the memory device. The memory device may include a program area having a plurality of memory cells and a spare area having a plurality of memory cells. The memory device may include a memory cell layer having the program area and the spare area. The memory cell layer may include a plurality of vertically stacked memory cell layers. Each of the plurality of memory cell layers may include the program area and the spare area. The program area and the spare area may be either vertical or horizontal to one another.

Abstract: According to embodiments, systems and methods are provided for filtering a signal. A first reference signal may be generated according to a signal model and a second reference signal may be generated by analyzing a continuous wavelet transform of a signal. The first and second reference signals may then both be applied to an input signal to filter the input signal according to the components of both of the reference signals.

Abstract: A high performance memory based computation system comprises an array of memory cells. Each memory cell stores a logic data corresponding to a chosen combination of inputs based on a specific logic function. For improved performance, the memory cell array can be divided into sub-blocks; and the sub-blocks can be serially disposed or juxtaposed. The performance of the memory based computation system can further be improved by removing the repeated memory cell rows, column, and/or sub-arrays.