Abstract: A system and method for multi-channel network congestion control. A method includes establishing multi-channel control over a plurality of communication channels by connecting each of the plurality of communication channels to a scheduling component and to a synchronizing component; determining a packet routing scheme for a plurality of packets of a data stream based on feedback from each of the plurality of communication channels, wherein the packet routing scheme includes a routing of each packet to a respective communication channel of the plurality of communication channels; and sending the plurality of packets via their respective communication channels, wherein each of the sent packets includes timing data, wherein the synchronizing component is configured to synchronize the plurality of packets based on the timing data of each packet and to reconstruct the data stream using the synchronized packets.

Abstract: A system includes a data carrier drive apparatus and a data carrier apparatus. The data carrier apparatus includes a unit to output transmission data during a first state and adjustment data during a second state, and a current changer configured to change a current value of a current flowing from the data carrier drive apparatus to the data carrier apparatus according to data values of the transmission data and the adjustment data. The data carrier drive apparatus includes a detector to detect a detection value corresponding to the current value of the current, a determiner to determine the data value of the transmission data by comparing the detection value with a threshold value during the first state, and an updater to update the threshold value based on the detection value during the second state.

Abstract: An integrated circuit is provided that comprise a receive unit to be tested for receiving an input signal and storing the input signal at a predetermined point of time. Additionally, it comprises a processor for applying an error correction to the received input signal, for comparing the error corrected signal with an expectation value and for outputting an error message when the filtered input signal does not correspond to the expectation value. A power source supplies the receive unit to be tested with an adjustable voltage and/or and adjustable current. An adjustment unit varies the predetermined point in time and the adjustable voltage respectively the adjustable current.

Abstract: An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

Abstract: A method at a first device for synchronising a first clock of the first device to a second clock of a second device, includes receiving a first message comprising an identifier from a third device; generating a first timestamp in dependence on the time at which the first message is received at the first device according to the first clock; receiving a second message from the second device comprising the identifier and a second timestamp, the second timestamp having been generated in dependence on the time at which the second device received the first message from the third device according to the second clock; and adjusting the first clock in dependence on a time difference between a time indicated by the first timestamp and a time indicated by the second timestamp.

Abstract: An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

Abstract: Methods and apparatus for synchronization of media playback within a wireless network. In one embodiment, the present disclosure is directed to precision synchronization over time, based on repeated measurements of a common time reference. In one exemplary embodiment, the common time reference is a Time Synchronization Function (TSF) of a Wireless Local Area Network (WLAN). In another exemplary embodiment of the present disclosure, the application processor and the modem processor measure a pulse width and the aforementioned common time reference in order to adjust media playback.

Abstract: A system for verifying clock synchronization between master and slave network equipment is provided. The master includes a transmitter, first control logic, and a first processor. The slave includes a receiver, second control logic, and a second processor. The transmitter may send synchronization packets to the receiver. When a synchronization packet is sent, the first control logic forwards a first timestamp sample to the first processor. In response to receiving a synchronization packet, the receiver may generate a second timestamp sample that is forwarded to the second processor. When a number of first timestamp samples are collected at the first processor, the transmitter may send a timestamp packet to the receiver. In response to receiving the timestamp packet, the receiver may compare the first and second timestamp samples in an effort to synchronize a slave reference clock in the slave to a master reference clock in the master.

Abstract: A method for frequency synchronization of a multiport device may include recovering a clock frequency of a master port of a first device that is linked to the multiport device at a slave port of the multiport device. A clock frequency of the slave port may be locked to the recovered-clock frequency of the master port of the first device. Frequency data may be stored in a first frequency register associated with the slave port. The stored frequency data may include a difference between the recovered-clock frequency of the master port of the first device and a local-clock frequency of the multiport device. A clock frequency of one or more master ports of the multiport device may be synchronized with the locked clock frequency of the slave port by coupling the first frequency register to frequency registers associated with one or more master ports.

Abstract: A system for compensating for periodic noise in a time interleaved system having multiple phases of interest includes a master clock path, a detection circuit and an actuator circuit. The master clock path is configured to receive an input clock and to output an output clock, each of the input and output clocks having periodically occurring interleaving periods. Each interleaving period includes timeslots corresponding to the phases of interest of the time interleaved system. The detection circuit is configured to receive the input and output clocks for each timeslot, and to detect periodic noise in the output clock introduced by the master clock path by comparing the received input and output clocks. The actuator circuit includes a controllable delay element configured to adjust a delay of the input clock through the master clock path to compensate for the periodic noise detected by the detection circuit for each timeslot.

Abstract: In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities.

Abstract: The present invention provides a method for range extension is wireless communication systems. One embodiment of the method includes determining whether a mobile unit is within a first range corresponding to a range of timing advances supported by a timing advance command. This embodiment also includes transmitting a plurality of timing advance commands to the mobile unit when the mobile unit is outside the first range so that the mobile unit can synchronize with the base station by combining information in the plurality of timing advance commands.

Abstract: A method and apparatus for delivering screen display data to existing display devices. Some embodiments of an apparatus include an interface to receive an input stream for a display device. The apparatus further includes a module to generate on screen display data for the display device. The apparatus includes a multiplexer, the multiplexer to multiplex the on screen display data into the input stream.

Abstract: A method for synchronizing network elements to a global clock derived from the GPS clock acquired by a plurality of base stations. The global clock is distributed to controllers of various networks, and from there to network access devices. The network access devices further distribute the global clock to various wire-line and local wireless networks and from there, to the users served by these networks. The user equipment is enabled with a simple clock discipliner that adjusts the local clock to the global clock, resulting in a reliable synchronization across the converged communication networks.

Abstract: A portable electronic apparatus has a first storage section configured to store information to be communicated to the processing apparatus and formats for a frame to be transmitted to the processing apparatus, in association with one another. The processing apparatus has a second storage section configured to store information communicated by the portable electronic apparatus and the format of the frame transmitted by the portable electronic apparatus, in association with each other. The portable electronic apparatus select one of the formats stored in the first storage section based on the data to be transmitted to the processing apparatus. The processing apparatus recognize information communicated by the portable electronic apparatus based on the format of the frame received from the portable electronic apparatus.

Abstract: In a computer-implemented method of adjusting a local clock at a receiver in a packet network, the local clock is generated by a phase locked loop locked to a master clock with the aid of time-stamped timing packets arriving over the network from the master clock with a packet delay distribution about a nominal delay. The timing packets are filtered to adjust for the packet delay distribution. A control input for the phase locked loop is derived from the timing packets. The amount of skew in the packet delay distribution about the nominal delay is determined, and the arrival times of timing packets are then selectively modified to correct for the amount of skew in the packet delay variation distribution prior to filtering the timing packets.

Abstract: The present disclosure relates to systems and methods for geographically-diverse redundant servers and the like interconnected via wavelength division multiplexed (WDM) systems with managed path differential delay of the WDM systems. The present disclosure provides transport systems and methods incorporating absolute time references, such as global positioning system (GPS) time references and/or the like, and selective buildout delays, such as first-in, first-out (FIFO) buildout delays and/or the like. In one exemplary embodiment, the transport systems and methods of the present invention are used in conjunction with the International Business Machine Corporation (IBM) Geographically-Dispersed Parallel Sysplex (GDPS) integrated, automated application and data availability solution to meet and/or exceed the associated 10 microseconds transmit/receive path differential delay requirement. Other comparable uses are also contemplated herein, as will be obvious to those of ordinary skill in the art.

Abstract: A communications device includes a phase and frequency tracking loop having a signal input and adjustable loop filter that establishes a predetermined tracking loop bandwidth for samples of communication signals received at the signal input and processed within the tracking loop. A tracking loop update circuit updates the loop filter operating parameters. It is operative with the loop filter for increasing or decreasing the tracking loop bandwidth of the phase and frequency tracking loop based on the measured signal-to-noise ratio in the received samples of communication signals at the signal output by the tracking loop and on the known or measured apriori tracking capabilities of demodulator based on the symbol rate of communication signal.

Abstract: Systems and techniques are disclosed wherein a gated pilot signal can be re-acquired faster by searching a last known pilot offset and/or searching a last coset in which the last pilot signal was found.

Abstract: A method of synchronizing decoders within a network to a server includes receiving a set of timestamps and local clock signals upon receiving the beacon interrupt signal, computing differential timestamp and local clock values based on values of timestamp and local clock signals, respectively, within the sets of timestamp and local clock signals, determining whether the differential local clock value has a predetermined relationship with the differential timestamp value, and transmitting a clock rate adjustment command signal to the decoder when differential local clock value does not have the predetermined relationship with the differential timestamp value. The clock rate adjustment command signal adjusts the local system time clock of the decoder such that a subsequent differential clock value will have the predetermined relationship with the differential timestamp value.

Abstract: The invention relates to an automation device, with which a multiplicity of physically distributed functional units communicate with each other by means of a common transmission protocol. The device has a microcontroller (110), which is assigned at least one clock generator (120) and one memory unit (150), and which is connected at least to one data source (140), which is designed to output a data bit-stream to be transmitted. A sequential sequence of equidistant samples of a trapezoidal time profile is stored in the memory unit (150), such that it can be called up, in such a manner that the samples can be output either using the clock of the first clock generator or using the clock of the second clock generator, depending on the data bit-stream.

Abstract: Embodiments of a multi-radio wireless communication device and methods for synchronizing wireless network and Bluetooth (BT) communications are generally described herein. Other embodiments may be described and claimed. In some embodiments, a BT radio module adjusts a master clock signal by a predetermined step size before each subsequent BT transmission in response to a frame sync pulse from a wireless network radio module to reduce a time difference between subsequent frame sync pulses and synchronization reference points of BT slots.

Abstract: An apparatus for reproduction of an image frame in an image receiving system is disclosed. The apparatus includes a demultiplexer for restoring a received signal to a decodable bitstream and generating start information of each image frame of the bitstream, and an image decoder for decoding the bitstream restored by the demultiplexer, thereby generating a reproducible I frame or P frame, which is an image frame; an image reproduction time uniformity processing module for buffering each image frame output from the image decoder, and then outputting the buffered I frame or P frame while delaying the I frame or P frame based on the start information of each image frame provided by the demultiplexer according to a preset delay time. The present delay time has been preset to be greater than a processing time period required for decoding of an I frame and to be less than a time interval between image frames in the image bitstream.

Abstract: In one embodiment, a monitor circuit is disclosed. For example, the monitor circuit includes a first delay line circuit having a plurality of delay taps for receiving data from a data channel, and a second delay line circuit having a plurality of points for sampling the data received from the first delay line circuit, where the plurality of points comprises an input point, a middle point and an output point. The monitor circuit further includes a voltage control circuit for providing a control voltage to the second delay line circuit, and a data compare circuit for comparing a data value of the input point and a data value of the middle point to produce a first out-of-bounds signal, and for comparing the data value of the middle point and a data value of the output point to produce a second out-of-bounds signal.

Abstract: A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.

Abstract: A method and system communicates payload data over a plurality of low voltage differential signaling (LVDS) channels (50). First device (100) transmits the payload data and synchronization information to the second device (150) over N LVDS channels (50), along with a word clock synchronized to the payload data. The second device generates M LVDS receive clocks from the word clock, each having a same frequency that is P times a frequency of the word clock, and each having a different phase. Each of N LVDS receivers (160) of the second device (150): correlates the synchronization data with a reference word using each of the M LVDS receive clocks to produce a correlation value for each of the M LVDS receive clocks; selects a selected LVDS receive clock producing a greatest correlation value; and receives the payload data for the corresponding LVDS channel (50) using the selected LVDS receive clock.

Abstract: An optical signal return path system analog RF signals are sampled using a master clock frequency, and combined with digital data such as Ethernet data at a cable node. The cable node sends the combined signals on a return path over a fiber optic medium to the cable hub. The cable hub extracts an approximate in-frequency replicate of a master clock signal, and can use the replicate master clock signal to desample the digitized RF signals back to analog. The cable hub can further use the replicate of the master clock signal to serialize Ethernet data, and send the Ethernet data back to the cable node via an optical cable in the forward direction. Accordingly, a single master clock signal can be used on a CATV network for encoding/decoding, and transmitting a variety of data signals, which enhances the integrity and reliability of the data signals.

Abstract: A system and a method of transmitting data from a first device to a second device, both devices receiving a clock signal, the first device acting on a first flank of the clock signal and the second device acting on a second flank of the clock signal. A chain of this type of devices may be used, where every second device acts on the first flank and the others on the second flank. In this manner, the data transport may be provided at the clock frequency while allowing backpressure.

Abstract: In a wireless communication system using a reference channel used for error rate measurement and associated with a plurality of transport channels multiplexed on a coded composite transport channel (CCTrCH), a method is employed for reselection of the reference channel from favorable candidate transport channels. A channel is initially selected from the plurality of multiplexed channels as the reference channel. Channels are monitored based on quantitative data content criteria to determine whether an ON or OFF state exists. A different channel is selected from the plurality of multiplexed channels as the reselected RTrCH when a better candidate transport channel in the ON state becomes available, or when the monitored RTrCH reflects an OFF state.

Abstract: A communications system includes a physical layer device (PLD) and a logical link device (LLD), each having respective send and receive interfaces being substantially identical to define symmetrical interfaces for the system. Accordingly, design and manufacturing is simplified compared to conventional systems. In addition, advantages are also provided in terms of loopback capability and packaging options. The PLD comprises a PLD send interface including PLD parallel information outputs, and a PLD receive interface including PLD parallel information inputs. Similarly, the LLD comprises an LLD receive interface including LLD parallel information inputs, and an LLD send interface including LLD parallel information outputs. Parallel communications channels connect the PLD information outputs to respective LLD information inputs, and connect the LLD information outputs to respective PLD information inputs.

Abstract: A method and system for providing multi-channel circuit emulation clock recovery wherein a single instance of the clock recovery logic effects circuit emulation clock recovery for multiple channels. For one embodiment of the invention, fine tuning clocking is effected by comparing an outgoing clock with a recovered clock and switching a clock recovery mechanism, the switching performed in conjunction with a multi-channel context.

Abstract: A communications system for controlling equipment associated with a vehicle, includes a micro-controller (604) and a digital serial communication link (621, 622, 662, 663) using a multiplexed timing signal and first data signal. A camera or image sensor (650) located in the vehicular component communicates with the micro-controller (604) via the digital serial communication link.

Abstract: A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. A best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.

Abstract: Various exemplary embodiments include a method and related system and monitoring entity including one or more of the following: generating timing information at a master node in a packet-switched network, the timing information specifying a value of a master clock; communicating the timing information from the master node to a plurality of slave nodes over a first plurality of time-division multiplexing (TDM) pseudowires; running a digital phase-locked loop on each slave node to synchronize each slave node to the master clock, wherein each digital phase-locked loop outputs a frequency at which the respective slave node is operating; sending the frequency outputted by each digital phase-locked loop to a monitoring entity over a second plurality of TDM pseudowires; utilizing the outputted frequencies at the monitoring entity to identify all slave nodes that are experiencing timing problems; and implementing a remedial measure for all slave nodes that are experiencing timing problems.

Abstract: A unit timing signal synchronized with a high-order transmission frame is used for measuring a difference between the number of data pieces of a client signal mapped to the high-frequency frame and the number of data pieces of the output client signal by integrating the difference therebetween for each unit timing signal. Then stuffing and de-stuffing operations are performed so that a integration result is zero.

Abstract: A method and mechanism for monitoring performance in a network computing system. A user application on a source system is configured to communication with a destination system. The application is configured to load a dynamic linked library upon execution. The dynamic linked library is configured to store packet identifiers and time stamp information for communication packets received from the application prior to the packets being conveyed to the destination system. Upon receipt of an acknowledgement packet from the destination system, the library code is configured to retrieve the previously stored time stamp information, determine transit latency information corresponding to the communication packet, and log the determined transit latency information. Acknowledgement packets may further include time stamp information which may be utilized to determine additional latency information corresponding to the communication packet and/or acknowledgement packet.

Abstract: Disclosed are a method and system to estimate the maximum error in the clock offset and skew estimation between two clocks in a computer system. The method comprises the steps of obtaining a first set of data values representing a forward delay between the first and second clocks, and obtaining a second set of data values representing a negative backward delay between the first and second clocks. The method comprises the further step of forming a lower convex hull for said first set of data values, and forming an upper convex hull for said second set of data values. First and second parallel lines are formed between the upper and lower convex hulls, and these parallel lines are used to estimate the worst case error for the offset, skew rate and dispersion of said first and second clocks.

Abstract: Virtual concatenation circuitry is disclosed for implementation in a network element of a data communication network. The virtual concatenation circuitry in a preferred embodiment is operative: (i) to maintain, for each of the individual member streams of a virtual concatenation stream, a corresponding counter which tracks pointer adjustments for that member stream; and (ii) to generate pointers based on values of the counters so as to substantially equalize incoming and outgoing pointer adjustments for the member streams at the network element.

Abstract: A system and method for closely synchronizing the transmission of real-time data streams is described. Synchronization data is transmitted by a cycle master for receipt by one or more cycle slaves. A cycle slave updates an internal state based on synchronization data received from the cycle master. This internal state may govern reproduction of received real-time data streams by the cycle slave. Such synchronization data may be inserted into transmitted media streams. The cycle slave internal state may be more accurately set by calculating timing differences between the cycle master and cycle slave and periodically adjusting that internal state between receipt of the synchronization data from the cycle master.

Abstract: Local Interconnect Network message budget calculation error is reduced by utilizing an eight bit time measurement of the sync byte in the message header. The method determines the header budget separately from the data budget, simplifying the required logic. The sync byte reference time is multiplied by the message data size to determine the data budget.

Abstract: The invention comprises a method and apparatus for adapting plesiochronous hierarchical layered data to produce synchronous hierarchical layered data. Similarly, the invention comprises a method and apparatus for adapting synchronous hierarchical layered data to produce plesiochronous hierarchical layered data.

Abstract: A wireless LAN can be used to support audio communication sessions between wireless communication devices and wired communication devices both configured to operate according to the Internet Protocol. Both the wired and wireless communication devices generate and transmit frames of voice information over the LAN to each other and in the process of generating these frames they place a timestamp in each frame that is used by a receiving communications device to determine when the frame should be played in relationship to all of the other frames of voice information it receives. At times these communication devices can place incorrect timestamp values in the frames of audio information which can affect the quality of the communication experience for a user. I propose to correct any incorrect timestamp values by first recognizing that a timestamp value is incorrect and then rounding the value to the nearest frame boundary.

Abstract: Methods and apparatus for controlling latency variation of packets received in a packet transfer network are provided. A plurality of packets is received at a network element of a receive node of the packet transfer network. A time-stamp is provided for each of the plurality of packets. An egress delay time is computed at a scheduler of the network element for each of the plurality of packets in accordance with each corresponding time-stamp to provide a substantially constant latency for the plurality of packets upon egression from the network element.

Abstract: A system and method for minimizing transmit latency uncertainty in a 100 Mb RMII Ethernet physical layer device is disclosed. A 100 Mb RMII Ethernet transmit physical layer device comprises a divide circuit that selects a phase of a transmit clock signal for transmitting data. The invention comprises a reset circuit that aligns the divide circuit to select an optimal phase of the transmit clock signal for transmitting data. The reset circuit of the invention is capable of reducing the transmit latency uncertainty from approximately twenty nanoseconds to four nanoseconds.

Abstract: A method of allocating sub-channel signal interleaving patterns to BSs forming a wireless communication system that divides a frequency band into a plurality of sub-carriers and including a plurality of sub-channels, which are a set of predetermined adjacent sub-carriers. The method includes: creating a basic orthogonal sequence having a length identical to a number of the sub-carriers forming the sub-channel; creating a plurality of sequences having a same length as the basic orthogonal sequence by cyclic-shifting the basic orthogonal sequence a predetermined number of times or performing a modulo operation based on a number of the sub-carriers forming the sub-channel, after adding a predetermined offset to the cyclic-shifted basic orthogonal sequence; selecting a predetermined number of sequences corresponding to a number of the BSs from among the plurality of sequences; and allocating the selected sequences as the sub-channel signal interleaving patterns for the BSs.

Abstract: A synchronization system (D) for equipment of a synchronous transport network comprises, firstly, a first synchronization module (MA) comprising i) a first submodule (SM1A) delivering a first intermediate clock signal derived from a first external reference clock signal or an internal reference clock signal, ii) a second submodule (SM2A) delivering a first main reference clock signal derived from the first intermediate clock signal or a second intermediate clock signal, and iii) a third submodule (SM3A) delivering a first output reference clock signal derived from the first main reference clock signal or a second main reference clock signal, and, secondly, a second synchronization module (MB) comprising i) a first submodule (SM1B) delivering the second intermediate clock signal derived from another first external reference clock signal and another internal reference clock signal, ii) a second submodule (SM2B) delivering the second main reference clock signal derived from the first or the second intermediate c

Abstract: A clock filter circuit (20), which serves for filtering the clock of non-isochronous data signals having a selected one of at least two nominal data rates, has an auxiliary clock source (21) that generates an auxiliary clock signal (27) with a pulse repetition rate which is in the range between the at least two predetermined data rates, a delay line (22) connected to the auxiliary clock source (21) for creating a set of mutually delayed copies of the auxiliary clock signal and a multiplexer (23) that switches in a cyclic order between the delayed copies according to predetermined rules, which depend on the selected data rate to generate a filtered clock signal (28). A control circuit determines whether the rate of the filtered clock (28) signal must be increased or decreased as compared to said data signal and controls the multiplexer (23) to delay or advance the cyclical switching accordingly.

Abstract: Disclosed are a method and system for estimating the skew and offset between two clocks in a computer system. The method comprises the steps of obtaining a first set of data values representing a forward delay between the first and second clocks, and obtaining a second set of data values representing a negative backward delay between the first and second clocks. The method comprises the further steps of forming a lower convex hull for said first set of data values, and forming an upper convex hull, above the lower convex hull, for said second set of data values. The clock offset and the skew between said first and second clocks are estimated using those convex hulls. In a preferred embodiment, this estimation is made by identifying a best clock line between the first and second convex hulls.

Abstract: A novel clock synchronization mechanism for recovering and distributing a centralized clock source synchronously over asynchronous networks such as optical Ethernet. A clock conversion scheme is provided whereby multiple clocks having diverse rates are converted to clock signals all having a common rate. One of the converted clocks is chosen and all downstream clock signals is derived from this clock. A high quality clock source located anywhere on the network is distributed throughout the network thus turning an asynchronous Ethernet network into a synchronous one. Synchronous TDM data streams can then be easily transported over the Ethernet network.

Abstract: A novel clock method and synchronization mechanism for recovering and distributing a centralized clock source synchronously over legacy asynchronous network devices such as legacy optical Ethernet devices that do not support synchronous Ethernet. An external device functions transparently to provide legacy optical Ethernet devices a clock synchronization and distribution mechanism. The external devices implement a clock conversion scheme whereby multiple clocks having diverse rates are converted to clock signals all having a common rate. One of the converted clocks is selected and all downstream clock signals are then derived from this clock. A high quality clock source located anywhere on the network is distributed throughout the network thus turning an asynchronous Ethernet network into a synchronous Ethernet network. Synchronous TDM data streams can then be easily transported over the Ethernet network.