Abstract: An optical receiver including: a preamplifier capable of changing a conversion gain in accordance with a reception level of a received burst signal; a gain control circuit capable of switching between a fast time constant and a slow time constant; and a convergence determination circuit for outputting a time constant switching signal in accordance with a state of the gain control circuit (transient state or steady state) and a reset signal between the burst signals. This configuration can switch the time constant of the gain control circuit at an appropriate timing.

Abstract: A variable-precision distributed arithmetic (VPDA) multi-input multi-output (MIMO) equalizer is presented to reduce the size and dynamic power of 112 Gbps dual-polarization quadrature phase-shift-keying (DP-QPSK) coherent optical communication receivers. The VPDA MIMO equalizer compensates for channel dispersion as well as various non-idealities of a time-interleaved successive approximation register (SAR) based analog-to-digital converter (ADC) simultaneously by using a least mean square (LMS) algorithm. As a result, area-hungry analog domain calibration circuits are not required. In addition, the VPDA MIMO equalizer achieves 45% dynamic power reduction over conventional finite impulse response (FIR) equalizers by utilizing the minimum required resolution for the equalization of each dispersed symbol.

Abstract: A communication level table storage unit stores a communication level table that defines correspondence between a communication level at least defined by MCS (modulation scheme and coding rate) and a range of required CINR at the communication level. A communication quality management unit obtains CINR of a received signal at another communication apparatus which is a communication partner. A setting unit refers to the communication level table, and when a difference between a representative value of a range of required CINR at a current communication level and a representative value of a range of required CINR of CINR at a communication level which is one level higher is more than or equal to a threshold value, sets a communication level such that the obtained CINR of the received signal is included in the range of required CINR.

Abstract: In one embodiment, a receiver may receive a signal from a transmitter. The receiver may include a first sampler that may sample the signal when the value of the signal is zero. The receiver may further include a second sampler that may sample the signal halfway between a time when the first sampler samples the signal and the next time when the first sampler samples the signal to produce a set of sampled values. The receiver may be further operable to determine that a sampled value in the set of sampled values is a logic 1 if the sampled value is greater than the value of a reference voltage and that the sampled value is a logic 0 if the sampled value is less than the value of the reference voltage.

Abstract: A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface settings. The computer system further includes a memory containing machine executable instructions. Execution of the instructions causes the processor to: monitor communications traffic on the at least one interface; store, eye distribution data acquired during the monitoring of the communications traffic in a database; compare the eye distribution data to a set of predetermined criteria; and generate a set of updated interface settings if the eye distribution does not satisfy the set of predetermined criteria.

Abstract: Methods and apparatuses for adaptable receiver detection are provided. Embodiments include providing, by receiver detection circuitry at a transmitter coupled to a communication link, a voltage to the communication link; determining, by the receiver detection circuitry, a rise time corresponding to a rising edge change of the voltage on the communication link; determining, by the receiver detection circuitry, a fall time corresponding to a falling edge change of the voltage on the communication link; and determining, by the receiver detection circuitry, whether the rise time and the fall time are consistent with the transmitter being coupled through the communication link to a remote receiver.

Abstract: One embodiment relates to a method of adapting a receiver for equalization of an input data signal. A variable gain amplifier (VGA) loop adapts a VGA circuit using an initial threshold voltage so as to adjust a VGA gain setting to regulate a data amplitude feeding into a decision feedback equalization (DFE) circuit. In addition, the DFE adaptation loop may adapt the DFE circuit using the initial threshold voltage. When the adaptation of the VGA is done, then the VGA gain setting is frozen and adaptation of the threshold voltage may be performed by a threshold adaptation loop. Another embodiment relates to a system which includes a DFE adaptation circuit module, a CTLE adaptation circuit module, and a threshold adaptation circuit module that adapts a threshold voltage that is fed to the DFE adaptation circuit and the CTLE adaptation circuit. Other embodiments and features are also disclosed.

Abstract: Provided is a method and apparatus to adaptively set a threshold for signal demodulation. The apparatus and the method include adaptively setting a threshold to demodulate a currently received symbol based on the demodulation value of a previously received symbol based on a comparison value. The comparison value is obtained by comparing a number of previously received symbols having a demodulation value of “0” and a number of currently received symbols having a demodulation value of “1”.

Abstract: A DTV pilot tone is detected in a noisy environment by computing a power average of Fast Fourier Transform (FFT) output spectra of a received signal, finding a power peak in the averaged outputs, computing an adjustment parameter to center the power peak in a Discrete Fourier Transform bin of the averaged output spectra, applying the adjustment parameter to adjust the received signal, computing a coherent average of FFT output spectra of the adjusted signal, and, testing a power spectrum of the coherent average for the presence of the DTV pilot tone.

Abstract: Methods for receiving a signal and a detection circuit are disclosed. The detection circuit and related methods may be useful for the fast and accurate receiving of data signals. The detection circuit generally comprises a first circuit having a first time constant, a second circuit having (i) a common input with the first circuit and (ii) a second time constant, the second time constant being less than the first time constant, and a switch configured to (i) charge the first circuit with an input signal when the switch is in a first state, and (ii) charge or discharge the second circuit with the input signal when the switch is in a second state, the switch having the second state when the input signal is no longer received at the common input.

Abstract: A method and apparatus for adjusting a symbol decision threshold at a receiver in a communication network enables the receiver to be adapted to more correctly receive symbols as transmitted by a transmitter. In one embodiment, a received bit imbalance is detected by a receiver prior to error correction and after error correction to determine whether an error component of the received signal contains larger numbers of ones or larger numbers of zeros. Where the transmitter scrambles the signal prior to transmission, the receiver will also scramble the signal after error correction and prior to counting the number of zeros or ones. Any imbalance between the number of transmitted and received ones or zeros is used as feedback to adjust threshold values used by detectors to fine tune the manner in which the receiver interprets incoming signals.

Abstract: As single-ended signaling is implemented in higher-speed communications, accurate and consistent reading of the data signal becomes increasingly challenging. In particular, single-ended links can be limited by insufficient timing margins for sampling a received input signal. A single ended receiver provides for improved timing margins by adjusting a reference voltage used to sample the input signal. A calibration pattern is provided to the receiver as the input signal, and the reference voltage is adjusted toward a median value of the signal.

Abstract: A direct-conversion type wireless receiver includes a pair of mixers for frequency-converting a radio signal received from an antenna into a base band signal by local signals having different phases; a first amplification circuit for amplifying the base band signal up to a demodulation level; a second amplification circuit provided between the mixer and the first amplification circuit; and a variable current circuit including a multi-stage current mirror to add a current 2n times as high as a reference current. The wireless receiver further includes a control unit configured to correct a DC offset of the mixer by allowing a current to flow into the second amplification circuit from the variable current circuit, based on an output of the first amplification circuit, and a capacitor connected between a gate and a source of a PchMOSFET which allows the reference current to flow therethrough.

Abstract: A mechanism is provided for dynamically adjusting DC offset at the time of deviation from DC balance ½ (DC level) in a data pattern including long-period consecutive bits generating DC offset in a section of data. A receiver circuit unit of an LSI having a serializer/deserializer arrangement for performing high-speed serial transmission includes an offset adjusting circuit. The offset adjusting circuit calculates DC balance in an arbitrary section of data by averaging received serial data. Based on comparison between a DC level and the DC balance obtained by averaging the received data, offset is shifted toward the H side when the DC balance exists on the H side from the DC level, and shifted toward the L side when the DC balance exists on the L side.

Abstract: Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link.

Abstract: Eye diagram scan circuit and associated method for a receiver circuit, including a level adjust circuit, a phase interpolator and a control module. The receiver circuit provides a first data signal and a primary phase data according to a received signal. The control module provides a phase offset data and a level offset data. The level adjust circuit adjusts a level of the received signal in respond to the level offset data; the phase interpolator triggers according to a sum of the phase offset data and the primary phase data, so a second data signal is provide in response to the level-adjusted received signal. The control module compares the first data signal and the second data signal, and accordingly provides an eye diagram scan result for the phase offset data and the level offset data.

Abstract: A signal handling device (14) for handling a signal (S2, S3, S4) transmitted through a body, where the signal is coded with a coding scheme and associated clock rate, comprises a receiving unit (22) configured to receive the signal (S2), a signal sampler (30) configured to sample at least a section of the signal with a sample rate that is higher than the clock rate of the coding scheme and form at least one series of samples of the signal (S4), where the samples of a series have been sampled at a sampling position periodically recurring according to the clock rate, and a data analyser (32) configured to investigate if said at least one series fulfils a data sequence detection criterion, and set a sampling position for which a series of samples fulfils the data sequence detection criterion to be an operative sampling position.

Abstract: Provided is a pulse receiver capable of receiving a burst signal and decoding the burst signal with a bit error rate reduced to a target value or less by controlling a determination threshold such that decoding success rate is equal to or less than a predetermined value. A decode unit 140 decodes a pulse train 20 to information 30, counts the number of decoding successes for a predetermined time period and outputs the counted number (decoding success rate DR) to a control unit 150. The control unit 150 uses as a basis the decoding success rate DR communicated from the decode unit 140 to control the set value of reference voltage Vth used in the comparator 130.

Abstract: In various embodiments, a reference voltage (Vref) generator for a single-ended receiver in a communication system is disclosed. The Vref generator in one example comprises a cascoded current source for providing a current, I, to a resistor, Rb, to produce the Vref voltage (I*Rb). Because the current source isolates Vref from a first of two power supplies, Vref will vary only with the second power supply coupled to Rb. As such, the Vref generator is useful in systems employing signaling referenced to that second supply but having decoupled first supplies. For example, in a communication system in which the second supply (e.g., Vssq) is common to both devices, but the first supply (Vddq) is not, the disclosed Vref generator produces a value for Vref that tracks Vssq but not the first supply.

Abstract: Methods for detecting and/or indicating the presence of valid data and threshold setting and data detection circuitry are disclosed. The threshold setting and data detection circuitry and related methods may be useful for fast and accurate reception of optical signals. The detection circuit generally comprises (i) a first circuit configured to regulate or control a DC offset of a differential input signal, and (ii) a second circuit coupled to the first circuit, the second circuit configured to indicate the presence of a data signal at the differential input signal when a voltage difference between true and complementary nodes of the differential input signal is above a predetermined threshold.

Abstract: A system and method are provided for tuning a serial link. The method includes receiving, by a receiver circuit, an offset correction pattern transmitted over a serial link and sampling the received offset correction pattern based on an offset correction parameter to generate a sampled signal. A distribution of the sampled signal is computed and the offset correction parameter is set based on the distribution. The system includes a receiver circuit that is coupled to the serial link and an offset correction unit that is coupled to the receiver circuit. The receiver circuit is configured to receive the offset correction pattern and sample the received offset correction pattern based on the offset correction parameter to generate the sampled signal. The offset correction unit is configured to compute the distribution of the sampled signal and set the offset correction parameter based on the distribution.

Abstract: A method for estimating an unwanted component that a receiver introduces into a signal at a known frequency, the method comprising applying a frequency offset to a signal, which comprises a wanted component at the known frequency, to form an offset signal having a frequency spectrum in which the wanted component is not positioned at the known frequency, processing the offset signal in the receiver and estimating a component positioned at the known frequency in the frequency spectrum of the processed signal.

Abstract: An apparatus for demodulating an Amplitude Shift Keying (ASK) encoded signal is provided. The apparatus comprises a peak detector, a first comparator, a threshold generator, a delay circuit, and a second comparator. The peak detector is configured to detect a peak voltage, and the first comparator is coupled to the peak detector and receives a first threshold voltage. The threshold generator is coupled to the peak detector and is configured to generate a second threshold voltage that is proportional to peak voltage. The delay circuit is coupled to the first comparator, and the second comparator is coupled to the delay circuit and that is coupled to the threshold generator so as to receive the second threshold voltage.

Abstract: A method includes receiving a symbol modulated with multiple bits according to a signal constellation including multiple constellation points. A soft metric is computed for a given bit in the symbol: A first constellation point closest to the received symbol according to a distance measure is found. A row or column of the constellation points, which is closest to the first constellation point according to the distance measure, and over which a value of the given bit is constant and is opposite to the value of the given bit in the first constellation point, is identified. At least the identified row or column is searched for a second constellation point that is closest to the received symbol according to the distance measure. The soft metric is calculated based on the first and second constellation points. The value of the given bit is reconstructed based on the soft metric.

Abstract: Provided are a receiving apparatus and method for a wireless communication system using multiple antennas. A receiving method for a wireless communication system using multiple paths, the receiving method comprising: receiving signals through a predetermined number of multiple paths; sensing a carrier according to saturation state degrees of the signals, and providing saturation state information; calculating automatic gain components of the received signals by using the received signals and the saturation state information of the received signals; and performing a noise matching process to amplify noises on the predetermined multiple paths according to the automatic gain components during a predetermined period.

Abstract: A mixer included in a receiver of a wireless communication system is provided. The mixer includes a switching unit including a plurality of transistors receiving a Radio Frequency (RF) signal and a Local Oscillation (LO) signal, and outputting a baseband signal, and a voltage controller outputting a voltage control signal controlling a body voltage of at least one transistor from among the plurality of transistors to thereby control a threshold voltage of the at least one transistor.

Abstract: In one embodiment, a method of communicating data values over a three conductor interface is provided. Different data values are transmitted by generating and transmitting three respective signals to a receiver using three conductors. The first signal is maintained as a set voltage level. The second signal is alternated between a high voltage and a low voltage according to a carrier frequency. The third signal is alternated between the high and low voltages and is out of phased with the second signal. To transmit a first data value, the first signal is generated on a first conductor, the second signal is generated on a second conductor, and the third signal is generated on a third conductor. To transmit a second data value, the second signal is generated on the first conductor, the first signal is generated on the second conductor, and the third signal is generated on the third conductor.

Abstract: The present invention discloses a signal transmission device performing compensation by filtering characteristics for generating a transmission signal according to a pulse amplitude modulation signal. The signal transmission device comprises: a filtering characteristic compensation circuit for generating a compensation signal according to the pulse amplitude modulation signal and a filtering function; a filter coupled to the filtering characteristic compensation circuit for generating a filtered signal through filtering the compensation signal according to the aforementioned filtering function; and an analog front-end circuit for generating the transmission signal according to the filtered signal.

Abstract: A wireless communication device is disclosed that is capable of reduced power consumption. The device includes several analog components, including some that may be capable of operating at multiple different operation powers and others whose function may be performed by an equivalent digital component. Based on a quality of a received signal, the wireless communication device can adjust a power consumption configuration of its analog components in order to optimize power use. For example, when signal quality is higher than necessary, the device can sacrifice performance to reduce operating power and/or switch to digital equivalent components. Similarly, when signal quality is lower than necessary, the device can enhance performance by increasing operating power and/or switching from digital equivalent components to corresponding analog components.

Abstract: A circuit and a method are used estimate quality of the output of a wireless receiver. This quality measure is used to control the supply voltage and thereby provide power savings.

Abstract: A wireless receiver for receiving a signal with a characteristic pattern includes a predictor for predicting the presence of a non-zero value of the characteristic pattern. A tracker tracks a noise component in the received signal between predicted non-zero values. The resulting noise component is subtracted from the received signal to output a processed signal, which is then decoded by a pattern discriminator and demodulator. The wireless receiver is less sensitive to noise and interference.

Abstract: In accordance with some embodiments, receivers for receiving a wireless data transmission are provided, the receivers comprising at least one amplifier that receives an RF input signal and produces at least one amplified signal; a mixer that mixes the at least one signal to produce a mixed signal; a filter that filters the mixed signal to produce a filtered signal, a comparator that compares the filtered signal to a threshold voltage and produces a digital signal, a first pulse generate i that generates a first pulse in response to a transition in the digital signal, a second pulse generator that generates a second pulse that is longer than the first pulse in response to a transition in the digital signal; and digital logic that generates a clock output and that generates a data output based on a state of the first pulse when the second pulse expires.

Abstract: A wireless communications device may include a portable housing and a temperature-compensated clock circuit carried by the portable housing. The device may further include a wireless receiver carried by the portable housing for receiving timing signals, when available, from a wireless network, and a satellite positioning clock circuit carried by the portable housing. A clock correction circuit may be carried by the portable housing for correcting the temperature-compensated clock circuit based upon timing signals from the wireless network when available, and storing historical correction values for corresponding temperatures. The clock correction circuit may also correct the temperature-compensated clock circuit based upon the stored historical correction values when timing signals are unavailable from the wireless network, and correct the satellite positioning clock based upon the temperature-compensated clock circuit.

Abstract: A mechanism is provided for dynamically adjusting DC offset at the time of deviation from DC balance ½ (DC level) in a data pattern including long-period consecutive bits generating DC offset in a section of data. A receiver circuit unit of an LSI having a serializer/deserializer arrangement for performing high-speed serial transmission includes an offset adjusting circuit. The offset adjusting circuit calculates DC balance in an arbitrary section of data by averaging received serial data. Based on comparison between a DC level and the DC balance obtained by averaging the received data, offset is shifted toward the H side when the DC balance exists on the H side from the DC level, and shifted toward the L side when the DC balance exists on the L side.

Abstract: An embodiment of the invention provides an electronic device. The electronic device includes a digital-to-analog converter (DAC), a transmitter front-end (TX FE), an amplifier, an analog-to-digital converter (ADC), and a swap circuitry. The TX FE has a first and a second input end coupled to a first and a second output end of the DAC, respectively. The ADC has a first and a second input end coupled to a first and a second output end of the amplifier, respectively. The swap circuitry is configured to couple the first and second output ends of the DAC to a first and a second input end of the amplifier in a normal state, respectively, and couple the first and second output ends of the DAC to the second and first input ends of the amplifier in a swapped state, respectively.

Abstract: An improved reference voltage (Vref) generator for a single-ended receiver in a communication system is disclosed. The Vref generator in one example comprises a cascoded current source for providing a current, I, to a resistor, Rb, to produce the Vref voltage (I*Rb). Because the current source isolates Vref from a first of two power supplies, Vref will vary only with the second power supply coupled to Rb. As such, the improved Vref generator is useful in systems employing signaling referenced to that second supply but having decoupled first supplies. For example, in a communication system in which the second supply (E.g. Vssq) is common to both devices, but the first supply (Vddq) is not, the disclosed Vref generator produces a value for Vref that tracks Vssq but not the first supply. This improves the sensing of Vssq-referenced signals in such a system.

Abstract: A receiver circuit includes a first slicer coupled to receive data signals from a signal path and a reference voltage from a reference voltage path that is separate from the signal path. The first slicer is configured output a logic value based on a comparison between a voltage of the data signal and the reference voltage. The receiver circuit further includes a reference voltage generator configured to generate the reference voltage. The reference voltage generator is configured to dynamically generate the reference voltage based on logic values of previously received signals during operation in a first mode. During operation in a second mode, the reference voltage generator is configured to generate and provide the reference voltage as a static voltage.

Abstract: A broadcast receiving apparatus receives digital broadcast and analog broadcast including same broadcast contents simultaneously, and outputs the analog broadcast while the reception state of the digital broadcast worsens, thereby reduces uncomfortable auditory sensations caused by output switching from one type of broadcast to another type of broadcast. The broadcast receiving apparatus is configured to perform control to bring the acoustic characteristic of pre-switching broadcast closer to the acoustic characteristic of post-switching broadcast based on received field strength of analog broadcast signals when the output is switched from one broadcast to another broadcast.

Abstract: Methods and apparatus for power measurement in a communication system. In an aspect, a method is provided for power measurement. The method includes selecting between a signal decoding mode and a power measurement mode, decoding an input signal if the signal decoding mode is selected, and calculating a power measurement associated with the input signal if the power measurement mode is selected. In another aspect, an apparatus is provided for power measurement. The apparatus includes means for selecting between an active mode and a power measurement mode, means for decoding an input signal if the active mode is selected, and means for calculating a power measurement associated with the input signal if the power measurement mode is selected.

Abstract: A communication system comprises a direct conversion receiver for correcting imbalance errors. The direct conversion receiver receives a radio frequency (RF) signal and converts the RF signal to baseband signals. The direct conversion receiver further translates the baseband signals to digital signals having a direct current (DC) offset and applies a DC offset correction to the digital signals having the DC offset to generate first DC offset corrected signals. An imbalance correction unit of the direct conversion receiver applies an imbalance correction to the first DC offset corrected signals by estimating an error between an average envelope of the first DC offset corrected signals and an average envelope of second DC offset corrected signals. The imbalance correction unit is fixed at initial imbalance parameter values. The direct conversion receiver further updates the initial imbalance parameter values of the imbalance correction unit based on the estimated error for correcting imbalance errors.

Abstract: Methods and apparatuses for calculating the location of an optimal sampling point for a receiver system are disclosed. In brief, a first method comprises determining a maximum voltage margin and a maximum timing margin of a received signal, and from these margins, determining an optimal sampling point, which includes a reference voltage level (Vref) and a relative sample phase. The location of the optimal sampling point is based on the locations of the sampling point of the maximum voltage margin and the sampling point of the maximum timing margin. A second method comprises establishing an initial sampling point, and then successively refining each of the voltage and timing components of the sampling point until an optimal sampling point is reached.

Abstract: Certain aspects of the present disclosure relate to a method for emulating N-bits uniform quantization of a received pulse signal by using one-bit signal measurements. One method for wireless communications includes receiving a signal transmitted over a wireless channel, wherein the signal comprises a sequence of pulses, applying gain values to the pulses to obtain a binary matrix for each gain value, generating a probability vector for each gain value using the binary matrix obtained for that gain value, and generating an output signal by linearly combining the probability vectors.

Abstract: Unfolded adaptive/decision-directed loops and correction circuits therefor, architectures, apparatuses and systems including the same, and methods, algorithms and software for reducing latency in an adaptive and/or decision-directed loop. Disclosed embodiments advantageously reduce effects of loop latency, improve the accuracy of corrections in an adaptive loop, and minimize overhead and delays associated with such improvements.

Abstract: In various embodiments, a reference voltage (Vref) generator for a single-ended receiver in a communication system is disclosed. The Vref generator in one example comprises a cascoded current source for providing a current, I, to a resistor, Rb, to produce the Vref voltage (I*Rb). Because the current source isolates Vref from a first of two power supplies, Vref will vary only with the second power supply coupled to Rb. As such, the Vref generator is useful in systems employing signaling referenced to that second supply but having decoupled first supplies. For example, in a communication system in which the second supply (e.g., Vssq) is common to both devices, but the first supply (Vddq) is not, the disclosed Vref generator produces a value for Vref that tracks Vssq but not the first supply.

Abstract: A wireless communication threshold for an implantable medical device is automatically adapted in an attempt to maintain optimum signal detection sensitivity. In some aspects, a threshold level may be adapted to account for current environmental conditions, implant conditions, device conditions, or other conditions that may affect the reception of wireless signals at the device. In some aspects, the determination of an optimum level for the threshold involves a tradeoff relating to effectively detecting target signals while avoiding detection of noise and/or interference. In some aspects, adaptation of a threshold may be based on maximum energy levels associated with one or more sets of RF energy sample data. In some aspects, adaptation of a threshold may be based on the number of false wakeups that occur during a period of time.

Abstract: A receiver circuit includes a first slicer coupled to receive data signals from a signal path and a reference voltage from a reference voltage path that is separate from the signal path. The first slicer is configured output a logic value based on a comparison between a voltage of the data signal and the reference voltage. The receiver circuit further includes a reference voltage generator configured to generate the reference voltage. The reference voltage generator is configured to dynamically generate the reference voltage based on logic values of previously received signals during operation in a first mode. During operation in a second mode, the reference voltage generator is configured to generate and provide the reference voltage as a static voltage.

Abstract: As single-ended signaling is implemented in higher-speed communications, accurate and consistent reading of the data signal becomes increasingly challenging. In particular, single-ended links can be limited by insufficient timing margins for sampling a received input signal. A single ended receiver provides for improved timing margins by adjusting a reference voltage used to sample the input signal. A calibration pattern is provided to the receiver as the input signal, and the reference voltage is adjusted toward a median value of the signal. As a result, the receiver provides for reading received single-ended data in a manner enabling accurate data transfer at higher speeds.

Abstract: A pulse response for a receiver, as an array PR, is found from the receiver's symbol stream. For a continuous stream of arbitrary data, a value of the array PR[k] can be determined from the signal levels of the symbols received. The stream of received data is input to a FIFO. Between the first and last locations of the FIFO is the symbol referred to herein as Dn. Symbols located in the FIFO before Dn are referred to as Dn?x. Symbols located in the FIFO after Dn are referred to as Dn+x. Dn differs from the other FIFO symbols in that its signal level can be measured with an adjustable error slicer. The ISI effect of any Dn?k upon Dn can be measured, and thus any PR[k] measured, by measuring the average signal level of Dn when only certain types of data streams occur in the FIFO.

Abstract: One embodiment relates to a receiver circuit for multi-level amplitude signaling which includes at least three amplitude levels for each symbol period. The receiver circuit includes a peak detector, a reference voltage generator, and a comparator circuit. The peak detector is arranged to detect a peak voltage of the multi-level amplitude signal, and the reference voltage generator uses the peak voltage to generate multiple reference voltages. The comparator circuit uses the multiple reference voltages to detect an amplitude level of the multi-level amplitude signal. Other embodiments and features are also disclosed.

Abstract: A method of transmitting speech data to a remote device in a distributed speech recognition system, includes the steps of: dividing an input speech signal into frames; calculating, for each frame, a voice activity value representative of the presence of speech activity in the frame; grouping the frames into multiframes, each multiframe including a predetermined number of frames; calculating, for each multiframe, a voice activity marker representative of the number of frames in the multiframe representing speech activity; and selectively transmitting, on the basis of the voice activity marker associated with each multiframe, the multiframes to the remote device.