Abstract: A serial communication system includes a receiver that incorporates an amplitude monitor, which may be used to set and maintain appropriate termination-resistance values and transmit pre-emphasis and receive equalization settings. The amplitude monitor can note the presence or absence of input signals, as is required by some communication standards, such as those that require support for “out-of-band” (OOB) signaling for e.g. rate negotiation. The amplitude monitor compares the input signal with a reference level in response to a sample clock. The sample clock is periodically phase shifted with respect to the incoming data so the amplitude monitor is sure to sample an incoming data eye at or near the peak amplitude over a selected sample period. The amplitude detector notes the detection of an input signal if the input signal surpasses the reference level for any sample phase.

Abstract: An adaptive slicer threshold is derived from averages of maximum and minimum values of the received signal, the method comprising the steps of: —averaging (86) several detected maximum values and averaging several detected minimum values, and —calculating (86) the slicer threshold from these average minimum and maximum values.

Abstract: Various systems and methods are provided for adaptive equalization. The adaptive equalization is performed on a data signal received from a channel in a receiver. The data signal is equalized using an equalizer in the receiver, thereby generating an equalized data signal. During equalization, an equalization setting of the equalizer is adapted based upon an overshoot of the equalized data signal at a data transition.

Abstract: A test signal is generated and supplied to a signal processing circuit for making frequency conversion. A signal outputted from the signal processing circuit is detected to generate a detected signal including a detected positive signal corresponding to the positive signal of the test signal and a detected negative signal corresponding to the negative signal. And the level of the detected positive signal and the level of the detected negative signal are compared to output the comparison result indicating which level is higher. Further, an offset correction signal for making a level difference between the detected positive signal and the detected negative signal within a preset permissible range is generated, based on the comparison result, and offset correction of the test signal or modulated signal supplied from the outside is made in accordance with the offset correction signal.

Abstract: Methods and apparatuses for calculating the location of an optimal sampling point for a receiver system are disclosed. In brief, a first method comprises determining a maximum voltage margin and a maximum timing margin of a received signal, and from these margins, determining an optimal sampling point, which includes a reference voltage level (Vref) and a relative sample phase. The location of the optimal sampling point is based on the locations of the sampling point of the maximum voltage margin and the sampling point of the maximum timing margin. A second method comprises establishing an initial sampling point, and then successively refining each of the voltage and timing components of the sampling point until an optimal sampling point is reached.

Abstract: The invention relates to a method for adjusting a pulse detection threshold consisting in detecting a pulse when the edge of said pulse envelop crosses the threshold, in allocating (A) a staring value (TH0) to the threshold and in adjusting (B1) the threshold (TH) in such a way that the number of pulses detected on at least one observation window (OWj) satisfies a predetermined criterion in a determined time.

Abstract: A receiver has a first input port and a second input port both coupled to a differential amplifier through first and second input capacitors. A bias circuit coupled to the core side of the first input capacitor and to the core side of the second input capacitor is configured to provide a selected voltage to at least one of the first input and the second input of the differential amplifier. In one embodiment, a common mode bias circuit provides a common mode voltage to both inputs of a differential amplifier. In a particular embodiment, a run length detector monitors the output of the differential amplifier and provides a run length feedback signal or an average bit density feedback signal to the set the selected voltage between periods of data reception.

Abstract: A communication system comprises a twisted pair communication link operably coupled to at least two driver stages for providing at least two independent input signals on the twisted pair communication link. The at least two independent input signals on the twisted pair communication link are summed and input to a comparator arranged to compare the summed signal to a reference value. The output of the comparator is input to the at least two driver stages. The outputs from the at least two driver stages are summed and fed back and summed with one or more of the independent input signals. In this manner, adverse effects due to non-ideal symmetry between components in a twisted pair communication link, such as a Controller Area Network system, are reduced.

Abstract: The object of the present invention is to provide a waveform shaping device and an error measurement device which can perform a waveform shaping operation with the sufficient amplitude margin, even if the mark ratio of the inputted data signal is significantly varied and the amplitude of the inputted data signal is decreased.

Abstract: A communication apparatus using a chaotic signal and a method thereof are provided. The communication apparatus includes a correlator which multiplies source data by one of an optical orthogonal code (OOC) and a prime sequence code (PSC), and outputs transmission data, a transmission signal generating unit which generates a chaotic transmission signal by masking the transmission data with respect to a chaotic signal, and an antenna which transmits the chaotic transmission signal. As a result, multiple accesses are enabled, and a wireless communication system for short-distance operation, which is economic and low power-consuming, is provided.

Abstract: A signal processing device includes: a first correlator that sequentially multiplies a first receive signal including a pattern in a receive signal and a first reference pattern signal including a complex conjugate of a first partial signal of the first receive signal at a sampling timing to generate a first correlation voltage; a second correlator that sequentially multiplies the first receive signal and a second reference pattern signal including a complex conjugate of a second partial signal, which is behind the first partial signal, at a sampling timing to generate a second correlation voltage; and a phase difference generation circuit that generates a first phase difference between the first partial signal and the second partial signal based on a first correlation peak voltage obtained when the first correlation voltage has a peak value and a second correlation peak voltage obtained when the second correlation voltage has a peak value.

Abstract: Methods and apparatuses for calculating the location of an optimal sampling point for a receiver system are disclosed. In brief, a first method comprises determining a maximum voltage margin and a maximum timing margin of a received signal, and from these margins, determining an optimal sampling point, which includes a reference voltage level (Vref) and a relative sample phase. The location of the optimal sampling point is based on the locations of the sampling point of the maximum voltage margin and the sampling point of the maximum timing margin. A second method comprises establishing an initial sampling point, and then successively refining each of the voltage and timing components of the sampling point until an optimal sampling point is reached.

Abstract: A system and method for receiving radio frequency signals, comprising a plurality of analog signal couplers, for communicating a representation of a radio frequency signal; a respective analog to digital converter for each of said couplers, each having an output presenting a digital representation of the representation and an associated clock; a non-blocking switch matrix, receiving the plurality of outputs and associated clocks, and producing a plurality of regenerated outputs and associated regenerated clocks under selective control of a switch matrix signal; and a plurality of digital radio frequency signal processors, adapted to receive at least one regenerated output from the non-blocking switch matrix and associated regenerated clock.

Abstract: The radio base station of the present invention detects desired sampling points, which are sampling points having reception levels higher than or equivalent to a predetermined threshold, to calculate a ratio of the desired sampling points to the entirety of sampling points contained in a desired bandwidth, the total number of sampling points being equivalent to the number of carriers in one cycle of the frequency band of the reception signal. Further, so as to calculate a gain to be applied in the amplification of signal level to a predetermined target level, the radio station uses as a gain a value obtained by dividing the target level by a product, the product being obtained by performing multiplication of an average value of levels of the signal components within the desired frequency band and an reciprocal of the ratio calculated.

Abstract: A method and apparatus for adjusting a symbol decision threshold at a receiver in a communication network enables the receiver to be adapted to more correctly receive symbols as transmitted by a transmitter. In one embodiment, a received bit imbalance is detected by a receiver prior to error correction and after error correction to determine whether an error component of the received signal contains larger numbers of ones or larger numbers of zeros. Where the transmitter scrambles the signal prior to transmission, the receiver will also scramble the signal after error correction and prior to counting the number of zeros or ones. Any imbalance between the number of transmitted and received ones or zeros is used as feedback to adjust threshold values used by detectors to fine tune the manner in which the receiver interprets incoming signals.

Abstract: Disclosed herein is a sensor system having a sensor and at least one communication line operable with the sensor. The transmission medium is configured to convey data transmitted by the sensor to a remote location. The sensor transmits data on the communication line a plurality of times by at least two methods of transmission or modulation. Further disclosed herein is a method based on the foregoing. Further disclosed is a method of communicating by modifying a voltage amplitude of a signal and receiving the communication signal by employing a variable threshold detection circuit in the downhole device. Further disclosed is a system for communicating data between a downhole device and a remote location including a remote device for generating a communication signal, the remote device configured to modify a voltage amplitude of said communication signal.

Abstract: A method and arrangement for estimating a DC offset for a signal received in a radio receiver. The received signal includes a digitally modulated signal component, a DC offset component, and a noise component. When the signal is of a known type, such as a Gaussian Minimum Shift Keying (GMSK)-modulated signal with constant amplitude in a GSM/EDGE cellular radio system, the method exploits the known characteristics of the statistical distribution for the known type of signal to obtain a better estimate of the DC offset. The statistical distribution of the received digitally modulated signal component is first analyzed. That statistical distribution is then compared to the known statistical distribution for the known type of signal to identify differences. The differences are then used to estimate the DC offset. Additional iterations may be performed to further improve the DC estimate.

Abstract: Disclosed herein are systems and methods for detecting a signal to provide a detected data sequence, comprising providing a plurality of candidate data sequences, computing baseline wander estimates associated with respective ones of the candidate data sequences, comparing a signal to each of the respective ones of the candidate data sequences, wherein the comparisons are compensated by corresponding ones of the baseline wander estimates, and choosing, based on the comparisons, one of the plurality of candidate data sequences to be the detected data sequence.

Abstract: A driver circuit is coupled to an optical waveguide transmitter. The driver circuit has a current generator that is in series with the transmitter, and a current robbing circuit is coupled to the transmitter. The current robbing circuit is to divert first and second amounts of current from the transmitter, in accordance with predetermined values of first and second bit streams, respectively, in which data is received to be transmitted. Other embodiments are also described and claimed.

Abstract: In a receiver, an AC-coupling solution uses a fully integrated circuit for simultaneously providing both baseline wander compensation and common-mode voltage generation. Usefully, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high resistive impedance element is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the received data voltage level. The voltage correction circuit is controlled by the feedback of data detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation.

Abstract: A semiconductor device comprising receiver circuitry arranged to receive a dual carrier RF signal comprising a first wanted component and a second wanted component. The receiver circuitry is arranged to down convert the received dual carrier RF signal to create a Very Low Intermediate Frequency, VLIF signal whereby the first wanted component of the received dual carrier signal is subsequently located at a positive VLIF offset with respect to DC, zero hertz, and the second wanted component of the received dual carrier signal is subsequently located at a negative VLIF offset with respect to DC. The semiconductor device further comprises a signal processing logic module arranged to receive the VLIF signal and to separate the first and second wanted components of the received signal.

Abstract: A variable bandwidth receiver uses allocated bandwidth more efficiently and ensures that blocking signals do not overload receiver components. The receiver includes multiple branches for receiving a first bandwidth signal. Each receiver branch has a filter for passing signals in a frequency band corresponding to a second bandwidth less that the first bandwidth and an analog-to-digital converter for converting the baseband signal into a digital signal. A controller digitally combines the digital signals from two or more of the receiver branches to produce a received signal having a bandwidth substantially wider than the first bandwidth. Because combining is done after analog-to-digital conversion in the digital domain, the controller can combine the digital signals from two or more of the receiver branches having adjacent corresponding frequency bands without the normal guard band separating them.

Abstract: In an FSK receiver according to the present invention, a correction operation for a DC offset component is performed based on a maximum value and a minimum value of a demodulation signal. If a difference between the maximum and minimum values is less than a predetermined threshold value TH1, the correction operation is halted. Thus, the FSK receiver can rapidly perform an appropriate offset removal from a multi-level FSK signal.

Abstract: A method and system using the principle of generalized maximum likelihood estimation to resolve sample timing uncertainties that are associated with the decoding of communication signals. By using generalized maximum likelihood estimation, sample timing uncertainty can be resolved by taking multiple samples of the received signal within a symbol period and determining which sample best corresponds to the optimal sample timing. The sample which best corresponds to the optimal sample timing can be determined from a timing index which can be calculated from ambiguity indicators that are based on the samples of the received signal.

Abstract: A hybrid structure circuit for the cancellation of both Type-I and Type-II DC offsets. It comprises a static compensator in conjunction with a servo-loop feedback amplifier to suppress the undesired DC components present along the path of the base band after the direct conversion mixer. Two mixers are used to down convert a received RF signal directly to a base band signal with two components: in-phase and quadrature-phase. Both in-phase and quadrature-phase branches employ the same circuitry for DC offset cancellation. Miller effect is also utilized in the structure in order to implement the circuit on-chip.

Abstract: A receiver includes: a first amplifier for amplifying an input signal and outputting an output signal; a clock generator for generating a clock signal corresponding to a period of the output signal; a judger for outputting a first logical value or a second logical value in accordance with a phase lead or phase lag which has been occurred at a crossing point of the positive-phase signal and the negative-phase signal of the output signal upon rising or falling the clock signal; a detector for outputting a difference value between a time for which the judgment signal has the first logical value and a time for which the judgment signal has the second logical value; and an adjustor for adjusting reference voltages of a positive-phase signal and a negative-phase signal of the input signal in accordance with the difference value output from the detector.

Abstract: A tail estimate signal which includes noise associated with baseline wander is generated. The tail estimate signal is generated by processing an input signal using a detector to obtain one or more decisions. Using the one or more decisions, the tail estimate signal is generated. The tail estimate signal is removed from the input signal.

Abstract: An upconverter includes a switching architecture configured to receive an input signal, a first local oscillator (LO) signal, and a second local oscillator (2LO) signal that is at a frequency that is twice a frequency of the local oscillator (LO) signal, wherein the switching architecture is configured to switch the input signal on transitions of the second local oscillator (2LO) signal, and wherein the first local oscillator signal and the second local oscillator signal are combined to form combined LO 2LO switching signals.

Abstract: A radio-controlled timepiece that receives a standard time signal containing a time code and adjusts the time based on the received standard time signal includes: a reception unit that receives the standard time signal; an analog/digital conversion unit that digitizes the received standard time signal based on a prescribed threshold value; a time counter that keeps time; a time code generator that generates a reference time code based on the time counted by the time counter; a duty evaluation unit that calculates the pulse duty cycle of the digital signal output from the A/D conversion unit, and determines if the received pulse duty cycle that is calculated matches the duty cycle of the reference time code generated by the time code generator; a level changing unit that changes the relative level of the threshold value to the reception signal if the duty evaluation unit determines that the received pulse duty cycle does not match the duty cycle of the reference time code; and a time code decoder that decodes

Abstract: A power amplifier includes a power amplifier core in which a transmit signal having an amplitude-modulated (AM) component and a phase-modulated (PM) component is passed and amplified, the power amplifier comprising a forward path, and an additional amplification device configured to generate an output that is proportional to an output of the power amplifier core, such that the output of the additional amplification device indirectly controls the output of the power amplifier core.

Abstract: A receiver assembly for use in an optical telecommunications network is provided that automatically generates a reference level for the incoming signal burst based on its preamble without the need to pre-process the entire signal burst. The entire signal burst is fed directly from the TIA into the input of the limiting amplifier. A differential amplifier, tapped from the data and data bar outputs of the limiting amplifier, samples the signal stream to capture the preamble portion of each signal burst. The preamble portion of the signal burst is then passed, post amplification, into a sample and hold circuit. The sample and hold circuit samples the amplitude of this preamble portion of the signal and then holds the sampled level for use as a reference level for the processing of following payload signal.

Abstract: An apparatus comprising an analog filter, an analog to digital converter coupled to said analog filter; and a digital filter coupled to said analog to digital converter; wherein the apparatus is configured such that distortion introduced into a filtered signal by said analog filter is substantially compensated by said digital filter.

Abstract: A null detector and its corresponding method are provided. The null detector includes a power detector, a smoother, and an overlapper. The power detector outputs a power level signal according to the power level of a received signal. The smoother is coupled to the power detector for determining according to the power level signal whether the received signal is transmitting a null symbol, and then the smoother outputs a null detection signal at a first state value or a second state value indicating the result of the determination. The overlapper is coupled to the smoother for providing the duration and position of the null symbols transmitted by the received signal according to the null detection signal.

Abstract: A method and system of establishing an offset for a receiver. In one embodiment, a method includes receiving an input signal and generating a first signal. The method can further include integrating the input signal and the first signal at a reference node. In addition, the method can include comparing the input signal to a signal at the reference node and generating an output signal, analyzing the output signal to determine whether the output signal contains noise, and modifying the first signal based on the analysis of the output signal.

Abstract: A signal processing apparatus has a plurality of baseline wander correcting units, provided in a processing path in which a predetermined processing is performed on an input signal. At least one of the plurality of baseline wander correcting units includes a correction permission control unit that controls permission or rejection of correction, and baseline wander in the input signal is corrected sequentially by each of the plurality of baseline wander correcting units, based on a control of the correction permission control unit. The baseline wander correcting unit corrects the baseline wander by determining whether or not the baseline correction is to be effected or not, so that the wander of baseline can be efficiently corrected.

Abstract: A multibit quantizer is provided, at its input terminals, with a variable gain circuit and an offset addition circuit to perform tracking control in which for each sampling time, the level of an offset signal of the offset addition circuit is adjusted based on output digital data of an output processing circuit and the preceding control signal of an offset control circuit so that the quantizer operates without causing a saturation operation. As a result, the output digital data, in which the number of bits is greater than the number of bits of the quantizer by the offset value controlled by the offset addition circuit, is outputted from the output processing circuit for each sampling time.

Abstract: Baseline wander is removed. A first decision signal is generated from an input signal using a first detector. Baseline wander associated with the input signal is estimated using the first decision signal. The estimated baseline wander is removed from the input signal. A second decision signal is generated from the input signal with the baseline wander removed using a second detector.

Abstract: A power consumption control method applied to a communication system adjusts the power consumption of a portion of circuit in the communication system according to a transmission distance between the communication system and another communication system. Another power consumption control method applied to a communication system adjusts the power consumption of a portion of circuit in the communication system according to a signal index of the communication system.

Abstract: A wireless communication device may include a receiver coupled to a modem. The receiver may receive a wireless packet according to a wireless networking protocol such as a protocol in the IEEE 802.11 family of wireless protocols. Upon receiving a packet, the receiver may processes the packet according to a selected one of a plurality of discrete gain states. The modem coupled to the receiver may select the gain state used to process the packet such as by sending one or more signals to the receiver to reduce the gain state after determining that the current gain state is too large. The modem may implement a plurality of power detection modules in order to detect signals at varying power levels. The implementation of a plurality of power detectors may allow the gain state selection process to be performed very quickly as required by some wireless networking protocols.

Abstract: A receiver includes: an amplifier that amplifies a received broadband signal up to a predetermined level; a first switch that switches an output signal from the amplifier; a signal generator that generates a signal for controlling a switching operation of the first switch; an integration capacitor that integrates an output signal from the first switch; a comparator that compares an output voltage from the integration capacitor with a predetermined voltage; and a reset circuit that discharges electrical charges accumulated in the integration capacitor based on a comparison result from the comparator.

Abstract: In an embodiment, set forth by way of example and not limitation, a data slicer includes a signal input node, a comparator having a first input of a first polarity, a second input of a second polarity which is the opposite of the first polarity, and an output coupled to a data out node, the first input of the comparator being coupled to the signal input node, and a multi-mode threshold generator including a first threshold generator and second threshold generator, whereby the first threshold generator is selected firstly and the second threshold generator is selected secondly.

Abstract: A receiver includes a memory for storing DC offset amounts generated by an analog circuit; an amplifier; a DC offset amount generator for generating a first offset value and a second offset value to be removed from the received signal amplified at the amplifier; a first DC offset component-removing unit for removing the first DC offset value from the received signal before the amplifier; a second DC offset component-removing unit for removing the second DC offset value from the received signal after the amplifier; and an updating unit for updating the DC offset amount stored in the memory in view of the second DC offset value generated by the DC offset amount generator. A maximum value of the second DC offset value is set larger than a multiplication value of a gain of the amplifier by a minimum resolution value of the first DC offset value.

Abstract: A signal processing apparatus sets a discrimination level most suitably, regardless of whether the apparatus is in the minimum receiving system or the maximum receiving system. The apparatus comprises a light receiving unit converting input signal light to an electric signal, and a level detecting unit for detecting a high level component and a low level component of the electric signal from the light receiving unit, along with peak levels on a high-side and a low-side of the electric signal.

Abstract: An adaptive algorithm is implemented that optimizes the slicer threshold by optimizing the tail distribution of a “+1” and “?1” histogram. Through the use of a low resolution and under-sampled ADC, a histogram of received bit may be created. The difference between the y-intersects of lines derived from the “+1” and “?1” histogram is used to determine an error function. The algorithm iteratively updates the threshold value based on this error function.

Abstract: Methods and systems for detecting defects in serial link transceivers. Defect detection includes detecting open circuits in one or more of the transmission lines, detecting short circuits between one or more of the transmission lines and a power supply, detecting short circuits between the transmission lines, or detecting short circuits across optional AC-couplings in the transmission lines. The detection can include direct or indirect detection of voltage or current.

Abstract: Techniques for performing automatic gain control (AGC) at a receiver are described. The receiver may receive an OFDM-based symbol composed of a cyclic prefix and a useful portion. The receiver may scale the OFDM-based symbol with an initial receiver gain, adjust the initial receiver gain based on the cyclic prefix, apply the adjusted receiver gain prior to the useful portion, and process the useful portion to recover at least one signal sent by at least one transmitter. The receiver may select the initial receiver gain, e.g., based on a predicted received power level for the at least one transmitter, a pattern of different receiver gains, etc. The receiver may apply the initial receiver gain at the start of the OFDM-based symbol. The receiver may measure the power of a set of samples in the cyclic prefix and may adjust the receiver gain based on the measured power and a target power.

Abstract: A receiver includes a memory for storing DC offset amounts in accordance with a DC offset component remaining in a received signal; a first DC offset component-removing unit configured so as to generate a first DC offset amount from the DC offset amounts stored in the memory and to remove the first DC offset amount from the received signal; an amplifier for amplifying a signal output from the first DC offset component-removing unit; and a second DC offset component-removing unit configured so as to generate a second DC offset amount from the DC offset amounts stored in the memory in view of a gain of the amplifier and remove the second DC offset amount from the signal amplified by the amplifier.

Abstract: A circuit and a method for baseline wandering compensation for solving the problem of baseline wandering in receivers of a communication system are provided. Two paths of baseline wandering compensation are provided on the basis of a slicer error. One of the paths adjusts a direct current (DC) bias of an input signal, and the other path adjusts the determining levels of the slicer, and thus, the present invention avoids input saturation of an analog-to-digital converter, enhances the signal-to-noise ratio, and achieves a precise baseline wandering compensation.

Abstract: A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

Abstract: The transmission control unit of the device transmits sample data while changing the setting of output amplitude and emphasis of the transmitter within a prescribed range. The transmission processing unit of the device generates an eye diagram from the sample data received by the receiver, detects receivable phase-range data from the eye diagram, and transmits the same. The optimization processing unit of the device writes the phase-range data transmitted from the device into the table in correspondence to the output amplitude and emphasis of which the setting has been changed, determines optimum values of output amplitude and emphasis from the table obtained upon the completion of setting change within the prescribed range, and sets the same in the transmitter of the device. Then, the device, serving as the transmitting side, determines optimum values of output amplitude and emphasis of the transmitter and sets the same.