Abstract: The invention relates to Method for Selecting Subchannel Mode and MIMO Communication System Using the Same. A method for self-adaptively selecting a code modulation sub-channel mode is suitably used in a MIMO communication system that comprises a base station and mobile terminals, wherein the method comprises the steps of: the mobile terminal estimating channel state information thereof, and determining a sub-channel structure most suitable for data transmission thereto, based on the channel state information; the mobile terminal feeding back information on the determined sub-channel structure most suitable for data transmission thereto to the base station; and the base station determining a sub-channel structure used for a down link, based on the information on the sub-channel structure fed back by the mobile terminal.

Abstract: A communication receiver and a receiving method are disclosed. An analog front-end device samples a receiving signal and generates a sampled signal. A signal detector detects presence of the receiving signal according to the sampled signal. A symbol timing recovery (STR) unit determines an optimal symbol sampling point according to a zero-crossing point of the sampled signal when the receiving signal is present, and then generates a recovered symbol based on an optimally chosen sampled value according to the optimal symbol sampling point.

Abstract: A power consumption control method applied to a communication system adjusts the power consumption of a portion of circuit in the communication system according to a transmission distance between the communication system and another communication system. Another power consumption control method applied to a communication system adjusts the power consumption of a portion of circuit in the communication system according to a signal index of the communication system.

Abstract: A frequency translation filter includes a baseband filter circuit, a clock generator, and a switching circuit. The baseband filter circuit is operable to provide a baseband filter response. The clock generator is operable to generate multiple-phase clock signals at a desired frequency. The switching circuit is operable to frequency translate the baseband filter response of the baseband filter circuit to a high frequency filter response in accordance with the multiple-phase clock signals.

Abstract: A signal processing apparatus includes a first baseline wander correcting unit, provided in a processing path in which a predetermined processing is performed on an input signal, which corrects baseline wander by a feedforward and a second baseline wander correcting unit, provided anterior to the first baseline wander unit, which corrects the baseline wander by a feedback control. The first baseline wander correcting unit derives an amount of baseline wander. Further, it calculates a value corresponding to an average value of the amount of derived baseline wander and fine-adjusts a correction amount of baseline. Then it corrects the baseline wander by using the fine-adjusted baseline amount. The second baseline wander correcting unit calculates a value corresponding to an average value of the amount of baseline wander derived by the baseline wander derivation unit and coarse-adjusts a correction amount of baseline, and corrects the baseline wander by using the coarse-adjusted baseline amount.

Abstract: Techniques are disclosed relating to reducing wander created by AC couplers. In one embodiment, an integrated circuit is disclosed that includes an AC coupler and a DC-level shifter. The AC coupler is configured to receive a differential input signal at first and second nodes, and to shift a common-mode voltage of the differential input signal. The DC-level shifter is coupled to the first and second nodes, and configured to reduce wander of the AC coupler. In various embodiments, the DC-level shifter is configured to supply a differential reference signal to the AC coupler, and to create the differential reference signal from the differential input signal at the first and second nodes by changing a common-mode voltage of the differential input signal.

Abstract: A receiver includes a front-end amplifier, a sampler, and a decision-feedback equalizer. The front-end amplifier provides for amplifying a received input signal to yield an amplified input signal. The sampler provides for sampling the amplified input signal so as to yield a sampler output signal. The sampler output signal is a function of the amplified input signal and a reference signal coupled to a reference input of the sampler. The decision feedback equalizer provides for adjusting the reference signal as a function of feedback based at least in part on the sampler output signal.

Abstract: In one example embodiment, an optoelectronic module includes an optical receiver and a post-amplifier. The optical receiver is configured to receive an optical signal and generate an electrical data signal corresponding to the optical signal. The post-amplifier is electrically connected to the optical receiver and is configured to amplify the electrical data signal. The optoelectronic module further includes means for quantifying a quality of the optical signal from which the amplified electrical data signal is derived.

Abstract: An apparatus comprising an analog filter, an analog to digital converter coupled to said analog filter; and a digital filter coupled to said analog to digital converter; wherein the apparatus is configured such that distortion introduced into a filtered signal by said analog filter is substantially compensated by said digital filter.

Abstract: A receiving apparatus includes a first receiving circuit that receives an input signal based on a clock signal, and outputs a first output signal, a second receiving circuit that receives the input signal based on the clock signal, and outputs a second output signal, and a comparison circuit that compares value of the first output signal outputted by the first receiving circuit and value of the second output signal outputted by the second receiving circuit.

Abstract: According to an embodiment, a DC offset canceller includes a first DA converter, a first adder, an amplifier, a comparator, an averaging circuit, and a successive approximation register. The first DA converter is configured to DA-convert first correction data into a first correction voltage. The first adder is configured to add an input signal and the first correction voltage to output a first added signal. The amplifier is configured to amplify the first added signal to output an amplified signal. The comparator is configured to compare the amplified signal and a reference voltage to output a comparison result. The averaging circuit is configured to receive the comparison results of the comparator to obtain a majority decision result by performing majority decision on logical values of the comparison results in a predetermined time period.

Abstract: A serial communication system includes a receiver with an amplitude monitor. The amplitude monitor compares the input signal with a reference level in response to a sample clock. The sample clock is periodically phase shifted with respect to the incoming data so the amplitude monitor is sure to sample an incoming data eye at or near the peak amplitude over a selected sample period. The amplitude detector notes the detection of an input signal if the input signal surpasses the reference level for any sample phase. The amplitude monitor experiments with different sample-clock phases over a number of data symbols, but is capable of measuring amplitude fast enough to resolve amplitude-based signals used for rate negotiation.

Abstract: In accordance with some embodiments of the present disclosure, a method may include generating a first current equal to a bandgap voltage divided by a resistance selected to approximately match a process resistance integral to a receiver. The method may further include generating a second current equal to temperature-dependent current multiplied by a predetermined scaling factor. The method may also include subtracting the second current from the first current to generate a bias current. The method may additionally include providing the bias current to the receiver.

Abstract: A burst optical signal receiving device is provided, which includes an optical receiving component and a limiting amplifying circuit unit. The optical receiving component further includes a photodetector, a trans-impedance amplifier, a first direct current (DC) cancellation forbidding circuit, and a DC bias circuit, and the limiting amplifying circuit unit further includes a group of alternating current (AC) coupling capacitors, a limiting amplifier, and a second DC cancellation forbidding circuit. Through the technical solution, an input burst optical signal within a certain dynamic range can be recovered into a valid burst electric signal in shorter time. The technical solution can be applied in a burst optical signal receiver in a 10-Gigabit Ethernet passive optical network (10GEPON).

Abstract: A receiver includes: an amplifier that amplifies a received broadband signal up to a predetermined level; a first switch that switches an output signal from the amplifier; a signal generator that generates a signal for controlling a switching operation of the first switch; an integration capacitor that integrates an output signal from the first switch; a comparator that compares an output voltage from the integration capacitor with a predetermined voltage; and a reset circuit that discharges electrical charges accumulated in the integration capacitor based on a comparison result from the comparator.

Abstract: Provided is a pulse receiver capable of receiving a burst signal and decoding the burst signal with a bit error rate reduced to a target value or less by controlling a determination threshold such that decoding success rate is equal to or less than a predetermined value. A decode unit 140 decodes a pulse train 20 to information 30, counts the number of decoding successes for a predetermined time period and outputs the counted number (decoding success rate DR) to a control unit 150. The control unit 150 uses as a basis the decoding success rate DR communicated from the decode unit 140 to control the set value of reference voltage Vth used in the comparator 130.

Abstract: A receiver configured to selectively receive an RF signal from an operating band having a plurality of RF channels. The receiver is configured to upconvert the desired RF channel to an intermediate frequency (IF) greater than the RF channel frequencies. The upconverted RF channel is downconverted to baseband or a low IF. The receiver can perform channel selection by filtering the baseband or low IF signal. The baseband or low IF signal can be upconverted to a programmable output IF.

Abstract: Embodiments include a decision feedback equalizer (DFE) that includes a first comparator configured to receive as inputs a soft value and a first threshold, a second comparator configured to receive as inputs the soft value and a second threshold, a selector configured to select an output of either the first comparator or the second comparator as a DFE output based on one or more previous bits output by the selector; an error calculator configured to determine an error for the first comparator and the second comparator, and a threshold adjuster configured to adjust the first threshold and the second threshold, the first threshold and the second threshold each being a non-linear combination of one or more previous outputs of the selector.

Abstract: Apparatus and methods for removing dc offsets in feedback loops such as may be used in communication circuits are disclosed. A comparator may be used to sample the output of the feedback loop, with the comparator output applied to a DSP module. The DSP module is configured to determine a dc offset in the output signal and generate an offset correction signal, which may then be applied to the input of the feedback loop to adjust the de offset.

Abstract: A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design that operates at frequencies above 10 GHz, making it feasible to employ decision feedback equalization in optical transceiver modules. An adaptation technique is also disclosed to maximize communications reliability. The adaptation module can be treated as a straightforward extension of the pre-computation unit. At least some method embodiments include, in each time interval: sampling a signal that is partially compensated by a feedback signal; comparing the sampled signal to a set of thresholds to determine multiple speculative decisions; selecting and outputting one of the speculative decisions based on preceding decisions; and updating a counter if the sampled signal falls within a window proximate to a given threshold. Once a predetermined interval has elapsed, the value accumulated by the counter is used to adjust the given threshold.

Abstract: A linear equalizer (LEQ) includes a first transconductance device coupled to an input node of the LEQ and a second transconductance device AC coupled to the input node of the LEQ to increase a gain of the LEQ for data signals above a predetermined frequency. The first transconductance device and the second transconductance device are of complimentary types. A bimodal LEQ includes inputs to control operation of the bimodal LEQ in a current mode or a voltage mode. The bimodal LEQ includes first and second transconductance devices. One of the first and second transconductance devices is AC coupled to an input node to increase the gain for data signals above a predetermined frequency.

Abstract: Apparatus, systems, and methods are provided for controlling the output of a transmitter using a digital error signal. A method comprises generating a digital reference signal based on a baseband input signal and converting the digital reference signal to an analog reference signal. The method further comprises generating an analog error signal in response to a difference between the analog reference signal and an analog output signal. The method further comprises generating a digital error signal from the analog error signal, and generating an input signal for the transmitter based on the baseband input signal and the digital error signal.

Abstract: A method for adapting a threshold value of a detection device comprising the following steps: Transmission of a signal burst having a predefined pulse-repetition interval, a predefined burst length and a defined signal frequency; receiving and processing of a receive signal, in particular by means of amplification, filtering and demodulation, so as to obtain the envelope; determining a receive-signal magnitude as interference-level sample from the receive signal following a first predefined time duration (?t1) starting with a signal burst within a predefined second time duration (?t2), preferably at the end of the pulse repetition interval; and adapting the threshold value of the detection device as a function of the interference level sample. Also provided is a device for adapting a threshold value of a detection device.

Abstract: A technique for determining a frequency offset between components of a communication network based on a Constant Amplitude Zero Auto-Correlation (CAZAC) sequence is described. A method implementation of this technique comprises a provision of a set of correlation signals at different frequencies, with each correlation signal being indicative of a specific frequency offset hypothesis and comprising the CAZAC sequence. Once a synchronization signal comprising the CAZAC sequence is received, this synchronization signal is correlated with each of the correlation signals to obtain a correlation result for each frequency offset hypothesis. In a next step, at least one of the frequency offset hypotheses is selected based on a comparison of the correlation results. The frequency offset may then be determined based on the at least one selected frequency offset hypothesis.

Abstract: A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

Abstract: In an embodiment, set forth by way of example and not limitation, a data slicer includes a signal input node, a comparator having a first input of a first polarity, a second input of a second polarity which is the opposite of the first polarity, and an output coupled to a data out node, the first input of the comparator being coupled to the signal input node, and a multi-mode threshold generator including a first threshold generator and second threshold generator, whereby the first threshold generator is selected firstly and the second threshold generator is selected secondly.

Abstract: A wireless communications device may include a portable housing and a temperature-compensated clock circuit carried by the portable housing. The device may further include a wireless receiver carried by the portable housing for receiving timing signals, when available, from a wireless network, and a satellite positioning clock circuit carried by the portable housing. A clock correction circuit may be carried by the portable housing for correcting the temperature-compensated clock circuit based upon timing signals from the wireless network when available, and storing historical correction values for corresponding temperatures. The clock correction circuit may also correct the temperature-compensated clock circuit based upon the stored historical correction values when timing signals are unavailable from the wireless network, and correct the satellite positioning clock based upon the temperature-compensated clock circuit.

Abstract: A method and system using the principle of generalized maximum likelihood estimation to resolve sample timing uncertainties that are associated with the decoding of communication signals. By using generalized maximum likelihood estimation, sample timing uncertainty can be resolved by taking multiple samples of the received signal within a symbol period and determining which sample best corresponds to the optimal sample timing. The sample which best corresponds to the optimal sample timing can be determined from a timing index which can be calculated from ambiguity indicators that are based on the samples of the received signal.

Abstract: A system and method for generating for efficiently obtaining a desired harmonic from a fundamental frequency the prior art is needed. The system and method of the present invention produces a desired harmonic by employing techniques using gain stages (or limiter/comparator circuits) in combination with pre-defined offset voltages (or currents). The output signals of the gain stages are added with the correct phase to generate the desired harmonic.

Abstract: It is an object of the present invention to provide a multicarrier transmission system for enabling degradation of a transmission speed in an adjacent line adjacent to a communication line, to be avoided. For this purpose, a multicarrier transmission system in the present invention is a multicarrier transmission system configured so that a first communication device and a second communication device are connected via a communication line, wherein the first communication device controls a transmission output of a signal to be outputted to the above described communication line, based on a difference between a transmission distance of the above described communication line and a transmission distance of an adjacent line adjacent to the above described communication line.

Abstract: Provided are a reception apparatus and transmission apparatus for supporting a scalable bandwidth in a carrier aggregation environment. The reception apparatus and transmission apparatus can link carrier aggregation technology and scalable bandwidth technology by supporting a scalable bandwidth having different bandwidths in size in a carrier aggregation environment, thereby enhancing compatibility between different wireless communication systems.

Abstract: Unfolded adaptive/decision-directed loops and correction circuits therefor, architectures, apparatuses and systems including the same, and methods, algorithms and software for reducing latency in an adaptive and/or decision-directed loop. Disclosed embodiments advantageously reduce effects of loop latency, improve the accuracy of corrections in an adaptive loop, and minimize overhead and delays associated with such improvements.

Abstract: An adaptive cable equalizer includes a data signal input unit, a clock signal input unit, a variable equalizer that inputs a data signal input from the data signal input unit, and a transition time measuring portion that measures a transition time of a data signal output from the variable equalizer, with an equalizer control loop being configured that controls characteristics of the variable equalizer based on the output signal of the transition time measuring portion. The adaptive cable equalizer further includes a control circuit that controls response characteristics of the control loop according to the frequency of a clock signal input from the clock signal input unit. This enables a quick response at fast transfer rates by making the relationship between the response time of the control loop and the number of data bits substantially constant even when the transfer rate changes from a slow transfer rate to a fast transfer rate.

Abstract: An asymmetric DFE receiver circuit is disclosed. The receiver circuit includes a voltage measuring unit configured to determine a signal voltage of a received signal, and a comparator unit configured to calculate a difference between the signal voltage and an evaluation threshold voltage and to compare the difference to the value of a midpoint voltage. The comparator unit is configured to generate a first control signal if the difference is greater than the midpoint voltage value or a second control signal if the signal voltage is less than the midpoint voltage value. The receiver includes an adjustment circuit configured to adjust the evaluation threshold voltage toward the signal voltage if the first control signal is generated and away from the signal voltage if the second control signal is generated. The rates of adjustment may vary depending upon whether the received signal is a transition bit or a non-transition bit.

Abstract: There are provided video encoders and corresponding methods for performing fast mode decision of B-frames. A video encoder for encoding video data for a B slice that is divisible into macroblocks includes an encoder (OO) for performing mode selection when encoding a current macroblock in the B slice by counting a number of neighboring macroblocks in the B slice coded in a DIRECT mode, and only checking one of the DIRECT MODE or a 16×16 mode for the current macroblock when the number of neighboring macroblocks coded in the DIRECT mode exceeds a predetermined threshold.

Abstract: The invention is directed to a system and method of regulating a slicer for a communication receiver. A zero-crossing accumulator receives a slicer output from the slicer and accordingly determines a zero-crossing length of the slicer output. A threshold decision unit regulates at least one threshold value of the slicer according to the zero-crossing length.

Abstract: A receiver arrangement includes a single ended multiband feedback amplifier, at least one single ended input, differential output mixer arrangement including a main mixer and a trim mixer, and a mixer feedback loop circuit configured to receive differential output signals generated by the mixer arrangement. The mixer feedback loop circuit generates a feedback signal based on the received differential output signals and provides the feedback signal to the mixer arrangement to minimize DC-offset and second order intermodulation products. The single ended multiband feedback amplifier may include an input stage and a programmable resonance tank circuit connected to the input stage for suppressing downconverted noise from harmonics of the LO-frequency, and a configurable feedback net that shapes the frequency response of a feedback loop including the feedback net based on a band operation of the single ended multiband feedback amplifier.

Abstract: Systems and methods for transferring incoming single-ended burst signals of which at least one characteristic varies widely from burst to burst onto a pair of differential lines. The systems comprise an input for receiving an incoming burst signal, a signal adaptation block for adapting said widely varying characteristic and a single-ended-to-differential converter. In a first aspect a reset signal for resetting a settings determination block, which controls the signal adaptation block, is sent backwards over the differential lines, preferably using a common-mode signal. In a second aspect, a status freezing mechanism is employed for freezing the settings of the settings determination block after the end of the preamble of an incoming burst.

Abstract: A tail estimate signal which includes noise associated with baseline wander is generated. The tail estimate signal is generated by processing an input signal using a detector to obtain one or more decisions. Using the one or more decisions, the tail estimate signal is generated. The tail estimate signal is removed from the input signal.

Abstract: A method for inverting telecommunication channel distortion by adaptive wavelet lifting. The distortion signal is analyzed using wavelet lifting and the inverse filter is computed. Coefficients of the inverse filter are used to either compute a transmission pre-filter or to update the transmitted message.

Abstract: A passive mixer include a switching architecture configured to generate differential in-phase (I) and differential quadrature-phase (Q) signals using differential components of the in-phase (I) and quadrature-phase (Q) signals operating on transitions of an approximate 25% duty cycle signal.

Abstract: Briefly, a method an apparatus and a wireless communication device are provided. The wireless communication device includes a receiver to receive complex sequences of symbols. The receiver includes an estimator to estimate one or more channel taps. The estimator includes a memory to store at least a portion of one or more calculated values of an estimation matrix and is capable to estimate the one or more channel taps based on a stored portion of calculated values of the estimation matrix.

Abstract: A multiple-input multiple-output (MIMO) system can transmit on multiple antennas simultaneously and receive on multiple antennas simultaneously. Unfortunately, because a legacy 802.11a/g device is not able to decode multiple data streams, such a legacy device may “stomp” on a MIMO packet by transmitting before the transmission of the MIMO packet is complete. Therefore, MIMO systems and methods are provided herein to allow legacy devices to decode the length of a MIMO packet and to restrain from transmitting during that period. These MIMO systems and methods are optimized for efficient transmission of MIMO packets.

Abstract: Methods and apparatus for gathering information about the eye of a high-speed serial data signal include sampling each bit of a repeating, multi-bit data pattern at several eye slice locations. For any given eye slice location, each bit in the data pattern is compared in voltage to a base line reference signal voltage to establish a reference value for that bit. Then the reference signal voltage is gradually increased while the voltage comparisons are repeated until for some bit a result of the comparing is different than the reference value for that bit. This establishes an upper value for the eye at the eye slice location. The reference signal voltage is then gradually decreased to similarly find a lower value for that eye slice.

Abstract: Methods and apparatus are provided for determining receiver filter coefficients for a plurality of phases. One or more coefficients for a receiver filter are determined by determining a first coefficient for a first phase of a data eye; and determining a second coefficient for a second phase of the data eye. The receiver filter may be, for example, a decision-feedback equalizer. The first and second coefficients may be determined by performing an LMS adaptation of decision-feedback equalization coefficients. In another embodiment, the first and second coefficients may be determined by obtaining eye opening metrics from a data eye monitor corresponding to each of the respective first phase and the second phase; and determining the respective first and second coefficients based on the eye opening metrics. The first and second phases can correspond to odd and even phases.

Abstract: An embodiment of the proposed invention is primarily applied to compensate the BLW in communication systems using THPs in their transmitters, especially suitable for the 10GBase-T Ethernet application. The present apparatus includes an additional decision device (slicer) used to generate DC offset information (error signal) and an extra modulus unit after our BLW compensator to reconvert compensated symbols to correct 16-PAM signals. In addition, the estimated error signals in our method are generated from the difference between the input of the BLW compensator and the output of the decision device. These error signals are then weighted to alleviate the impact of erroneous DC offset information on the performance of the BLW compensator. Therefore, a more direct and accurate DC offset information can be derived to improve the inaccurate BLW estimation in previous works.

Abstract: Compensation of transmit baseline wander in data transmission on a network. In one aspect, compensating for baseline wander includes receiving a signal to be transmitted by a transmitter, where the transmitter is operable with a higher-speed transmission standard requiring magnetics a first open circuit inductance. The signal is processed to compensate for a transmit baseline wander in the signal, the transmit baseline wander associated with a lower-speed transmission standard that requires magnetics with a second open circuit inductance that is higher than the first open circuit inductance. The processed signal is to be provided for transmission on a twisted pair cable of the network.

Abstract: Amplifier for an ultra-wideband (UWB) signal receiver having a signal input (15) for receiving an ultra-wideband signal which is sent by a transmitter (1) and which is transmitted in a sequence of transmission channels (Ki) (which each have a particular frequency bandwidth) which has been agreed between the transmitter (1) and the receiver (4); a transistor (18) whose control connection is connected to the signal input (15); a resonant circuit (26, 30, 31) which is connected to the transistor (18) and whose resonant frequency can be set for the purpose of selecting the transmission channel (Ki) in line with the agreed sequence of transmission channels; and having a signal output (29) for outputting the amplified ultra-wideband signal, the signal output being tapped off between the transistor (18) and the resonant circuit.

Abstract: A method for demodulating a radio frequency signal according to one embodiment includes receiving digital signals derived from a radio frequency signal; converting the digital signals to baseband signals; generating a frequency error signal using the baseband signals during an acquisition period; and shifting a frequency of the digital signals towards zero frequency error during the acquisition period using the frequency error signal, with the proviso that the digital signals are not phase locked during the shifting. Such methodology may also be implemented as a system using logic for performing the various operations. Additional systems and methods are also presented.

Abstract: In one embodiment, the present invention is directed to an apparatus configured to perform channel filtering operations digitally, to reduce area and power consumption as compared to analog filtering. After passive filtering of downconverted analog baseband signals, the signals are provided to digitization circuitry to convert the filtered baseband signals into digital signals. Then a digital circuit, which may be implemented as a digital signal processor (DSP), may channel filter the digital signals and provide the filtered digital signals to conversion circuitry to convert the channel filtered digital signals back to analog signals.