Abstract: Methods, systems, and devices for generating a balanced codeword protected by an error correction code are described. A memory device may receive data bits for storage. Based on the data bits, the memory device may generate a codeword that includes the data bits, parity bits, and placeholder bits. The memory device may balance the codeword by inverting one or more packets of the codeword. After balancing the codeword, the memory device may store at least a portion of the codeword in memory so that a later operation or a decoding process reveals the packets that were inverted as part of the balancing process. Accordingly, the memory device may re-invert the appropriate packets to recover the original data bits.

Abstract: The present disclosure provides a method for estimating a frequency offset, including: extracting sampling points from an input signal according to preset intervals to obtain a plurality of groups of sampling points, with the preset intervals of the groups of sampling points being different; performing processes on a current sampling point and the groups of sampling points to obtain data of arguments of complex numbers corresponding to the preset intervals; and determining an estimation value of a frequency offset of a current input signal according to the data of arguments of complex numbers corresponding to the preset intervals. The present disclosure further provides an apparatus for estimating a frequency offset, an electronic device and a computer-readable medium.

Abstract: A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.

Abstract: The present disclosure generally relates partial speed changes to improve in-order data transfer. Rather than determining an ECC decoder on a first available decoder basis, the ECC decoder may be based on the ECC decoder level. A memory device will have at least one FMU that has a syndrome weight (SW). The disclosure proposes assigning FMU's based on the SW rate. At the time the command is read, the data storage device determines which level of decoder will be assigned to the FMU. The determination will then be checked according to different system environment parameters to maintain performance or reduce power consumption. The arrangement allows a more flexible system design that can adapt according to the current system status.

Abstract: A communication control device according to an embodiment includes one or more hardware processors functioning as a transmission control unit and a communication unit. The transmission control unit performs control of transmission of messages by opening and closing a gate based on transmission permission information. The transmission permission information is generated based on gate control information including a plurality of entries for determining whether to open a plurality of gates corresponding to a plurality of queues. The transmission permission information indicates an amount of transmittable messages in a period corresponding to one or more continuous entries. The communication unit transmits and receives messages in accordance with the control of the transmission control unit.

Abstract: A wireless local area network (WLAN) station receiver has a center frequency offset (CFO) estimator and an CFO table with an association between a CFO value from a recently received access point packet for which the station is associated according to 802.11. The receiver performs a comparison between the CFO estimate of the received packet and the CFO value from the CFO database, and powers the receiver down if the comparison exceeds a threshold. The threshold may be an absolute value in parts per million, or may include a time drift compensation component.

Abstract: A user input system comprising a vibration motor, a sensor and a processor in communication with the sensor. The vibration motor is in contact with a surface and generates vibrations in the surface. The vibrations can be altered by a user touching the surface to create altered vibrations. The sensor is in contact with the surface and detects the altered vibrations. The processor receives and analyzes data corresponding to the altered vibrations. The processor determines, based on the analyzed data, whether a user's touch on the surface matches a stored vibration profile of the user.

Abstract: In accordance with an embodiment, a device configured to detect a presence of at least one digital pattern within a signal includes J memory circuits having respectively Nj memory locations; and processing circuitry comprising an accumulator configured to successively address the memory locations of the J memory circuits in a circular manner at frequency F and during an acquisition time, and successively accumulate and store values indicative of a signal intensity in parallel in the J addressed memory locations of the J memory circuits, and a detector configured to detect the possible presence of the at least one pattern.

Abstract: A circuit for processing a data stream is described. The circuit comprises a burst phase detector configured to receive a data input signal; a clocking circuit coupled to the burst phase detector, wherein the clocking circuit is configured to receive a delayed data input signal and to receive a data stream phase signal and a data stream detect signal; and a programmable clock generator configured to receive a plurality of clock signals; wherein a selected clock signal of the plurality of clock signals is generated by the programmable clock generator and provided to the burst phase detector and the clocking circuit.

Abstract: Computerized methods and systems obtain information associated with a first device attempting to connect with a second device that has a MAC address having an LAP and UAP. A transceiver is tuned to a frequency band at least covering a first channel represented in one or more candidate channel sequences, and receives a first packet transmitted by the first device. One or more second channels that each immediately follow the first channel in a corresponding one of the one or more candidate channel sequences are identified. The transceiver is tuned to a frequency band at least covering one of the second channels, and receives a second packet transmitted by the first device. A controller/processor processes the received second packet to determine whether the second packet is a valid packet. If the packet is a valid packet, the controller/processor extracts information from the second packet.

Abstract: A method and system are disclosed for blind decoding of Bluetooth packets. According to one aspect, a method of decoding packets includes detecting a packet using blind LAP detection. The method also includes estimating a duration of a payload of the packet and decoding a payload of the packet over the estimated duration according to each of a plurality of forward error correction (FEC) coding rates to produce a packet header. For each of a plurality of de-whitening seeds, the method includes performing de-whitening, extraction and reverse decoding on the packet header to produce a plurality of candidate upper address parts (UAPs). The method includes obtaining a subset of the candidate UAPs, each candidate UAP having a corresponding CRC code, and forming an ordered list of candidate packet types based at least in part on the estimated duration. The method includes performing a CRC to select a UAP.

Abstract: One example includes a frame synchronization module. The module includes a search correlator configured to find a first unique word (UW) pattern in a first set of digital sample blocks of a first data frame and a second UW pattern in a second digital sample blocks of a second data frame. The module also includes a buffer configured to store the first and second data frames and to concurrently release the buffered first and second data frames for downstream processing in response to time-aligning the first and second UW patterns of the respective first and second sets of digital sample blocks being aligned to a clock index.

Abstract: A method comprising operating at least one hardware processor for: receiving, by a radio frequency (RF) receiver, a plurality of training RF transmissions from an RF device, wherein each of said training RF transmissions is temporally associated with operational parameters and ambient parameters of said RF receiver and said RF device; at a training stage, training a machine learning classifier based, at least in part, on a training set comprising: (i) a Carrier Frequency Offset (CFO) value calculated for each of said training RF transmissions, and (ii) labels associated with said operational parameters and said ambient parameters; and at an inference stage, applying said machine learning classifier to determine whether one or more runtime RF transmissions originate from said RF device.

Abstract: Based on at least a portion of an SS block index, a UE may scramble information and a base station may descramble the scrambled information. Specifically, a UE may determine an SS block index associated with an SS block for reception. The UE may scramble information based on at least a portion of the determined SS block index. The information may include at least one of data, control information, or a CRC associated with control information. The UE may transmit the scrambled information to a base station. A base station may receive, from the UE, information scrambled based on at least a portion of an SS block index. The scrambled information may include at least one of data or control information. The base station may descramble the scrambled information based on the at least the portion of the SS block index.

Abstract: A method of performing clock synchronization between two apparatuses includes storing, in a first apparatus, information representing synchronization accuracy required by at least one function of the apparatus; carrying out, by the first apparatus, a service discovery procedure with a second apparatus, and receiving clock information from the second apparatus during the service discovery procedure; determining, by the first apparatus on the basis of the received clock information and said stored information, whether or not synchronization accuracy is sufficient for the at least one function; and upon determining that the synchronization accuracy is sufficient for the at least one function, synchronizing a clock of the first apparatus with a clock of the second apparatus.

Abstract: Disclosed are a multi-lane synchronization method and apparatus. The method includes: forming N data frames, frame headers of the N data frames including an identical frame header sequence, N being greater than or equal to 1 and less than or equal to the number of lanes M, and M being an integer not less than 2; and sending the N data frames via N lanes, wherein different data frames are sent via different lanes, and the frame header sequence is configured to perform frame synchronization between a receiving end and a sending end or to check frame synchronization. Also disclosed are a synchronization system and a computer storage medium.

Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.

Abstract: A sequence allocating method and apparatus wherein in a system where a plurality of different Zadoff-Chu sequences or GCL sequences are allocated to a single cell, the arithmetic amount and circuit scale of a correlating circuit at a receiving end can be reduced. In ST201, a counter (a) and a number (p) of current sequence allocations are initialized, and in ST202, it is determined whether the number (p) of current sequence allocations is coincident with a number (K) of allocations to one cell. In ST203, it is determined whether the number (K) of allocations to the one cell is odd or even. If K is even, in ST204-ST206, sequence numbers (r=a and r=N-a), which are not currently allocated, are combined and then allocated. If K is odd, in ST207-ST212, for sequences that cannot be paired, one of sequence numbers (r=a and r=N-a), which are not currently allocated, is allocated.

Abstract: The present disclosure relates to random access in wireless communication systems, and in particular to a wireless device, a preamble receiver, and methods for processing random access preamble signals. A disclosed method in a wireless device comprises generating (S11) one or more identical short sequences having a same time duration as an OFDM symbol used for carrying data traffic in a radio access network of the wireless device. The method also comprises generating (S12) at least one offset indicator sequence different from each of the short sequences, and constructing (S13) the preamble sequence by concatenating the at least one offset indicator sequence and the one or more identical short sequences in time, such that each of the at least one offset indicator sequence has a respective pre-determined location in the preamble sequence.

Abstract: A method for transmitting a synchronization signal by a transmitting side device to a receiving side device in a wireless access system. The method includes generating a concatenated code sequence in a frequency domain by concatenating a first code sequence having a first index (M1) and a second code sequence having a second index (M2). Each of the first code sequence and the second code sequence is obtained by cyclic shifting a code sequence. The concatenated code sequence is mapped to subcarriers for transmitting the synchronization signal via a secondary synchronization channel (S-SCH). The method further includes transforming the concatenated code sequence into a time domain signal; and transmitting the time domain signal to the receiving side device as the synchronization signal. The concatenated code sequence indicates a cell group identity (ID).

Abstract: A method for accessing a flash memory module includes: sequentially writing Nth-(N+K)th data to a plurality of flash memory chips of the flash memory module, and encoding the Nth-(N+K)th data to generate Nth-(N+K)th ECCs, respectively, where the Nth-(N+K)th ECCs are used to correct errors of the Nth-(N+K)th data, respectively, and N and K are positive integers; and writing the (N+K+1)th data to the plurality of flash memory chips of the flash memory module, and encoding the (N+K+1)th data with at least one of the Nth-(N+K)th ECCs to generate the (N+K+1)th ECC.

Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.

Abstract: Disclosed is a method of controlling a USB Power Delivery System including determining whether at least a predetermined length of initial bits of a message is received, turning on a clock when the predetermined length is received, determining whether the message has stopped, starting a counter when the message has stopped, determining whether a count value of the counter has reached a predetermined value, and turning off the clock when the predetermined count value has been reached.

Abstract: According to an embodiment, a wireless communication device, which complies with plural communication methods, includes a storing circuit and a received data selection determining circuit. The storing circuit sequentially stores a first received data until the first received data reaches a predetermined data size. When it is assumed that a radio signal complies to a second communication method, a first period is longer than a second period. The first period is a period from a first time when a reception of the radio signal is started to a second time when the first received data with the data size is stored. The second period is a period from the first time to a time when a second reception start signal is detected. The received data selection determining circuit determines a selection of the first received data, when the second reception start signal is not detected at the second time.

Abstract: An embedded system and, in particular, a communication protocol suitable for a data transmission using auxiliary physical channels of such an embedded system. A transmission method suitable for such a channel includes the transmission of a data signal based on the encoding of three symbols. The message consists of a preamble allowing recognition of the symbols used, followed by the significant part of the message. The decoding of the message comprises a first step of learning the symbols used, prior to the decoding of the significant part of the message.

Abstract: The present disclosure relates to a method of exchanging data packages between first and second portable communication devices over a bi-directional wireless communication channel. The method includes generating, by the first portable communication device, a first data package belonging to a first packet category comprising audio data or to a second packet category without audio data and transmitting the first data package from the first portable communication device to the second portable communication device through the wireless communication channel. Where an acknowledgement indicator of the second data package is unset or the second data package is absent, the first portable communication device retransmits the first data package from the first to the second portable communication device for at the most N times if the first data package belongs to the first packet category; N being a positive integer between 1 and 4.

Abstract: A wearable device and external reader is provided for herein. In some embodiments of the present disclosure, the wearable device or the reader is configured to receive a level of radiant energy, detect a change in the received level of radiant energy, determine that the detected change in the received level of radiant energy is indicative of a predetermined pattern of received radiant energy, and responsively operate (or cause to be operated via the external reader) one or more external devices.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter or a receiver. In one embodiment, the transmitter is for use with a base station and includes a primary module configured to provide a primary synchronization signal. The transmitter also includes a secondary mapping module configured to provide a secondary synchronization signal derived from two sequences taken from a same set of N sequences and indexed by an index pair (S1, S2) with S1 and S2 ranging from zero to N?1, wherein the index pair (S1, S2) is contained in a mapped set of index pairs corresponding to the same set of N sequences that defines a cell identity group. Additionally, the transmitter further includes a transmit module configured to transmit the primary and secondary synchronization signals.

Abstract: A method for providing information to a driver of a vehicle includes receiving, at a host vehicle via a wireless electronic communication link, messages that each include remote vehicle information for a respective one of the one or more remote vehicles; identifying host vehicle information for the host vehicle; determining that a potential message occlusion exists based at least in part on the remote vehicle information for the one or more remote vehicles and the host vehicle information; and in response to determining that a potential message occlusion exists, causing a message occlusion alert to be output.

Abstract: A joint preamble and code rate identifier flag in a reserved portion of a data field synchronization segment in a digital television (DTV) data field identifies the presence of preamble training data in a forward error correction (FEC) encoded portion of the DTV data field. The identifier flag also indicates the code rate used for the data field. The data field synchronization segment is not FEC encoded, thereby allowing detection of the identifier flag without FEC decoding. The detection at a receiver of the identifier flag in a DTV data field allows receiver elements, such as an equalizer and a FEC decoder, to more readily obtain and utilize the preamble training data, thereby enhancing reception and/or simplifying receiver design.

Abstract: A transmitting apparatus, a receiving apparatus, and a communication system are provided that allow a reduction in a frame loss due to interference caused by use of the same channel. A transmitting apparatus disposed in a base station includes a GPS receiver for receiving a GPS signal, a timing generator for controlling respective function blocks in accordance with the GPS signal and an inter-base-station control signal so as to precisely synchronize the timing of frame transmission among base stations, the front-end transmission processing unit including for converting transmission information into transmission time slots, a frame generator for generating a frame including a plurality of time slots and one frame guard, and a back-end transmission processing unit for transmitting the generated frame as a radio signal.

Abstract: A preamble identifier flag in a reserved portion of a data field synchronization segment in a digital television (DTV) data field identifies the presence of preamble training data in a forward error correction (FEC) encoded portion of the DTV data field. The data field synchronization segment is not FEC encoded, thereby allowing detection of the preamble identifier flag without FEC decoding. The detection at a receiver of the preamble identifier flag in a DTV data field allows receiver elements, such as an equalizer and a FEC decoder, to more readily obtain and utilize the preamble training data, thereby enhancing reception and/or simplifying receiver design.

Abstract: A system and method of extracting data from data packets transmitted over a wireless network includes receiving a data packet having a preamble portion and a payload portion. The preamble portion is cross correlated with a first known spreading sequence to generate a first timing signal and the preamble portion is cross correlated with a second known spreading signal to generate a frame timing signal. An impulse is detected in the first timing signal and a first timing parameter is set based upon the detected impulse in the first timing signal. An impulse is detected in the frame timing signal and a frame timing parameter is set based upon the detected impulse in the frame timing signal. Data is extracted from the received payload portion according to the first timing parameter and the frame timing parameter.

Abstract: In the subject system for polarity detection, link initialization between a primary device and a secondary device may be performed in at least two stages, a half-duplex stage when only the primary device transmits initialization signals and any encoded handshaking signals may be set to false, and a full-duplex stage when both devices may transmit initialization signals. The secondary device may perform polarity detection during the half-duplex stage. If the secondary device determines that the polarities of the received signals are reversed, the secondary device may reverse the polarities of any signals subsequently received from, and transmitted to, the primary device. In this manner, the polarities can be corrected for both devices during the half-duplex stage by the secondary device. The secondary device may initiate the full-duplex link initialization stage, during which any handshaking signals may be exchanged, by transmitting signals to the primary device.

Abstract: A radio frequency ranging system is grounded in establishing and maintaining phase and frequency coherency of signals received by a slave unit from a master unit and retransmitted to the master unit by the slave unit. For a preferred embodiment of the invention, coherency is established through the use of a delta-sigma phase-lock loop, and maintained through the use, on both master and slave units, of thermally-insulated reference oscillators, which are highly stable over the short periods of time during which communications occur. A phase relationship counter is employed to keep track of the fractional time frames of the phase-lock loop as a function of the reference oscillator, thereby providing absolute phase information for an incoming burst on any channel, thereby enabling the system to almost instantaneously establish or reestablish the phase relationship of the local oscillator so that it synchronized with the reference oscillator.

Abstract: A system may include one or more high-speed serial interfaces for moving data. A system may include a transmission unit configured to serially transmit data bits, and a receiving unit coupled to the transmission unit. The receiving unit may receive a stream of data bits from the transmission unit and establish an initial sample point. The receiving unit may then sample the bits at multiple offsets from the initial sample point, reestablishing the initial sample point between each offset. The receiving unit may also calculate bit error rates (BERs) for the samples taken at each sample point. Based on the BERs, the receiving unit may set a data sampling point for receiving a second stream of data bits from the transmitter unit. The receiving unit may limit the amount of time the data sampling point is used and recalculate the data sampling point when the amount of time has expired.

Abstract: A data signal receiver includes a clock signal filter, a falling pulse signal generator, a mixing block, and a sampler. The clock signal filter generates a first filtered clock signal and a second filtered clock signal by filtering a clock signal. The falling pulse signal generator generates a falling pulse signal based on the first filtered clock signal. The mixing block generates a mixed data signal by mixing a data signal and the falling pulse signal. The sampler generates a recovered data signal by sampling the mixed data signal in response to the second filtered clock signal.

Abstract: Systems and methods for discrete signal synchronization based on a known bit pattern are described. In one aspect of the present subject matter, a discrete signal synchronization system is configured to synchronize a preprocessed discrete signal with a modified discrete signal. The system comprises a processor and a synchronization module coupled to the processor. The synchronization module comprises an extraction module and comparison module. The extraction module determines a bit pattern from the modified discrete signal using Discrete Wavelet Transformation (DWT) and Singular Value Decomposition (SVD). The comparison module compares the determined bit pattern with a known bit pattern of the preprocessed discrete signal and records a time point at which the determined bit pattern matches with the known bit pattern of the preprocessed discrete signal as a synchronization point.

Abstract: A method of determining at a receiver whether a received signal comprises a pure tone signal component. The method comprises: measuring a received signal over a measurement period; calculating, using maximum likelihood hypothesis testing, a likelihood ratio value for the measured signal and, determining, based on said likelihood ratio value, whether the measured signal comprises a pure tone signal component. The likelihood ratio value is a value indicative of the ratio of a likelihood LFSC that the measured signal comprises a pure tone signal component, and a likelihood LnoFSC that the measured signal does not comprise the pure tone signal component.

Abstract: A modem and a method of placing a modem in an online data state. In one embodiment, the modem includes: (1) a digital interface configured to receive, via an AT channel thereof, a standard AT command directing an AT channel of the modem to exit a command state and enter an online data state and (2) a command processor coupled to the digital interface and configured to: extract channel designation data received as a standard parameter of the standard AT command, cause a channel designated by the channel designation data and separate from the AT channel to enter the online data state, and allow the AT channel to remain in the command state.

Abstract: An object of the present invention is to provide a receiving apparatus and a receiving method capable of preventing phase rotation of a signal after FFT from occurring on a frequency domain. Further, the receiving apparatus according to the present invention is provided with: a window control unit configured to control a position of an FFT window in which FFT is performed to the time domain signal, and output FFT data corresponding to the FFT window; a signal delaying unit configured to generate, from the time domain signal, a plurality of delay signals with different delay amounts; and a signal switching unit having a switch for outputting by switching between two of the time domain signal and the plurality of delay signals based on a predetermined switch timing, the signal switching unit being configured to output the FFT data including the output signal of the switch.

Abstract: One aspect of the present invention includes a bi-phase communication receiver system. The system includes an analog-to-digital converter (ADC) configured to sample a bi-phase modulation signal to generate digital samples of the bi-phase modulation signal. The system also includes a bi-phase signal decoder configured to decode the bi-phase modulation signal based on the digital samples. The system further includes a preamble detector comprising a digital filter configured to evaluate the digital samples to generate an output and to detect a preamble of the bi-phase modulation signal for decoding the bi-phase modulation signal based on the output.

Abstract: A communication system includes a first communication device and a second communication device for performing power line communication using a power line as a transmission line with the first communication device, and in the communication system, the first communication device includes a detection mechanism for detecting a zero crossing timing of a commercial power supply and transmitting mechanism for transmitting a transmission signal modulated in OFDM mode at the zero crossing timing, the transmitting mechanism first transmits a header signal having a preamble as the transmission signal when the power line communication is started, and the transmitting mechanism transmits a data signal having no preamble as the transmission signal after the header signal is transmitted, and the second communication device includes a receiving mechanism for performing a demodulation process on the transmission signal which is received, to thereby obtain receiving data.

Abstract: A method in a QAM receiver (100) for performing timing recovery. The QAM receiver (100) is configured to receive a sequence of symbols. Each symbol is represented by a respective IQ pair comprising a respective inphase component I and a respective quadrature component Q. The QAM receiver (100) samples the respective I component and the respective Q component with a relative timing offset between the sampling of the respective I component and the respective Q component. The QAM receiver (100) establishes a first value associated to a quality of the I component samples, and a second value associated to a quality of the Q component samples, and compares the first value and second value to determine if the sampling timing should be advanced or delayed to improve the sample quality. The QAM receiver (100) adjusts subsequent sampling by advancing or delaying a sampling timing based on the comparison.

Abstract: A technique includes receiving a datum indicative of a candidate delimiter in a receiver; and processing the datum in a machine to determine whether the datum indicates a synchronization delimiter. The processing includes comparing the candidate delimiter with a reference delimiter to identify at least one error in the candidate delimiter; and basing the determination of whether the datum indicates the synchronization delimiter at least on a bit position of of each error.

Abstract: A method and apparatus for transmitting or detecting primary synchronization signal. The receiver receives primary synchronization signal from a transmitter, and detects the sequence used in the received primary synchronization signal by using three root indexes. Here, the primary synchronization signal is generated by using a Zadoff-Chu sequence having one of the three root indexes. The three root indexes comprise a first index and a second index, and a sum of the first index and the second index corresponds to the length of the Zadoff-Chu sequence.

Abstract: Systems, methods, and other embodiments associated with preamble detection based on repeated preamble codes are described. According to one embodiment, an apparatus is provided that wirelessly receives a signal and calculates a differential output corresponding to a multiplication of the signal and a delayed version of the signal. A cross correlation is performed between the differential output and a known preamble pattern to produce a cross correlation output. One or more peaks are detected in the cross correlation. The detected peaks are used in subsequent processing to detect the known preamble pattern in the wirelessly received signal.

Abstract: Receiver synchronization techniques (RST), contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of the receiver clock, and phase and frequency recovery techniques, comprising a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing signals or time referencing messages wherein SCCS includes a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality.

Abstract: A transmission apparatus includes a plurality of orthogonal frequency division multiplexing (OFDM) modulation signal generators, which generate a first OFDM modulation signal and a second OFDM modulation signal. The transmission apparatus also includes a transmitter that transmits the first OFDM modulation signal from a first antenna and the second OFDM modulation signal from a second antenna, in an identical frequency band.

Abstract: Methods and systems for augmenting a source message by suitably-chosen bits and/or sequences of bits for the purpose of enhancing decoding or synchronization performance. Properties of the source message can be used to select and optimize synchronization sequences, including their length and placement within the source message. Various message attributes, such as message or segment weight, symbol counts, and others, including their combinations, may be encoded into the synchronization sequence to further improve decoding performance in the presence of errors. These methods and systems can be employed for standalone source decoding of noisy bit streams, as well as iterative joint source-channel decoding. They may further be combined with other methods whether or not known in the art, such as CRC and forward error correction, to achieve the desired performance complexity trade-off.