Abstract: A method for use in a receiver in an orthogonal frequency division multiplexing-based data transmission system of detecting frame synchronization with respect to a signal received from a transmitter in the system comprises the following steps. First, the received signal is searched at a first predetermined sub-carrier frequency and at least a second predetermined sub-carrier frequency for a previously inserted data pattern. Then a frame boundary in the received signal is identified as a position where the data pattern is detected at both the first predetermined sub-carrier frequency and the second predetermined sub-carrier frequency.

Abstract: There is provided a method of detecting a block sync signal in which a sync signal and code sequence can be distinguished from each other to recognize the head of a block composed of a plurality of code words at the time of data reading or reception. A sync word detector (10) is supplied with a window signal Sync_window generated based on a parity OK signal supplied from a parity check circuit (12) and indicating a period between the sync word included in signal read from the medium (1) and the ID information, and detects the sync word as to a bit string detected by a PRML Viterbi detector (6) with the use of the Sync_window signal.

Abstract: A method to train a radio includes the steps of: in a radio (36), receiving a slot of information (2) containing at least an initial portion (4) containing training information (10), a second portion (5) containing training information (11), which second portion (5) is separated from the initial portion (4), and a concluding portion (6) containing training information (12), which concluding portion (6) is separated from the second portion (5). The method combining one of the initial portion (4) with the concluding portion (6a) of a previous slot of information (1) and the concluding portion (6) with an initial portion (4b) of a subsequent slot of information (3) to provide an at least one combined portion of training information. The method using the at least one combined portion of training information and the second portion of training information to train the radio.

Abstract: A timing device for generating and outputting a plurality of signal edges by changing signal statuses at predeterminable times. The timing device includes a cyclically addressable memory in which a plurality of time events are stored. Each time event is assigned a time value, which corresponds to a predetermined time, and a plurality of predetermined signal statuses. The timing device further includes a comparator, which compares the current count of a counter to the time value of a time event, which has just been acquired from memory. Given a match, the next time event is read from the memory. The timing device also includes an output device which outputs the predetermined signal statuses. With the timing device it is possible to freely program periodically recurring time indications by allocating memory accordingly.

Abstract: A system and method of frame synchronization and detection for use in a digital receiver within a communication system. The digital radio communication system includes a receiver for receiving a signal stream that includes data frames. Each frame includes an arbitrary data sequence and a unique word. A predetermined number of contiguous bits from the unique word are appended to the beginning of each data frame to identify the start of the data frame. The communication system comprises a sampling circuit for sampling symbol levels, a filter to implement the cross correlation of the received signal with the stored unique word, a threshold detector circuit to detect when frame synchronization is achieved as well as additional circuitry to refine the estimate from the threshold detection circuit. The design utilizes coherent demodulation. However, the design is equally applicable to non-coherent demodulation. In one embodiment, the sampling rate is assumed to be two samples per symbol.

Abstract: A method of estimating the frequency at the receiving end for a packet transmission system, for estimating a carrier frequency error between received symbols (rk) and transmitted symbols (ck). An error function (H(&Dgr;{circumflex over (f)})) defined for minimizing a magnitude which is representative of an average distance between the received symbols compensated in phase (r′k) and estimations of the received symbols affected by a frequency error estimation (ĉkej2&pgr;k&Dgr;{circumflex over (f)}) is computed. The estimations of the received symbols affected by the frequency error estimation are obtained by varying the frequency error (&Dgr;{circumflex over (f)}) in an acquisition interval ([−fmax, +fmax]) for estimations of the transmitted symbol (ĉk). The estimations of the transmitted, symbols (ĉk) are obtained based on a threshold relating to the phase of the received symbol which is compensated in phase (r′k), in the case of a modulation of the PSK type.

Abstract: An information processing apparatus in which an eye center measuring unit determines a code judgment point from a peak timing signal supplied from a timing signal generation circuit and an amplitude signal supplied from an interpolator and detected by an amplitude detector, and outputs it to a multiplier via an amplifier, a subtracter, and a reciprocal generating unit. A zero cross point measuring unit determines a code change point from a zero cross timing signal supplied from a timing signal generation circuit and an amplitude signal supplied from the interpolator and detected by the amplitude detector, and outputs it to the multiplier via a subtracter. The multiplier multiplies the supplied signals, and a dB converter converts a supplied signal into a signal in decibels and outputs the signal to a display circuit.

Abstract: The invention relates to a method for forming a training sequence in a communication system, in which information is transmitted at one or several carrier frequencies, the training sequence (T) being used at least as a synchronization signal. The training sequence (T) is composed of three or more training parts (103-106; 209-212) by any of the following methods. In the first method, at least two adjacent training parts (103, 104; 209, 210) in the training sequence (T) are formed substantially identical, and furthermore, at least one training part (105, 106; 211, 212) is formed substantially as a negation to said identical training parts (103, 104; 209, 210). In the second method, at least two adjacent training parts (103, 104; 209, 210) in the training sequence (T) are formed substantially identical, and furthermore, at least one training part (105, 106; 211, 212) is formed substantially different from said identical training parts.

Abstract: A method and related circuit for recovering a digital signal can operate with a sampling frequency less than a data frequency. The circuit includes a plurality of interpolators for generating an output signal. The output signal is used by a computation module to generate a plurality of control words. The control words are used by the interpolators to perform weighted interpolation functions to precisely generate the output signal. A data circuit can then extract the original input signal digital information from the output signal.

Abstract: A receiver produces complex data samples from a demodulated received signal. The data samples, which may form a preamble identifying a wireless LAN data burst, are arranged in a sequence comprising sub-sequences having a predetermined relationship with each other. A tuning frequency offset is determined by delaying the complex data samples by a plurality of different delay periods, auto-correlating the complex data samples using said different delay periods in order to produce respective auto-correlation outputs, determining a plurality of phase-dependent values each dependent upon phase errors in a respective auto-correlation output and calculating a value representing frequency offset by combining the phase-dependent values in a weighted manner. The preamble can be recognised by using the same delay means.

Abstract: The present invention provides a method to achieve frame synchronization from a received data sequence before the carrier phase and frequency offset recovery for any MPSK modulated signals on the basis of maximum likelihood theory. Two overhead configurations are considered in developing the frame synchronization algorithms. One overhead configuration consists of a unique word followed by a preamble, and the other consists of unique word only. For the first overhead, the frame synchronization can be decoupled from carrier recovery because the preamble following the unique word is a known sequence pattern. In this case, the maximum-likelihood frame synchronization rule is simply a complex correlation. In second overhead, the unique word is immediately followed by random traffic data and thus the coupling effects are generated between frame synchronization and carrier recovery. These coupling effects are not dominant, however, and may be neglected in actual practice.

Abstract: A method (1400) of enabling automatic frequency control (AFC) concurrent with time alignment of information in a communication device includes a first step (1402) of providing a data stream to an AFC. A second step (1404) includes applying multiple frequency offsets to the data stream. The offsets are separated from each other by about ±2&pgr;/2m radians with m being the number of bits per symbol in the modulation system. A third step (1406) includes correlating each frequency offset signal with a predetermined symbol sequence until correlation is found. A fourth step (1408) includes coupling the correct data stream of the branch with the found correlation to an AFC logic circuit indicating AFC lock. A fifth step (1410) includes simultaneously supplying the correct data stream to the communication device along with the fourth step (1408) such that time alignment can take place concurrently with AFC in the communication device.

Abstract: The invention relates to a radio receiver which receives reception waves modulated with a frame being a sequence of slots and reproduces transmission information that is distributed to the slots. An object of the invention is to increase the reliability of channel inference and improve the transmission quality without substantially altering a basic configuration. A radio receiver of the invention performs quasi-synchronous detection on reception waves modulated with a frame; determines an error in a sequence of first vectors and a sequence of second vectors as an average of deviations of particular symbol positions to be indicated by the sequence of first vectors indicating a sequence of words included in each slot in a signal space, and the sequence of second vectors indicating known information included in the slots; and compensates for the error in the signal space.

Abstract: Forward and Reverse Channel Automatic Repeat reQuest (ARQ) communication is described in which a Forward Channel Automatic Repeat reQuest (ARQ) session between a first unit and a second unit is performed, in which a command is send to the second unit to start a forward channel ARQ session, where the command includes a message length field specifying the length of an ARQ message to be sent by the first unit to the second unit. The second unit may refuse the command because of the length of the ARQ message.

Abstract: A method is provided for transmitting control information in a digital audio broadcasting system. The method comprises the steps of transmitting a plurality of control bits in each of a plurality of control frames, wherein a first sequence of the control bits represents a transmission mode, and a second sequence of the control bits represents a control data synchronization word. The plurality of control bits can further include a third sequence of bits representative of an interleaver synchronization word. A method performed in a radio receiver for determining transmission mode and synchronization for a digital audio broadcasting signal is also provided. The method comprises the steps of receiving a plurality of interleaver frames containing digital information, wherein each of the interleaver frames includes a plurality of control frames.

Abstract: An apparatus, such as a modem or other component within a spread spectrum communication system, is described that introduces one or more “entropy” bits into a data stream to ensure that other components of the communication system readily detect data frame misalignment. In particular, an entropy bit is introduced within each frame to help ensure that the other components generate parity errors when not properly synchronized with the framing of the data stream. The entropy bits have values that change relatively frequently, and are unrelated to the other data bits of the frames. The entropy bit may, for example, be randomly or pseudo-randomly generated.

Abstract: A digital front-end for a wireless communication system incorporates gain control, signal detection, frame synchronization and carrier frequency offset (CFO) estimation and correction features configured for use with multiple receive antennas. The digital front-end may be applied to a wireless communication system in which transmitted signals carry a repeated signal pattern, such as orthogonal frequency division multiplexing (OFDM) systems. An example of a repeated signal pattern is the preamble of a signal transmitted according to the IEEE 802.11a wireless local area network (WLAN) standard. The signal detection, frame synchronization, and CFO estimation techniques make use of signals received from multiple antenna paths to provide enhanced performance. The gain control feature may be configured to adjust the gain in steps. The frame synchronization technique may operate as a function of gain control, handling the input signal differently before and after gain adjustment.

Abstract: After a pseudo synchronizing information is detected and a synchronization is lost, an arithmetic operation unit adds a random number outputted from a random number generator to a frame length information calculated. The detection of a synchronizing information is again executed in a stream counter to a bit stream of a plurality of continuous transmission data, from a bit located in delay for the bit of output information being a calculation result by the arithmetic operation unit. The frame synchronous circuit thus constructed achieves a synchronization setup securely in a high speed, if a transmission data containing a pseudo synchronizing information is transmitted.

Abstract: A method for sampling a data stream (22) includes receiving a segment of the data stream containing a sequence of known data, together with a source-synchronous clock signal (20), and generating a series of trial sampling clocks (60) by applying a corresponding series of different trial delays to the received clock signal The received segment of the data stream is sampled using each of the trial sampling clocks in turn to generate sampled data. The known data are compared to the sampled data to find comparison results for each of the trial sampling clocks. Responsive to the comparison results, a final delay is set, to be applied to the received clock signal so as to generate a final sampling clock for use in sampling the data stream subsequent to the segment.

Abstract: A method for synchronizing a receiver to a stream of transmitted symbols that includes a known synchronization word. The method includes receiving a signal in which the symbols, including the synchronization word, are encoded by frequency shift keying. The signal is sampled and digitized to generate a sequence of input samples. For each of the input samples, a phase difference is determined relative to a preceding input sample in the sequence, thereby generating a sequence of differential samples corresponding respectively to the input samples. The differential samples are then matched to the synchronization word.

Abstract: The probability of frame destruction is lowered while suppressing the redundancy of the transmission data. On the transmitting side, a predetermined unique word is contained in a frame n for storing the n-th data, and header information n, frame length information and header information n−1 of the frame n−1 one frame before the frame n are subjected to error-correcting coding, contained in the frame n, and transmitted. On the receiving side, the header of the frame n is received. When the frame length information is transmitted with error, the timing is specified by detecting the unique word and header information in the next frame n+1. When the header of the frame n is not successfully decoded, the information data of the frame n is decoded by using the header information n inserted into a predetermined position of the frame n+1.

Abstract: A digital receiver fast frequency and time acquisition system (200) for accurately providing both time and frequency synchronization to an incoming data stream with minimal delay to prevent any loss of incoming digital information. The invention provides synchronization with only a single synchronization word and includes a first channel select (cs) filter (204) that filters an incoming digital signal (202). A frame synchronization detector (206) then recognizes the time synchronization word from the first filtered signal. A coarse symbol time estimator (208) is then used for coarsely adjusting the time synchronization of the digital signal from the frame synchronization detector (206) and a fine frequency estimator (210) finely adjusts the frequency of the signal from the coarse symbol time estimator (208) for providing a frequency adjusted signal. A mixer (212) then combines the incoming digital signal with the frequency adjusted signal and provides a time and frequency compensated digital signal.

Abstract: A reception synchronization circuit for receiving a unique word transmitted in a predetermined digital pattern. A detection circuit detects the reception electric field intensity as received power. A UW correlation judgment circuit detects the unique word (hereinafter referred to as “UW”) and takes a correlation between the unique word thus detected and a predetermined digital pattern. A memory stores two or more threshold values for the movement average. After the two or more threshold values and the movement average are compared with each other, the correlation is taken by the UW correlation judgment circuit when the movement average is larger than the minimum values of the two or more threshold values.

Abstract: In coded representation of audio, video and system bitstreams, it is common to insert start codes to facilitate synchronization points. The start codes are usually unique patterns that cannot be duplicated within the bitstream. In the decoding process it is necessary to detect these start codes in order to begin the decoding of the bitstream in a synchronized way. In typical cases, it is normal for the start code to be byte aligned and have the first few bytes comprising of the same pattern. The present invention is a method and apparatus that exploit this feature to reduce the number of comparisons required. A specific order is used in comparing the input bitstream to the start code pattern. Using this order the decoder only need to compare a subset of the bytes during the start code detection process.

Abstract: A phase synchronizer operative to establish synchronization with the phase of a received codeword is disclosed herein. The phase synchronizer includes an input shift register for receiving a sequence of bits containing the codeword. The phase synchronizer includes a first syndrome computing module, operatively coupled to the input shift register, for computing first syndromes relating to a first potential phase of the codeword. A first error detection module determines, based upon the first syndromes, a first number of errors associated with the first potential phase of the codeword. A second syndrome computing module, operatively coupled to the input shift register, computes second syndromes relating to a second potential phase of the codeword. The second syndrome computing module provides the second syndromes to a second error detection module, which determines a second number of errors associated with the second potential phase of the codeword.

Abstract: Systems and methods for locating a known multi-symbol syncword in a received signal are disclosed, wherein a potential syncword is located in a first batch of samples of the received signal which has a correlation energy with the known syncword which exceeds a first detection threshold. A correlation energy with the known syncword for a group of samples in a second batch of samples of the received signal is determined, where the group of samples in the second batch of samples are selected based on the location of the potential syncword within the first batch of samples. The correlation energy associated with the group of samples in the second batch of samples is compared with a second detection threshold that is higher than the first detection threshold. The location of the known syncword may be identified based upon the comparison of the correlation energy associated with the group of samples in the second batch of samples with the second detection threshold.

Abstract: The invention relates to a method for generating a serial bitstream comprising information for synchronizing the serial bitstream internally and/or to another serial bitstream and/or for determining the position in the serial bitstream wherein a fixed code pattern is embedded in the serial bitstream. In order to retrieve a synchronization information or to determine the position in the serial bitstream very fast after the start of reading the serial bitstream and at any time during reading the serial bitstream it is provided according to the invention that the code pattern is periodically repeated in the serial bitstream and that any sequence of a fixed number of successive bits of the code pattern forms a unique code word allowing for synchronization and/or position determination, even under the occurrence of bit errors.

Abstract: A method and apparatus for synchronization of an audio/visual bitstream is transmitted by an encoder and received by a decoder by employing duplication or elimination of audio samples and video pixels. The invention enables clock synchronization between the encoder and a decoder with an unregulated clock oscillator so as to control the data reader by skipping ahead (eliminating a data element) or to pause (duplicating a data element) depending on whether the encoder clock is faster or slower than the decoder clock.

Abstract: A TDMA radio communication method including the steps of: providing a latter part of each of super frames with an assignment information notification period which is preceded by an assignment processing period, and providing a remaining part of the each of the super frame with an assignment request collecting period; transmitting, from a terminal station to a base station, assignment request information using a plurality of frames included in the assignment request collecting period; transmitting, from the base station to the terminal station, frame structure information and assignment information over a plurality of frames included in the assignment information notification period; and carrying out, in the base station, channel assignment of a radio channel, changes of the frame structure and of the channel assignment in response to timings of the super frames.

Abstract: A discrete multitone modulation transmission system is described in which frame synchronization is monitored at the receiver by correlating frequency domain complex amplitudes of a synchronizing frame with a stored synchronizing pattern. If the correlation result falls below a threshold, indicating a loss of frame synchronization, a plurality of correlations are performed, in each case using the stored complex amplitudes of the synchronizing frame multiplied by a respective complex value representing a respective complex derotation corresponding to a respective possible time shift of the synchronizing frame. The best correlation result, if it exceeds another threshold, indicates a time shift for restoring frame synchronization, this being possible before the next synchronizing frame is received.

Abstract: A data file (22) having a plurality of frames is received, with each frame having a syncword. A data string (52) including a plurality of potential syncwords (54) is identified in the data file (22). One of the potential syncwords (54) is randomly selected. A subsequent potential syncword address is determined based on the selected potential syncword (54). Whether a subsequent potential syncword exists at the subsequent potential syncword address is determined. The data file (22) is decoded based on the subsequent potential syncword in response to the subsequent potential syncword existing at the subsequent potential syncword address.

Abstract: A method is disclosed for receiving a transmitted signal in a communication system employing CDMA techniques wherein the transmitted signal includes a plurality of short codes, each of which is transmitted repetitively over a fixed period of time and where the received signal has CW interference in addition to the transmitted signal. The method includes using a Sequential Ratio Probability Test (SPRT) for detecting the presence of the short code in a plurality of time phases of the received signal by calculating a likelihood ratio for each phase. A likelihood ratio is a comparison of the signal's Probability Distribution Function (PDF) with a background noise PDF. The background noise PDF is calculated by combining in the RAKE the current short code with the input signal.

Abstract: In a coding system wherein an error correction/detection coding is combined with a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part for coding an input multiplexed code string to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part for inserting synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in a code string, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string to assemble an output code string.

Abstract: A communication system having a framing pattern to frame data to be transmitted to a phone line is provided. The data may be framed on one side of an isolation barrier and a clock signal may be extracted from the framed data stream on the other side of the barrier. The data to be framed is provided from an output of a delta-sigma modulator and the framing pattern utilized is a pattern that is unlikely to match the data stream output of the modulator. Thus, an erroneous detection of the framing pattern is unlikely to occur. The framing pattern is chosen to correspond to the expected modulator output for a full scale input signal that is at a frequency higher than the maximum actual frequency of the input data provided to the modulator.

Abstract: The present invention provides a synchronizing data protocol comprising one or more serial input-output (SIO) control word(s) and data passed across a high voltage interface, to allow the elimination of a frame synchronization signal (and corresponding AC coupling capacitors). The present invention has particular applicability to, e.g., time division multiplexed (TDM) data, serial data communication devices, or synchronous serial communication interfaces in general, and to the communication between a controller and a codec in an audio codec device in accordance with the AC '97 Specification, i.e., the AC Link. The synchronizing data protocol is implemented over a transmit data signal line to provide occasional synchronization (i.e., not frame-by-frame synchronization) between the two communicating devices. The master device includes a preamble insertion module to insert a predetermined preamble code word into the transmitted data stream.

Abstract: A frequency offset synchronizer is provided which includes an initial timing estimator, and a combined frequency offset and refined timing estimator. The initial timing estimator determines a rough timing value from input data samples and a reference synchronization word. The combined frequency offset and refined timing estimator operates in the close vicinity of the rough timing estimate and determines the frequency offset and synchronization timing from the input data samples and the reference synchronization word.

Abstract: A system includes a unique word correlator module which correlates a unique word field in a burst of a time division multiple access (TDMA) signal against a predefined marker sequence. Automatic timing control circuitry is coupled to the unique word correlator module. The automatic timing control circuitry derives a number of errors that are allowable during correlation of the unique word field.

Abstract: A digital data transmission system for transmitting digital data, a frame pulse signal, and a clock using a required minimum number of signal lines and with a simple circuit structure is provided. A signal separation circuit (46) that receives a multiple clock (CKFP) which is a frame pulse signal (FP) multiplexed with a clock (CK) includes a clock recovery circuit (47) for reproducing a recovered clock (RCK) by synchronization with the multiple clock (CKFP) using a synchronization loop, and a frame pulse signal separation circuit (48) for separating a recovered frame pulse signal (RFP) from the multiple clock (CKFP) on the basis of the recovered clock (RCK).

Abstract: A signal synchronism detecting circuit comprises a receiving circuit receiving a serial data including data bit groups each composed of a predetermined number of continuing bits and delimiter bit groups each composed of a predetermined number of continuing bits for delimiting the data bit groups from one another, a detecting circuit for obtaining an exclusive OR between continuing bits of the received serial data, so as to detect the delimiter bit group, and a serial-to-parallel converting circuit for serial-to-parallel converting the received serial data on the basis of the result of the detection of the delimiter bit group by the detecting circuit.

Abstract: The invention relates to a synchronism judgment apparatus for judging establishment of synchronization with a frame received as a sequence of consecutive slots to which sync patterns are dispersively distributed in a form commensurate with the receiving mode according to a standard suitable for one of a plurality of receiving modes, as well as to a communication system where such a synchronism judgment apparatus is employed. The synchronism judgment apparatus of the invention enables judgement of establishment of synchronization with accuracy compared to a conventional example as long as the above standard is reliably given or identified. Therefore, in a communication system to which the invention is applied, it is possible to maintain the transmission quality and the service quality high and flexibly adapt to a variety of communication services and transmission rates, and the transmission information quantity that may vary to a large extent.

Abstract: Control information is processed in synchronism with audio and video data according to a protocol such as RTP (Real-time Transfer Protocol). In one embodiment, a payload handler receives incoming data packets and forwards them to either a data control filter or an audio packet handler. The data control filter determines whether the data payload contains video data or control information and forwards video data to a video data packet handler and data control information to a data handler. The data control information can include an action identifier field (e.g., containing a “display” command) and a data object field (e.g., identifying a file location in a memory) so that the data control filter can display the identified file with the presentation of the other video and audio data.

Abstract: A method for analyzing the channel using the preceding slot synchronization sequence is provided. The method of the invention is for operating a receiver receiving a signal frame in a dynamic channel wherein the signal frame includes a plurality of slots, each including a plurality of data bits. Each of the slots further includes a synchronization sequence wherein at least a predetermined one of the slots is assigned for the receiver. The preceding slot following the receiver assigned slot includes a varying synchronization sequence which is selected from a group of predetermined synchronization sequences postulates. The method includes the steps of calculating from the preceding slot synchronization sequence an estimated taps value for each of the synchronization sequence postulates, calculating from the preceding step synchronization sequence a log likelihood metric value C(y,h) for each of the synchronization sequence postulates and selecting the synchronization word postulate having the best metric value.

Abstract: A synchronization detector has three registers to memorize individual patterns of three successive frames. A decoder produces a frame location signal on the basis of the individual patterns. A pointer circuit counts the number of the frame location signal to produce a pointer signal. The decoder produces a count-up signal when it can decode the individual patterns. The decoder produces a reset signal when it can not decode the individual patterns. A counter counts the count-up signal and is reset by the reset signal. A register holds a predetermined value. A comparator compares the count value of the counter with the predetermined value. The comparator produces a comparing order signal when the predetermined value is less than the count value. A comparing circuit compares the frame location signal with the pointer signal. If the frame location signal is not equal to the pointer signal, it happens that an optical head skips a few frames or slips to a next truck.

Abstract: A slot receiving synchronous circuit includes a temporary storage register for temporarily storing receiving slot data having an m-bit fixed length, where m is an integer, a detector for detecting whether the m-bit receiving slot data stored in the temporary storage register has a predetermined pattern, a slot counter circuit, initialized by the detection signal outputted by the detector, for synchronizing the receiving slot data, and a bit counter circuit for counting bit clocks inputted thereto in synchronization with each bit input of the receiving slot data, to provide a count value, and for supplying signals, when the count value reaches a predetermined value, to the slot counter circuit such that the slot counter circuit counts the signals. The slot counter circuit and the bit counter circuit are set to their initial values, respectively, by the detection signal.

Abstract: A coherent detecting circuit accurately estimates a propagation characteristic of a propagation path without increasing the number of pilot symbols when a fading frequency is high so that an error rate of received data is decreased. At least one pilot symbol is received from a transmitter. The pilot symbol may be provided in a data frame of data symbols, or transmitted through a channel different from a channel of the data symbols. A first estimated value of the propagation characteristic of a propagation path is estimated by using the pilot symbol. The data symbols are tentatively determined based on an estimated value of the propagation path. A second estimated value of the propagation characteristic is estimated by using the pilot symbol and at lease one of the tentatively determined data symbols. The data symbols are finally determined based on the second estimated value of the propagation characteristic.

Abstract: An initial frame timing acquisition unit includes an initial timing estimator, and a combined frequency offset and refined timing estimator. The initial timing estimator determines a rough timing value from input data samples and a reference synchronization word. The combined frequency offset and refined timing estimator operates in the close vicinity of the rough timing estimate and determines the frequency offset and synchronization timing from the input data samples and the reference synchronization word.

Abstract: A device and method for regulating a sampling rate in a digital data transfer system includes transmitting a synchronizing word used for receiver-side regulation of the sampling rate at regular time intervals. The received signal is filtered by a rate-regulating criterion filter and is simultaneously detected to recognize the synchronizing word. The initial value of the rate-regulating criterion filter controls an adjusting logic for the sampling rate once the to synchronizing word is recognized. A rate is formed for the initial value of the rate-regulating criterion filter and the rate undergoes high pass filtering before it is fed to the adjusting logic. An apparatus for controlling the sampling includes a clock control criterion filter, an adjustment logic device, a switch, an apparatus identifying the synchronization word, a magnitude formation circuit, and a high-pass filter. The formation circuit and the high-pass filter are disposed between the criterion filter and the logic device.

Abstract: A synchronization equipment performs correlation processing between a first known pattern included in a received signal and a second known pattern, and detects reception timing of the received signal. A correlation value computing portion computes a correlation value between the first known pattern and the second known pattern at every reception time. A reception timing detection portion compares the computed related value with a predetermined threshold value, determines the reception time when the correlation value becomes larger than the threshold value to be the reception timing of a received signal, and, after this determination, suspends the comparison between the correlation value and the threshold value, and holds the reception time determined to be the reception timing.

Abstract: An apparatus for receiving digital information signals, including a signal receiving portion for receiving a digital information signal, and for transmitting digital data composed of a series of transmission frames each divided into a plurality of segmental periods called symbols and including a reference Symbol for synchronization, a reference Symbol data extracting portion for extracting data transmitted through a reference Symbol from each of transmission frames of digital data obtained from the received digital information signal, a frequency offset detecting portion for obtaining a first frequency offset detection output based on the received digital information signal a strength of, data transmitted through the, reference Symbol at every transmission frame and obtaining also a second frequency offset detection output based on with the received digital information signal and a strength of specific data included in data transmitted in each of the plurality of Symbols, and a frequency synchronizing control

Abstract: A road side communication equipment is provided crossing over lanes of an expressway, so that a communication processing for toll collection is executed between the road side equipment and an on-board equipment passing a communication area. The road side equipment sends signals using a 32-bit synchronizing signal for the start slot of each frame and a 16-bit synchronizing signal for subsequent slots of the frame. The on-board equipment receives this to perform signal receiving processing. The received communication signals are then digital-demodulated and entered to a shift register, so that the bit pattern is compared in two comparators to detect the synchronizing signal. According to the output from AND circuits, the synchronizing signal is distinguished from the synchronizing signal to determine the received data and receive subsequent data.