Abstract: A method of correlating a signal to a synchronization pattern is disclosed. The signal has a waveform with frequency and phase angle components that may be varied, at each repeated signal pulse, to communicate a change in a bit pattern of the signal. A synchronization pattern is generated using knowledge of phase rotation direction due to two consecutive bits in a synchronization key. The signal is compared with the synchronization pattern. It is determined whether the comparison of the signal and the synchronization pattern indicate a correlation between the signal and the synchronization pattern.

Abstract: The repetitive structure of a preamble signal is exploited to enhance timing synchronization performance and frame start detection performance under adverse channel conditions. Received values are cross-correlated in time against a known noise-free version of the preamble. The presence of peaks in the cross-correlation output indicates presence of a frame. The peak locations provide symbol timing. Further cross-correlation processing and/or non-linear processing can be used to enhance the signal to noise ratio of the peaks.

Abstract: A receiver architecture for receiving an FSK signal having a predetermined number of modulation levels includes a selectivity filter (206) for selectively passing a wanted channel and rejecting unwanted channels. The selectivity filter has a filter bandwidth of about one-half the bandwidth of a pre-modulation filter in a transmitter sending the FSK signal. A discriminator (208) is coupled to the selectivity filter for demodulating the signal. A symbol recovery processor (210) is coupled to the discriminator for recovering the symbols through a maximum likelihood sequence estimation (MLSE) technique utilizing N states for each symbol time, wherein N equals the predetermined number of modulation levels, and wherein templates used in the MLSE for symbol transitions are optimized with a bandwidth substantially less than the bandwidth of the pre-modulation filter.

Abstract: A communications apparatus and method use tapped delay lines as multiplexers and demultiplexers. In one embodiment, a receiver (100) uses a tapped delay line (110) as a demultiplexer to acquire a burst communication at very high data rates in the range of 2.5 to 80 Gbps with low preamble overhead. A sliding window correlator (114) continually samples the delay line (110) to determine when a PN encoded word is contained therein. The transmission frequency is pre-acquired before any data is present through the use of a ring oscillator frequency calibration loop (130) that is imbedded within the tapped delay line (110).

Abstract: A method and device are disclosed for the detection and synchronization of a signal in a frequency-hopping system. The method has a step, for each frequency F(1) . . . F(M), of selecting the K samples corresponding to the greatest values of the signal, and their positions. For a given position, the M greatest values are combined which are selected from among K samples on each frequency having the given position. The greatest combined value is kept and the corresponding position. The greatest combined value is compared with a threshold value, and if the greatest combined value is greater than this threshold value, then the detection of the signal is declared.

Abstract: The invention relates to power control of a cellular mobile communication system using TPC, and a power control circuit in a base station set and a radio terminal is equipped with a synchronism detecting unit for detecting synchronism data indicating synchronism establishment from radio data every frame; a synchronism/asynchronism judging unit for judging synchronism/asynchronism based on the synchronism data, an execution/unexecution judging unit for judging execution/unexecution of TPC based on the synchronism data, TPC bits extracting unit for detecting TPC bits contained in the radio data, and a selection control unit for selecting execution/unexecution of transmission power control using the TPC bits based on the judged result and the judged result. 3-Stage control of suspension, execution and unexecution of TPC becomes feasible every frame on the basis of quality, more stable quality can be secured, and increase in the quantity of channel interference can be prevented.

Abstract: A method and apparatus for processing a data signal for transmission to a remote device transmits at least two synchronized copies of the data signal, in optical form, in different directions. To that end, the data signal first is synchronized to a clock signal to produce a composite signal. The composite signal then is converted to an optical signal, which is referred to as an “outgoing signal.” A plurality of copies of the outgoing signal then are transmitted. At least two copies of the outgoing signal are transmitted in different directions.

Abstract: Synchronization and impairment estimations can be performed jointly, thereby saving valuable time for decoding of the received packet. An initial synchronization in a TDMA system can be performed. Using this synchronization, the frequency offset choices and timing offset choices can be advantageously bounded within predetermined ranges. At this point, an algorithm can find the minimum error that gives the best frequency offset choice and timing offset choice combination over their respective ranges, together with the estimates of the signal magnitude and phase and at least one of a DC offset magnitude and phase, and a spur magnitude and phase.

Abstract: Disclosed is a method and apparatus for synchronizing data in a number of separate integrated circuits. In one embodiment, the apparatus includes a first integrated circuit configured to receive first data, and a second integrated circuit coupled to the first integrated circuit configured to receive second data. The second integrated circuit is separate from the first integrated circuit. The second integrated circuit is further configured to synchronize the second data with the first data. In another embodiment, the apparatus includes a first integrated circuit configured to receive first data, and a second integrated circuit coupled to the first integrated circuit configured to receive second data. The second integrated circuit is separate from the first integrated circuit. The second integrated circuit is further configured to detect when the second data is out of synchronization with the first data.

Abstract: A method of timing in a multi-cell system requiring synchronization of frames in transmission is provided. Transceivers of a wired data interface between a central controller and multiple base stations are synchronized to a frame timing clock up to a difference in propagation delays between the central controller and multiple base stations. The propagation delays are considered as constants, are measured, and are stored in each base station. A unique word is regularly inserted in the data transmitted by the central controller, at a fixed interval. When this unique word is detected by the base station within a fixed period of the frame timing clock, a frame signal delay is initiated at the next rising edge of each frame timing clock. This frame signal delay is equal to the period of the frame timing clock minus the propagation delay. At the end of the frame delay, the frame data is transmitted, and all frames are simultaneously transmitted from different base stations.

Abstract: A symbol synchronization device that enables effective symbol synchronization establishment and synchronization holding for an arbitrary spread code sequence.

Abstract: Provided is a frame synchronization method for synchronizing frames with pilot blocks added thereto based on differential correlation information in a satellite communication system. The method can acquire a highly reliable frame synchronization estimation value by achieving a multi-step threshold value test using pilot blocks after a correlation analysis and a threshold test based on a sync signal in order to resolve the problem of a low signal-to-noise ratio and a large frequency error and acquire highly reliable frame synchronization performance, and can overcome distortion of a correlation analysis value caused by the frequency error by analyzing correlation based on differential information. The method includes the steps of: a) performing correlation analysis and a threshold test by using a sync word; and b) performing a multi-step correlation value test by using the pilot blocks added to the frames prior to the sync word.

Abstract: In a DSRC communications controller equipped with a plurality of reception means for DSRC communications according to the invention, a reception reservation storage section 104 comprises means for detecting a communications frame start signal (unique word 1) of DSRC communications by using reception means not engaged in communications among the plurality of reception means and means for storing the control information of DSRC communications where the communications frame start signal is detected. On completion of DSRC communications by way of reception means, a controller uses the control information stored in the reception reservation storage section to establish next communications. This allows continuous reception of information from a plurality of roadside machines to be made efficiently even in case a plurality of communications areas overlap one another.

Abstract: In a data processor, a pickup head reads the data from a memory medium. Such data transferred in a plurality of parallel bits in synchronization with the clock signal to a controller unit from a read channel unit. The controller unit detects the predetermined mark for detecting synchronization included in the data in order to establish the synchronization of a series of data to be received from the read channel unit in order to demodulate the data other than the predetermined mark for detecting synchronization. The mark detecting unit in the controller unit detects the predetermined mark for detecting synchronization from the parallel data received with the shift register.

Abstract: A method for transmitting synchronization information with data, which data corresponds to a sequence of samples representative of a signal, includes detecting the occurrence of two consecutive equivalent samples and inserting a synchronization pattern for the second-occurring sample prior to transmission. At a receiving end, the incoming signal is monitored to detect the presence of the sync pattern and hold the value of the receiver output at the value of the immediately previous received sample. In this manner, the signal is reconstructed without degradation, and byte synchronization information is sent without any bandwidth loss.

Abstract: A method for generating a preamble sequence in an OFDM (Orthogonal Frequency Division Multiplexing) communication system that uses A sub-carriers in a frequency domain and uses N Tx (Transmission) antennas, includes the steps of: generating N sequences, each having a length of ‘B/N’, by dividing B sub-carriers from among the A sub-carriers by the ‘N’ indicative of the number of the Tx antennas; and mapping, for each of the N sequences, individual components of the sequence to the B/N sub-carriers from among the A sub-carriers on a one by one basis in order to assign the components of the sequence to the B/N sub-carriers, and assigning null data to remaining sub-carriers other than the B/N sub-carriers from among the A-sub-carriers, such that a preamble sequence of a corresponding Tx antenna is generated.

Abstract: The invention relates to an apparatus and a method for ascertaining and correcting the optimum sampling time for an oversampled input bit stream. This involves feeding the data bit blanked with the current sampling phase into the comparative sequence and using the data bit to ascertain a new, corrected sampling phase. This decision-based approach enables the sampling phase to be continuously corrected.

Abstract: A method and apparatus implementing the method, of selecting a bit load b for a channel in a carrier system. The carrier system encodes data based on a constellation of points. Each point represents a tuple of data. The constellation has a self-similarity property. The bit load for the channel is selected based on the self-similarity property of the constellation. In an alternate embodiment, the method and apparatus are used to determine the bit load of the sub-channels in a multi-carrier system.

Abstract: A master unit sends a start signal to a slave unit. When receiving the start signal from the master unit, the slave unit sends, to the master unit, a synchronization field that is a data train (pulse signal) indicative of a transfer clock with which the slave unit is able to perform transferring and receiving operations. The master unit sends, to the slave unit, command data in accordance with the transfer clock indicated by the synchronization field sent from the slave unit. In response to the command data sent from the master unit, the slave unit sends, to the master unit, response data in accordance with the transfer clock indicated by the synchronization field. Thus, in a communication system employing a serial data transferring apparatus of the present invention, the master unit establishes the synchronization for the data transfer, while the slave unit is free from a burden of establishing the synchronization for the data transfer.

Abstract: An ultra-wide band (UWB) radio frequency (RF) receiving device (205) includes a first receiver (305) that receives UWB RF signals, a second receiver (315) that receives an external cue, and a processing unit (330). The second receiver (315) receives an external cue that includes one of a television blanking signal, a zero-crossing of a FM radio transmission, a paging system signal, a zero-crossing of an analog voice transmission, a zero-crossing of an analog video transmission, a cellular telephony control channel signal, a cellular telephony traffic channel signal, a digital sub-band for an AM or FM radio station signal, a digital or analog signal in a short-wave-radio transmission, a digital television signal, a digital or analog signal in a land mobile radio transmission, a radio-navigation signal, a radar signal, a satellite signal, an acoustic event or signal, a magnetic event or signal, or an optical event or signal.

Abstract: A system receives input data frames that are configured according to a SONET or an SDH standard. The input data is converted to parallel data. The system provides groups of bits along parallel signal lines. In each group of bits, N contiguous bits in the group form a complete word of input data. The system identifies the boundary between complete words in the input data by comparing subsets of the bits to predefined framing patterns. The system then aligns the input data based on the location of each word using the boundary information. The output data of the system includes data that is word aligned. The system can also detect boundaries between the frames.

Abstract: The performance of a serial data transceiver in a programmable logic device may be determined by applying a stress sequence of sequential data to a receiver of the transceiver, comparing the received data to reference data and determining the number of errors.

Abstract: A frequency synthesizer and a method using a first seed word and a variable clock rate derived from a second seed word for synthesizing a signal frequency. An accumulator accumulates the first seed word at the variable clock rate with a remainder word for updating a reference word at the variable clock rate. The reference word has a most significant bit (MSB) and less significant bits (LSB)s. The remainder word corresponds to the LSBs at overflows of the MSB. A tracking filter filters the MSB for providing a filtered output signal having an output frequency derived from the first seed word and the variable clock rate. The variable clock rate is derived by direct synthesis from the second seed word and single sideband frequency upconversion. The tracking filter can be a phase lock loop with frequency upconversion.

Abstract: A frequency synthesizer and a method for synthesizing a microwave output signal frequency. The synthesizer uses a reference signal having a variable frequency and accumulation in feedback of a phase locked loop for synthesizing a microwave output frequency. The feedback accumulation rate is derived from a first seed word and the variable reference frequency is derived from a second seed word. A spur suppressor having arithmetic frequency conversions reduces the levels of in-band spurious signals of the variable reference frequency signal in order to reduce the spurious signal levels in the output signal.

Abstract: Disclosed is a parallel distributed sample descrambling (DSS) apparatus and a method that lowers a clock speed of 622 MHz into ? speed (77.76 MHz) and operates a serial descrambling processing in unit of bit by converting the processing into a parallel descrambling processing in unit of byte, power consumption can thus be reduced and a sufficient timing margin can be secured. The parallel DSS apparatus includes a serial-parallel conversion unit for converting receiving data into parallel data (D[7:0]) and generating a counter signal, a header error check (hereinafter, as HEC) generation unit for generating HEC data of the receiving data by CRC calculation, and abstracting upper two bits of the HEC data, and a descrambling processing unit for performing parallel descrambling of byte module by receiving output signals of the serial-parallel conversion unit and the HEC generation unit.

Abstract: A transmission control section 101 temporarily stores a transmission signal, outputs the stored transmission signal to a coding section 102 and outputs transmission timing information to a counter section 107. A preamble insertion section 104 inserts AGC preambles corresponding to the number set by a preamble number control section 110 into the transmission signal. The preamble number control section 110 compares a transmission time interval input from a subtraction section 109 with a threshold, decides to insert ten AGC preambles into the transmission signal when the transmission time interval is equal to or greater than the threshold and decides to insert five AGC preambles into the transmission signal when the transmission time interval is smaller than the threshold. By so doing, it is possible to make the transmission efficiency compatible with the error rate characteristic.

Abstract: A system and method for reordering tones of a DMT signal within a communication system is described. Cross tone correlated noise in a received signal is identified and rearranged such that tones with correlated noise are spread out throughout the received signal before being processed by a decoder such as, Viterbi decoder. In an embodiment, two tones with the most correlated noise are placed at each end of the sequence of tones presented to the Viterbi decoder. In some embodiment, the tones with correlated noise can be spread such that two adjacent tones with correlated noise have a minimum distance of at least three tones between them at the input to the Viterbi decoder. In other embodiment, tones in the received signal can be processed in various kinds of interleavers for reordering according to the interleaver scheme.

Abstract: Systems and modules for use in trellis-based decoding of encoded sets of data bits. A memory system has multiple arrays for storing an index for each one of multiple states. With each array element being associated with a state through which a decoding path may pass through, the contents of each array element is an index which points to an immediately preceding state. This immediately preceding state is represented by another array element in another array. Each array is populated with array element entries as encoded data set are received by a separate decoder which generates the indices. For every given number of arrays in a group, a trace-back process traces back the path followed by an encoding procedure for encoding the encoded set. By tracing back this path through the various arrays, the original unencoded set of data bits can be found.

Abstract: The invention is a method and apparatus for ensuring synchronization for digital communication between a transmitting and a receiving device, particularly when the clock and/or frame synchronization is sourced from a different location than the transmit data.

Abstract: A receiving apparatus (1) for receiving signals in a digital telecommunication system and a synchronizing method for synchronizing the receiving apparatus (1). The receiving apparatus (1) includes a receiver (2, 3) for receiving a reference symbol having at least two repetition patterns. One of the repetition patterns is phase-shifted in relation to the other. The receiving apparatus (1) is synchronized in the digital telecommunication system using the received reference symbol. The synchronization includes a cross correlation of at least one of the two repetition patterns within a cross correlation window having a predetermined length. In this manner, the performance and the accuracy of a cross correlation peak detection can be enhanced for improved synchronization.

Abstract: A sample clock extracting circuit comprises including a number-of-change point memory, a number-of-change point updating circuit and an output clock phase determining circuit. The number-of-change point memory stores a number-of-change-point information set every N types of clock phases each having a frequency equivalent to N times a symbol transmission rate of an input baseband signal. The number-of-change point updating circuit updates the number-of-change point information stored in the number-of-change point memory about a clock phase related to timing thereof when a rising change point or a falling change point occurs in the baseband signal. The output clock phase determining circuit determines a clock phase directly or indirectly indicative of a sample clock phase for the baseband signal based on the number-of-change-point information stored in the number-of-change point memory.

Abstract: A method for the reception of a signal comprising the following steps: 1) on the detection or reception of an edge in the received signal, a counting cycle Nc is activated, 2) when the value of Nc is equal to a number M of beeps of a generation clock Hg, a leading edge of the reception clock signal is sent and a new counting cycle Nc is activated, 3) when this new value of Nc is equal to a number M of beeps of a generation clock Hg, the clock Hr is made to pass to zero, and simultaneously 3.1) in the event of reception of an edge in the received signal, a new clock signal edge is sent when Nc=M, 3.2) in the event of non-reception in the received signal, a new clock signal edge offset by a value of 1(M+1) is sent when Nc=M, 4) the steps 1) and 2) are executed so long as the header is not detected, 5) upon the detection of a header, a Header Found signal is sent, the steps 1), 2), 3) and 3.1) are executed and this Header Found signal is transmitted at a processing step.

Abstract: A sampling unit that sequentially samples a received signal. A plurality of demodulation processing units set in advance with frequency correction values of mutually different sizes, and that correct frequencies of the sampled signals according to the frequency correction values, demodulate the sampled signals after the frequency correction, and output decision values and reliability information of the received signal, and detect known synchronization words that have been inserted into the received signal from the decision value. A decision value selecting unit selects one final decision value from a plurality of decision values based on a plurality of pieces of reliability information that have been output from the demodulation processing units and a result of the detection of the synchronization word. And, a frequency error detecting unit estimates a frequency error of the received signal based on a frequency correction value of the demodulation processing unit corresponding to the final decision value.

Abstract: An input signal DT contains a segment synchronization signal compliant with the ATSC standard. A clock multiplication section 111 multiplies a clock CK. A switchable sampling section 112 selects a sample point from among a plurality of timing points that are defined by the multiplied clock, and samples the input signal DT at the selected sample point. Moreover, the switchable sampling section 112 switches sample points from one to another in a synchronization-unestablished state. Once the segment synchronization is established, a synchronization detection device may maintain a synchronization-established state until the field synchronization detection fails, or the synchronization detection device may output a synchronization detection signal after shifting it in the time direction based on a bit error rate RT of the input signal.

Abstract: A correlation between a received signal and a sync word signal is calculated. A window signal having a time span which is equal to an equalization range for an adaptive equalizer is defined. A power sum of the correlation output signal in each of window signals #1, #2, #3, . . . are calculated by sequentially shifting the window signal in the time domain, and a rising edge of the particular window signal whose power sum maximum defines a symbol sync timing.

Abstract: Cell search synchronization in spread spectrum communications systems using primary and second synchronization codes with symbol partitioning for shorter coherent combinations (despreading) which are combined non-coherently, and Fourier transform analysis automatically adjusts for phase rotation of the despread sub-symbols.

Abstract: A phase synchronizer may operate, for example, to establish synchronization with a phase of a received codeword. The phase synchronizer may include, for example, an input shift register, a first syndrome computing module, a first error detection module, a second syndrome computing module, a second error detection module and a comparator arrangement. The first syndrome computing module may compute syndromes relating to a first potential phase of the codeword. The first error detection module may determine, based upon the first syndromes, a first number of errors associated with the first potential phase of the codeword. The second syndrome computing module may compute syndromes relating to a second potential phase of the codeword. The second error detection module may determine, based upon the second syndromes, a second number of errors associated with the second potential phase of the codeword.

Abstract: A data transmission process with auto-synchronised correcting code, auto-synchronised coder and decoder, corresponding transmitter and receiver. According to the invention, synchronisation management signals (HS, SS, ID) are formed and, under the control of these signals, a header is inserted before a data group and after it a correcting code. At receive end, these synchronisation management signals are reconstituted, the presence of a header is detected and any erroneous symbols are corrected. The invention also provides for an auto-synchronised coder and a decoder and for a transmitter and a receiver using them.

Abstract: A method is provided of detecting one of a set of preamble sequences in a spread signal. The method includes: (a) correlating the received spread signal with sequences of a first orthogonal Gold code (OGC) set in accordance with a first fast transform to provide a preamble signal; (b) correlating the preamble signal with the set of preamble sequences in accordance with a second fast transform to generate a set of index values; (c) forming a decision statistic based on the set of index values: and (d) selecting, as the detected one of the set of preamble sequences, a preamble sequence corresponding to the decision statistic.

Abstract: A method for selecting a modulation detector in a receiver and a receiver which includes a first and a second modulation detector, mechanisms for determining at least one cross-correlation value between the stored training sequence and at least one training sequence of the received signal, and mechanisms for selecting the detector used for the detection of a signal to be received in response to the determined at least one cross-correlation value.

Abstract: A data-demodulating method for demodulating a variable-length code (d, k; m, n; r) having a basic code length of n bits to data having a basic data length of m bits. A train of codes is received, and a sync signal having a pattern that breaks a maximum run is detected. The pattern is repeated twice continuously and the minimum run is repeated no more than six times. The first bit of the sync signal is “1” when the train of modulated codes that immediately precedes the sync signal is included in a termination table used to terminate, at a desired position, a code when less than a predetermined number of variable length codes are available.

Abstract: A method of modulating data having a basic data length of m bits, to a variable-length code (d, k; m, n; r) having a basic code length of n bits. A sync signal is added to a received train of codes after a minimum run. The sync signal has a pattern that is repeated twice continuously. The minimum run is repeated no more than six times; and the sync signal exhibits seven types of sync signal IDs, with any adjacent two bits of a sync signal ID being spaced apart by a distance of 2.

Abstract: Apparatus for modulating data having a basic data length of m bits, to a variable-length code (d, k; m, n; r) having a basic code length of n bits. A sync signal is added to a received train of codes after a minimum run. The sync signal has a pattern that is repeated twice continuously. The minimum run is repeated no more than six times; and the sync signal exhibits seven types of sync signal IDs, with any adjacent two bits of a sync signal ID being spaced apart by a distance of 2.

Abstract: A data-demodulating apparatus for demodulating a variable-length code (d, k; m, n; r) having a basic code length of n bits to data having a basic data length of m bits. A train of codes is received, and a sync signal having a pattern that breaks a maximum run is detected. The pattern is repeated twice continuously and the minimum run is repeated no more than six times. The first bit of the sync signal is “1” when the train of modulated codes that immediately precedes the sync signal is included in a termination table used to terminate, at a desired position, a code when less than a predetermined number of variable length codes are available.

Abstract: The present invention refers to a method and an apparatus for synchronizing operation at a node of a communication network. According to the invention a phase relationship between an output frame synchronization signal and an input frame synchronization signal is controlled by the adjustment of a phase difference between the output frame synchronization signal and a node synchronization signal.

Abstract: A digital receiver fast frequency and time acquisition system (200) for accurately providing both time and frequency synchronization to an incoming data stream with minimal delay to prevent any loss of incoming digital information. The invention provides synchronization with only a single synchronization word and includes a first channel select (CS) filter (204) that filters an incoming digital signal (202). A frame synchronization detector (206) then recognizes the time synchronization word from the first filtered signal. A coarse symbol time estimator (208) is then used for coarsely adjusting the time synchronization of the digital signal from the frame synchronization detector (206) and a fine frequency estimator (210) finely adjusts the frequency of the signal from the coarse symbol time estimator (208) for providing a frequency adjusted signal. A mixer (212) then combines the incoming digital signal with the frequency adjusted signal and provides a time and frequency compensated digital signal.

Abstract: A splicing system includes a splicer for seamlessly splicing togther digitally encoded data streams. In a preferred embodiment, the splicer preferably parses successive splice buffers of data stream data for a splice-out point and a splice-in point, closing an initial group of pictures GOP if needed. The preferred splicer further finds a new data stream real-time program clock reference PCR value for aligning new data stream decode/presentation, and aligns the new data stream start time. Concurrently, the splicer preferably uses a frame table to detect overflow and corrects such overflow by adding null packets, thereby delaying portions of data stream data. The splicer also preferably restores data stream encoding by deleting null packets, and thereby accelerating a portion of data stream data. In a further preferred embodiment, the splicer preferably uses a bit-clock schedule offset to delay or accelerate portions of data stream data.

Abstract: A User Equipment (UE) has a circuit that performs the acquisition for the low chip rate option of the Universal Mobile Telecommunication System (UMTS) Time Division Duplex (TDD) standard as formulated by the Third Generation Partnership Project (3GPP). The present invention implements the detection of the basic SYNC code; the determination of the midamble used and the detection of the superframe timing based on SYNC code modulation sequence. This enables reading of a full Broadcast Channel (BCH) message.

Abstract: A device, system and method for aligning data received on a plurality of data lanes in a data link are disclosed. One or more alignment vectors are generated for each of a plurality of data lanes where each alignment vector represents a location of an alignment character in an associated one of the data lanes. For each data lane, a plurality of alignment vectors may be associated with one or more alignment windows associated with the data lane. If the alignment vectors of the data lanes are associated with a common alignment window, an alignment position may be selected for each data lane.

Abstract: A system and method for detecting a synchronization (sync) signal in a communication signal are disclosed. A received communication signal is stored in a memory and portions thereof are read from the memory and monitored to detect the sync signal. When a detected sync signal is determined to be invalid, previously read portions of the received communication signal, preferably beginning at a portion of the received signal immediately after a start of the detected sync signal, are again read and monitored to detect the sync signal. Such reading and monitoring of previously read portions of a received signal provide for recovery from so-called false triggering based on invalid sync signals.