Abstract: The invention relates to synchronizing in communication systems by using a sequential correlation technique. A digital sequence known to the receiver, a so-called signature, is allocated a plurality of segments. The segments are correlated, segment for segment, in a correlator (300) which is equally as long as the segment. The segments may have the same or different bit patterns. When a first segment is received in the correlator (300) and the correlation value of this segment exceeds an associated threshold value, the segment is accepted as received and is saved in a memory (308) in response to a signal from the control unit (311). A timer (319) is set to a time point that corresponds to the length of the segments. There is then correlated a second segment whose correlation value on the signal from the timer (319) is added (304) to the value stored in the memory (308). If the sum exceeds an associated threshold value, the sum is stored in the memory (308). Detection continues in this way.

Abstract: The clock reproducing device includes a control device which generates a control signal for decreasing a clock frequency difference between a transmitter and a receiver according to a clock information difference between the transmitting clock information and reproduced clock information and a receiving interval of the transmitting clock information, thereby the clock reproducing device controls a reproduced clock frequency of a reproduced clock output device. The clock reproducing device carries out appropriate frequency control regardless of the transmitting interval of the transmitting clock information received from the transmitter.

Abstract: In a synchronizing system searching for k sub-frame patterns respectively distributed in k sub-frames in one frame of data transmitted via a transmission line where k is an integer, a frame pattern detection unit sequentially detects one of the k sub-frame patterns with a predetermined period. A control unit causes the pattern detection unit to detect an (i+1)th sub-frame pattern at the predetermined frame period after the pattern detection unit detects an ith sub-frame pattern where i=1, 2, . . . , k.

Abstract: A data clock signal for data in an incoming signal is generated by means of a clock recovery module. The incoming signal consists of a data burst having a periodic preamble followed by a data sequence. The clock recovery module comprises a first clock generator, a sampling device, a correlator, a control unit and a time registration device. The clock generator generates a clock signal having a first clock frequency which is a factor N higher than the frequency of the preamble. The sampling device samples the incoming signal at the first clock frequency. The correlator correlates the sampled signal with a predefined correlation word, the correlation between the incoming signal and the correlation word being represented as a correlation signal in the form of a series of discrete correlation signal values. The control unit detects local extreme values for the correlation signal.

Abstract: A receiver carrier synchronization apparatus and method for carrier synchronization with a received signal having a known data pattern preamble uses a "punctured" preamble for making carrier synchronization estimates thereby reducing the number of receivers required. The known data pattern preamble of the received signal is processed with a local reference signal and a differentiated replica of the known data pattern preamble to generate an error signal. The error signal is selectively sampled in the time domain in accordance with a puncture scheme, and the sampled error signal is used to generate the local reference signal in a closed loop. The received signal is processed with the local reference signal and a replica of the known data pattern preamble to generate a synchronization estimate signal.

Abstract: A method is provided for detecting a synchronization word in frames of serially transmitted data. The synchronization word consists of l synchronization bits, which are transmitted one bit per frame at a known position in each frame. The method comprises the steps of: storing each incoming bit in a memory organized as groups of words, each having at least l bits, so that each group of words contains bits from a same position in consecutive frames; rotating each group of words; comparing the group of words, at each rotation, to the synchronization word.

Abstract: The present invention discloses a method and apparatus for providing very fast message synchronization of synchronous serial data streams by reducing system reliance on complex and highly computational synchronization schemes. The benefits of the instant invention are realized by performing most of the computational effort during message design, rather than during real-time detection. The synchronization pattern preceding the data stream is constructed in accordance with predetermined rules and compared using multiple bit segment compares rather than performing comparisons bit-by-bit. The synchronization pattern is further provided with an index that is used to access a lookup table that contains information for providing true alignment of the data stream once synchronization has been detected.

Abstract: A byte aligner and frame synchronizer for 622 Mbit/s high speed data includes a clock divider, a data width extension circuit, a byte alignment controller, a byte alignment circuit, a pattern selector, a continuous pattern detector, a frame pulse generator, a frame sync detector, a frame sync loss detector, and frame sync error detector, and performs byte alignment very fast while also stabilizing frame synchronization by reinforcing an error correction function.

Abstract: A method and system for demodulating received signals in radio communication systems. Pi/4-DQPSK modulated signals can be demodulated to provide additional quality measurements and to facilitate diversity combination or selection. For example, a carrier is modulated with digital data using Pi/4-DQPSK to convey two bits of data by changing the radio carrier phase from the value at the end of the last symbol through an angle of either .+-.45 degrees or .+-.135 degrees, these four possibilities representing the bit pairs 00, 01, 11 or 10. The transitions of the radio signal are filtered in the complex (I,Q) plane to limit the spectrum. At the receiver, the received signal is downconverted, filtered and amplified using a hard-limiting intermediate frequency (IF) amplifier. The IF amplifier also produces an approximately logarithmic indication of the signal strength before limiting. The hard-limited IF signal containing phase information is fed to a direct phase digitizer.

Abstract: An offset circuit (2) detects an offset word serving as a synchronization pattern. By being triggered by the detection, main and subordinate synchronization detection circuits (5 and 6) detect the periodicity of the offset word only during a predetermined backward guard period. Both synchronization detection circuits (5 and 6) detect offset words at different timings. Therefore, if one synchronization detection circuit (5 or 6) fails in detection of synchronization, it is possible to use a detection result of the other synchronization detection circuit (5 or 6). Moreover, received data during the backward guard period is stored in a data memory (11). Therefore, it is possible to use the stored data as received data after detection of synchronization. Even after establishment of synchronization, the synchronization detection circuit (5 or 6) continuously detects the periodicity of an offset word at a timing different from an established timing.

Abstract: A wireless telecommunications system (1) includes a central terminal (10) for transmitting and receiving radio frequency signals to and from a subscriber terminal (20). A downlink communication path is established from a transmitter (200) of the central terminal (10) to a receiver (202) of the subscriber terminal (20). A downlink signal (212) is transmitted from the transmitter (200) to the receiver (202) during setup and operation of the wireless telecommunications system (1) carrying information partitioned into a plurality of frames. The downlink signal (212) includes an overhead channel (224) having a frame alignment signal (232) for each frame of information. The receiver (202) monitors the downlink signal (212) to identify the frame alignment signal (232). The downlink communication path is established when the receiver (202) identifies two successive frame alignment signals (232).

Abstract: In a receiving apparatus for radio data communications, even after a carrier is detected in a received signal, when a start-delimiter is not detected, or when a message broadcasting packet and/or a local packet for the apparatus is not detected, the supply of a clock signal to a data demodulating section for demodulating the modulated signal is stopped.

Abstract: The invention relates to a method for detecting the beginning of time messages in the signal received from a time-signal transmitter. The signal of the time-signal transmitter consists of a series of blanking intervals on a carrier signal in the seconds clock cycle in which blanking intervals of different length cause different information units to be transmitted (ZERO pulse, ONE pulse, frame pulse). A time message, comprising the information units transmitted over a period of one minute, contains the actual time information in coded form. The time message has areas/sectors with defined, constant information units and areas/sectors with variable contents that code the time information. A reference message is stored in a first area of memory that contains the defined, constant information units that are located in fixed areas/sectors. A number of successive information units corresponding to the length of a time message are stored in a second area of memory.

Abstract: A digital audio broadcasting (DAB) system includes a radio-frequency (RF) transmitter and a corresponding RF receiver that includes a frame detection circuit for providing a frame synchronization signal. The latter is used to inhibit a Reed-Solomon decoder from correcting data in any frame for which there was no synchronization.

Abstract: An apparatus and method for converting a serial data signal into a parallel data signal based on sync signals contained within the serial data signal are provided. The serial-to-parallel data conversion apparatus includes a signal input end, a true sync signal identifier for individually identifying whether the sync signals contained in the serial data signal are true sync signals having the same positions as those of original sync signals, based on predetermined sync patterns, a false sync signal removal unit for removing from the serial data signal false sync signals which are sync signals that are not identified by the true sync signal identifier as true sync signals, and a clock generator for generating a clock signal for performing serial-to-parallel conversion of the serial data signal by using the sync signals contained in the serial data signal output from the false sync signal removal unit.

Abstract: A method of fade recovery in a digital message transmission system in which data is encoded into code words, formatted into frames of a batch and transmitted in accordance with one or more transmission formats, and a synchronization code word, indicative of the transmission format, is inserted at the beginning of each batch, the method of fade recovery including energizing a receiver for a first predetermined time period and storing any signals received during the first predetermined time period, analyzing the stored signals to determine if the stored signals being transmitted is in one of the transmission formats, and if so, maintaining energization of the receiver in predetermined time increments for up to a maximum of a second predetermined time period and checking if any of the stored signals associated with each such time increment conform to at least one of the transmission formats.

Abstract: A modulator that modulates and encodes data using data symbols, interspersed with pilot symbols, for transmission to another modem, and a demodulator that decodes data symbols of a signal received from another modem. In the demodulator, a received signal is sampled at four times the symbol rate. The sampled signal is converted to quadrature signals and low-pass filtered to produce a complex baseband signal. Data symbols in the complex baseband signal are sampled in synchronization with the start of each symbol based on the pilot symbols that are interspersed in the signal. By processing the pilot symbols, full modem synchronization is maintained down to a very low signal-to-noise ratio, through noise bursts, or even when the data symbols representing data are replaced by predefined sequences of data symbols that convey the dots and dashes of Morse code identifying the station transmitting the modulated signal.

Abstract: The method is for resynchronizing a Data Reception Device. An error in synchronization occurs in multiplex equipment due to simulated frame alignment words. This situation is identified by a monitor that outputs an asynchronous desynchronization command (AB). The command is intermediately stored and is only evaluated with a window pulse (RI). As a result thereof, an error in synchronization, after whose appearance a resynchronization ensues, is avoided.

Abstract: A frame sync acquisition mechanism accurately locates a frame synchronization word within successive selectively bit-stuffed frames of data by not only looking for the frame sync word in the two expected alternative frame sync word locations based upon either the addition of stuff bits or the lack of such stuff bits, but also selectively examining a pair of additional potential locations, one of which precedes and the other of which succeeds the two expected alternative frame sync word locations. If an exact match with the frame sync word is located in either of the expected locations, that location is selected as the reference for the next succeeding frame. During the search of the next successive frame and for every succeeding frame, an attempt is made to initially match the frame sync word with in either of these expected locations. If unable to do so, the search is expanded to encompass the entire window of location uncertainty, so as to include the two additional locations.

Abstract: A method is provided for detecting a synchronization word in frames of serially transmitted data. The synchronization word consists of l synchronization bits, which are transmitted one bit per frame at a known position in each frame. The method comprises the steps of: storing each incoming bit in a memory organized as groups of words, each having at least l bits, so that each group of words contains bits from a same position in consecutive frames; rotating each group of words; comparing the group of words, at each rotation, to the synchronization word.

Abstract: A method and apparatus for effecting a digital communications in a tandem cross-connect of an intermediate station in a telephone system communications network to enable synchronization of the digital signals coupled between ports of the cross-connect. The method and apparatus provide center-tapped transformers at each port for coupling into the cross-connect, applying synchronizing signals to the center-tap of the transformer for raising and lowering the DC voltage of the transformer output cross-connect side without adversely affecting the signals being transmitted across the transformer coupled network, and processing received signals to identify and synchronize to repeating protocol patterns. In particular, the invention employs photo-optically coupling to the transformers to maintain electrical isolation of the synchronizing elements of the circuitry and employing the circuitry in particular in connection with synchronizing to the A and B signalling bits of a T1 protocol.

Abstract: A frame-synchronous reproducing circuit (10) includes a BIC status register (20) of six stages, and a BIC status signal (c) from each stage of the register is applied to a BIC pattern determination circuit (24) in which the BIC status signal (c) and a BIC changing pattern being stored in advance are compared with each other. If the both are coincident with each other, the BIC pattern determination circuit (24) applies a high-level signal to a JK flip-flop (26) via an OR circuit (48), whereby a high-level signal representing that frame synchronization has been settled is outputted from the JK flip-flop (26).

Abstract: A bit insertion apparatus and method used to error encode data stored on data storage media monitors the number of bit insertions made on a given randomized block of data to determine if the number of bit insertions falls within the tolerable limits for storing the data. If the number of bit insertions is not tolerable, the pseudo-random code used to randomize the data stream is reconfigured. In a preferred embodiment, the bit insertion technique monitors the phase and amplitude content of the data stream and inserts appropriate bit patterns to ensure that phase and amplitude lock are maintained on the data stream for reading and decoding purposes.

Abstract: Audio data is processed from a packetized data stream carrying digital television information in a succession of fixed length transport packets. Some of the packets contain a presentation time stamp (PTS) indicative of a time for commencing the output of associated audio data. After the audio data stream has been acquired, the detected audio packets are monitored to locate subsequent PTS's for adjusting the timing at which audio data is output, thereby providing proper lip synchronization with associated video. Errors in the audio data are processed in a manner which attempts to maintain synchronization of the audio data stream while masking the errors. In the event that the synchronization condition cannot be maintained, for example in the presence of errors over more than one audio frame, the audio data stream is reacquired while the audio output is concealed.

Abstract: A method to encode and to decode frames of data used in synchronous protocols, including HDLC and SDLC. The invention operates on blocks of data, such as data bytes or data words, in a parallel rather than a bit serial manner. The invention compares an aligned block of data with reference bit sequences for flag or abort signal detection, for zero detection, for zero deletion, for detection of consecutive one bits, and for zero insertion following a stream of consecutive one bits, for encoding and decoding according to various protocols. The invention also maintains proper data alignment following such zero insertions or deletions, and provides encoding and decoding under both data overrun and data underrun conditions.

Abstract: A system and method for determining a timing error of an incoming signal, in one embodiment, receives the incoming signal into a receiver, and locates a known portion within a time frame of the incoming signal. The known portion is compared with a stored representation of the known portion, and with a stored representation of a derivative of the known portion. The timing error of the incoming signal is determined with respect to the clock signal based on the comparing of the known portion with the stored representations, and a subsequent known portion is located within a subsequent time frame of the incoming signal based on the timing error.

Abstract: A superframe lock subsystem includes a correlator which searches for and identifies a first unique word indicative of a frame boundary within a received bit stream during an initial acquisition state. A controller subsequently predicts frame boundaries in accordance with the first unique word. In a tentative frame lock state, the correlator searches for and determines if a second unique word exists at the frame boundary subsequent the frame boundary which corresponds to the first unique word. If the second unique word is determined to exist at the corresponding frame boundary and if a single frame duration separates the first and second unique words, the superframe lock subsystem enters a frame lock state. During the frame lock state, information of the corresponding frames is processed.

Abstract: A television signal is formatted for transmission by arranging a plurality of encoded data symbols, representing a plurality of source data bytes, into successive data frames each comprising 313 data segments. One of the data segments of each frame comprises a frame sync segment of which the last 12 symbols comprise a copy of the last 12 encoded data symbols of the preceding data segment. The remaining segments of each frame comprise 12 interleaved subsegments A-L, each subsegment comprising a plurality of encoded data symbols representing a contiguous group of sources data bytes, with the first symbol of each of the first 4 subsegments A-D comprising a predetermined segment sync symbol. The received signal is decoded by independently processing the symbols of each respective subsegment to derive estimations of the source data bytes.

Abstract: A system for use in a local switching center is provided for processing synchronization signals. A transmission sync signal is generated at the local switching center for transmission to a switching center of a higher hierarchy for looping back to the local switching center. The looped back sync signal has a propagation delay time with respect to the transmission sync signal. A time division switch produces clock pulses. A stored pattern is read out of a non-volatile memory according to an address value provided by an address counter which counts the clock pulses of the time division switch. A delay time is also read out of the non-volatile memory according to the same address value. A phase difference signal is produced by comparing the length of the propagation delay time with the delay time read out of the non-volatile memory.

Abstract: An audio decoder decodes audio frames included in a Motion Picture Experts Group (MPEG) bitstream for presentation or playing. Each audio frame includes a synchronization code and a frame header, followed by audio data. The synchronization codes are detected, and it is determined that the decoder is synchronized to the bitstream after a first predetermined number, for example three, of successive valid audio frames have been detected. It is similarly determined that the decoder is unsynchronized to the bitstream after a second predetermined number, which can also be three, of successive invalid audio frames have been detected. Each and every frame is determined to be valid if its header parameters are valid, it passes the CRC error check (optional), no syntax errors are detected and its frame length (interval) is as expected.

Abstract: A synchronizer for telecommunications signals includes a telecommunications interface for receiving bits of a telecommunications signal having a frame, an SRAM which stores bit-defined states for a plurality of bit locations in the frame, a state update lookup table for changing the states for a plurality of the frame bit locations of the SRAM based on a previous state and based on an incoming bit of the telecommunications signal, and frame location identification logic for determining the location of the overhead bit of the telecommunications signal frame based on the states of the plurality of bit locations. In a first embodiment, the SRAM is an x by y bit SRAM, where x equals the number of bits in the frame, and y is large enough so that the number of possible states .ltoreq.2.sup.Y.

Abstract: The present invention provides a method and device for channel selection for setting at least one channel among N channels as a reference channel, detecting temporal location of the reference channel in a reception side, selecting an arbitrary channel using a relative time difference between the detected temporal location of the reference channel and that of the channel to be selected.

Abstract: In a receiver for an OFDM modulated transmission signal including at least one synchronizing symbol in each frame, the synchronizing symbol is located by stepwise shifting a window along a reception sample sequence to make a cross-correlation calculator (55) calculate cross-correlation values between a stored pattern produced from a pattern memory (53) and sequence portions picked up by the window, a maximum selector (57, 59) select two successive maxima of the cross-correlation values at a time interval substantially equal to a frame period, and a controllable clock generator (61-65) generate a clock sequence at the time interval for use in sampling the sample sequence. On a transmitter side, the at least one synchronizing symbol may either be preceded by a null period or be a main synchronizing symbol preceded by an auxiliary synchronizing symbol for use in roughly defining ranges in which the window should be shifted.

Abstract: A line sync detector for a digital television receiver receives digital television data including line synchronization code groups of four symbols having successive values of +S, -S, -S and +S at the beginning of each data line, S being a prescribed sample level. A first delay line has an input tap to which the digital television data are supplied, an output tap, first and second intermediate taps, a first symbol latch having an input connection from the input tap and having an output connection to the first intermediate tap, a second symbol latch having an input connection from the first intermediate tap and having an output connection to the second intermediate tap, and a third symbol latch having an input connection from the second intermediate tap and having an output connection to the output tap. The signals at the input tap, the first and second intermediate taps and the output tap of the first delay line are combined in 1:(-1):(-1):1 ratio to generate a combined response.

Abstract: A high speed parallel frame synchronizer provides high speed frame synchronization functions utilizing parallel processing techniques implemented with commercially available components. Serial input data is demultiplexed to an N bit wide word at a rate of 1/N of the input clock frequency. A total of N parallel correlators are used to detect the frame synchronization pattern. Outputs of the correlators are arbitrated using a priority encoder which provides synchronization information to the frame synchronizer. One embodiment of this invention utilizes 4N correlators to simultaneously provide for synchronization of true/inverted and forward/reverse data generated by real-time or playback data sources.

Abstract: A synchronization detector includes a NRZI circuit for extracting edge portions of RF signals detected as binary-valued signals to form a pulse train, a counter for counting the number of channel clocks in the distance between transitions represented by the edge portions, a latch circuit operated responsive to pulses from the NRZI circuit for holding a number of previously counted channel clocks immediately preceding a current count of channel clocks, and AND gates and an OR gate for detecting synchronization signals when the combination of the channel clocks from the counter and the latch circuit is the combination of the maximum distance between transitions Tmax and Tmax-kT (k=1 or 2) of a (d, k; m, n; r) modulation code. Synchronization signals may be detected promptly even if the frame structure is increased in size to enable restoration of synchronization to be expedited when frame structure synchronization is not in order. A demodulator utilizing the synchronization signal detector is also disclosed.

Abstract: In a wireless TDMA network a control module (CM) sends a time stamp relative to the beginning of its frame in a synchronization packet allowing each of a plurality of user modules (UM) to maintain synchronization relative to the CM. The CM uses a plurality of directional antennas and transmits the synchronization packets over each antenna over a predetermined number of frames. The UMs use a receive time stamp to identify the beginning of a received synchronization packet. The difference between the time stamps combined with a delay constant is used by the UMs to adjust time synchronization to the CM frame.

Abstract: For a radio communications system with time-divided frequencies, the synchronization between a base station and a mobile station is shifted as the mobile moves. The base station transmits symbol sequences with synchronization words to the mobile, which through this obtains a reference point in time. The mobile transmits to the base station symbol sequences with synchronization words, which in the mobile may be displaced in time relative to the reference point in time. The base station generates a reception point in time for the symbol sequences from the mobile by correlation and filtering. The reception point in time is compared with the reference point in time and upon a mutual deviation, a time deviation is generated for the base station. This time deviation is added to a previous time shift in the mobile.

Abstract: A succession of variable length data packets containing a header portion and data portion are received. Selected data from the data packet headers is stored in designated locations of a header memory. A data packet start address is provided with each stored header portion to designate a location in a data memory for commencing the storage of data contained in a corresponding data packet. The data from the received data packets is stored commencing in the data memory locations designated by the corresponding data packet start addresses. In an illustrated embodiment, the data packets are macroblocks from digitized television frames. A plurality of next data packet position indicators are provided in the data, for use in periodically verifying macroblock boundaries during the receipt of the television data and to provide a rapid recovery from a transmission error affecting the actual or identified length of a macroblock.

Abstract: A method and apparatus is provided for synchronizing a received communication signal. A synchronization signal is derived from a received signal having a plurality of synchronization words. Each synchronization word has a predetermined number of synchronization symbols. The synchronization signal is filtered. The filtering is characterized by spacing each filter tap to correspond to synchronization word length increments. Synchronization information is generated which is based on a comparison of the filtered synchronization signal to a threshold. Finally, the synchronization information is output based on a confidence derision derived from the synchronization information.