Abstract: A method, system, and device capable of generating one or more clocks internally to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external synchronization clocks for each data stream. One aspect of the clock generator provides a two-stage interpolation system. In a first stage, two clocks are selected which accurately detect a calibration data sample. In a second stage, a single, fine-tuned, clock is synthesized by interpolating the two selected clocks.

Abstract: Sort operations of an input signal are performed by providing a first sort part 6 comprising one shift circuit 8 and (l?1) sort circuits 9a to 9c, and a second sort part 7 comprising one delay circuit 10, (m?1) sort circuits 11a to 11c and m shift circuits 12a to 12d in a pattern synchronous circuit 100.

Abstract: A discrete multitone modulation transmission system is described in which frame synchronization is monitored at the receiver by correlating frequency domain complex amplitudes of a synchronizing frame with a stored synchronizing pattern. If the correlation result falls below a threshold, indicating a loss of frame synchronization, a plurality of correlations are performed, in each case using the stored complex amplitudes of the synchronizing frame multiplied by a respective complex value representing a respective complex derotation corresponding to a respective possible time shift of the synchronizing frame. The best correlation result, if it exceeds another threshold, indicates a time shift for restoring frame synchronization, this being possible before the next synchronizing frame is received.

Abstract: A method and apparatus for triggering data-path conversion utilizing PCM bit robbing signalling. The method and apparatus permits the pass-through of compressed voice packets over a PCM stream between dissimilar interconnected networks or dissimilar payload specifications in the interconnected networks, and also provides the capability to convert the packets to a different payload specification between the networks. Once a voice path is established between the two networks, the incoming PCM data stream is monitored for a voice synchronization pattern which appears periodically in a predetermined bit position in the PCM samples. Upon detection of a matching voice synchronization pattern, a pass-through mode for the voice data between the networks is initiated. A data or payload conversion operation may also be initiated on detection of the matching voice synchronization pattern.

Abstract: Method and apparatus for protocol pattern identification in protocol data units (PDUs). Techniques disclosed utilize the concept of stages. Within each stage, a protocol identification apparatus attempts to find a pattern match between the bits of the protocol data unit and the predefined bits of search patterns for a particular layer of protocol encapsulation. Once found the apparatus resets itself and begins the search anew for the next layer of encapsulation. The user is provided the ability to look for a particular pattern in a higher layer protocol without having knowledge of which lower layer protocols were used. Both hardware and software implementations of this apparatus provide for very fast identification of the protocol data units. Information regarding which encapsulations are present in a particular protocol data unit are provided saving software routines time when they process each packet.

Abstract: Data transactions are partitioned to transfer data across a communication connection requiring naturally aligned data transfers of quad-words. It is determining from byte enable signals whether the bytes of the data to be transferred start in the high order dword or end in the low order dword of a quad-word. The transaction is separated into two transactions if the bytes of the data to be transferred start in the high order dword or end in the low order dword of a quad word. A second transaction is created by pre-appending if the bytes of the data to be transferred start in the high order dword. A second transaction is created by post-appending if the bytes of the data to be transferred end in the low order dword of a quad word.

Abstract: A method and system for maintaining synchronization and identifying received codewords in a spread spectrum communication system is disclosed. According to the method and system, a spread spectrum transmitter divides information being transmitted into pairs of tetrads. The transmitter then substitutes modulating codes selected from first and second groups of modulating codes for each pair of tetrads. The bit stream consists of codewords alternatingly selected from the first and second code groups. The bit stream does not contain any codes from the first and second groups other than the selected codes in the selected positions. The transmitter modulates a carrier using the modulating codes and transmits the signal to a spread spectrum receiver. The spread spectrum receiver synchronizes itself with the incoming signal and identifies the transmitted information by detecting the alternating sequence of codewords from the first and second code groups.

Abstract: The frame synchronizing circuit establishes frame synchronization by detecting a sync pattern laid in an incoming frame. The frame synchronization circuit comprises a first frame synchronizing unit and a second frame synchronizing unit. The first and second synchronizing units synchronize with a first pattern, a second pattern at a first position and a second position, respectively. Thereafter, when the first position used for the synchronization by the first frame synchronizing unit is found to be in error, the first frame synchronizing unit synchronizes with the second pattern at the second position used by the second frame synchronization unit.

Abstract: Selector circuits are connected in a hierarchical arrangement. Each of the selector receives two of synchronizing pattern detection signals and two of synchronizing pattern position signals and selects one of the received synchronizing pattern position signals in accordance with values of the received synchronizing pattern detection signals, so that the position of a synchronizing pattern on parallel data can be identified in a tournament fashion.

Abstract: A signal processing circuit having a data sync signal detector and a disk device. Input data read from a magnetic disk is input to a data discriminator. A data discrimination output constituting a code bit output discriminated by the data discriminator is input to a post-coder the output of which is input to a decoder and a (1+D) processing unit. The processed output of the processing unit is input to an error detection/correction unit and separated into bit strings of odd numbered bits and even numbered bits, divided into groups. An error detection/correction output is input to a data sync signal detector, and matched against a sync pattern. When the number of coincident groups is greater than a threshold value, a sync signal is output and upon detection causes the decoder to demodulate the data.

Abstract: Methods and apparatus for use in aligning frames in a receiver of a data transmission system include checking one or more bit positions associated with a received data stream to determine a number of bits in the bit positions, respectively, that match a predetermined bit pattern. The number for a bit position is compared to a first threshold value and a second threshold value. A bit position is identified as being associated with a false framing pattern or mimic when the number is not less than the first threshold value. A bit position is identified as a potential framing bit position or possible framing bit position when the number is not less than the second threshold value. The first threshold value is changed when a bit position is identified as a potential framing bit position and another bit position is identified as being associated with a false framing pattern.

Abstract: A transmitter outputs a radio signal formed from a first baseband signal incorporating a synchronization signal. The recipient obtains a second baseband signal from the received radio signal, detects the synchronization signal in a portion of the second baseband signal in order to compute synchronization parameters and/or parameters for estimating a radio transmission channel, and uses the computed parameters to demodulate another portion of the second baseband signal and extract the transmitted information from it. The synchronization signal contains a synchronization pattern selected by the transmitter on the basis of signalling information to be supplied to the second station. The receiver searches several patterns in the second baseband signal in order to obtain the signalling information depending on the detected pattern.

Abstract: Method and system for optimally estimating the location of each of a sequence of two or more synchronization patterns in a digital signal bit stream. A first reference location for a sync pattern is determined. A Boolean product or other product of the sync pattern (of length S) with S consecutive bit values of the digital stream is formed, for each of a selected consecutive sequence of candidates for a second reference location of the sync pattern within a window of selected length. A candidate reference location that yields the largest (or smallest) product value within the window is estimated to be a second or “next” reference location of the sync pattern, if the product value is at least equal to (or, alternatively, is no greater than) a selected threshold value. The sync pattern used for testing the digital stream can be varied from one location to another. The number of bit matches or the number of bit non-matches can be used to determine an optimal reference location for the sync pattern.

Abstract: A data sync signal detecting device for detecting a sync signal having sync signal detection errors. The detecting device applies the output data of a most-likelihood decoder to shift register bit cells. The data is sequentially shifted and held in the bit cells of the shift register. The bit cell outputs are separated into odd-numbered and even-numbered bit string and applied to first and second pattern matching circuits. The odd-numbered bit string is matched with “01001” by a first pattern matching circuit. The even-numbered bit string is matched with “01011” by a second pattern matching circuit. First and second matching results are applied to a coincidence number adder/majority decision circuit. When coincidence occurs, the matching result is “1”, and when non-coincidence occurs, the matching result is “0”.

Abstract: An apparatus for detecting a predetermined pattern of bits in a data bitstream includes a series of detecting elements (2-6), each detecting element in the series corresponding to a predetermined bit in the predetermined pattern. Each detecting element receives a data bit from the data bitstream (8), the corresponding predetermined bit in the predetermined pattern and an error signal from a previous detecting element in the series. The output of each detecting element is an error signal indicative of the number of mismatches between the data bit and the corresponding predetermined bit in the predetermined pattern, both in previous detecting elements in the series in previous clock cycles and in the current detecting element in the current clock cycle. The error signal of the final detecting element (6) of the series is coupled to a logic control element (18) for detecting that a maximum allowed level of mismatches has been detected.

Abstract: A digital PLL pulse generator includes a delay-chain section having a plurality of delay elements forming delayed clock signals with different delayed states; a synchronized-signal detecting section to detect a plurality of delayed clock signals, and to output synchronizing information; a pulse forming section to form an output pulse having a desired pulse width and a desired timing by selecting a desired delayed clock signal, based on the synchronizing information and pulse forming information for forming a desired pulse; a feedback section to receive a feedback pulse returned from an external device as a result of loading the output pulse onto the external device, and to detect a phase difference between the feedback pulse and the output pulse; and a correcting section to correct a timing of the output pulse formed by the pulse forming section in response to the detected phase difference.

Abstract: A packet synchronization detector for an incoming digital signal which includes a regularly repeated predetermined synchronization pattern which repetition rate defines the length of one transmission packet according to the present invention comprises a synchronization pattern detector (1) and several synchronization state machines (2, 31, . . . , 3n) which respectively determine whether or not one detected synchronization pattern with a respective position in regard to the length of one transmission frame has the correct repetition rate to determine whether or not lock has been achieved. Therefore, a very fast lock is achieved, since also in case of bit patterns that match to the synchronization byte, but that are not the synchronization byte no penalty time occurs to lock to the incoming digital signal.

Abstract: A synchronism pattern detecting timing recorder (20) records a synchronism pattern detecting timing at which a synchronism pattern is detected in reception data, a synchronism decider (12) collates the reception data with reference data to decide whether or not the reception data is consistent in phase with the reference data, and a timing generator (22) operates, when the synchronism decider (12) gives a decision for inconsistency in phase, for a match between the synchronism pattern detecting timing recorded in the synchronism pattern detecting timing recorder (20), as a subsequent one, and a timing of a synchronism pattern of the expectation data, and the subsequent synchronism pattern detecting timing in record is used to render the phases consistent, allowing for a rapid synchronization to be obtained, without the need of waiting a detection of synchronism pattern, even with an inconsistency in phase due to a false synchronism pattern.

Abstract: A network device configured to detect a framing pattern includes a data scanner and a frame detector. The data scanner examines parallel bytes of data and detects portions of a framing pattern in the parallel bytes of data, identifies the phase of the framing pattern and outputs alignment information and phase information when a framing pattern has been detected. The frame detector receives the alignment information and phase information and determines whether framing patterns having the same phase relationship have been detected within a predetermined number of frames.

Abstract: A digital frame determination method and apparatus are provided which collect a data frame from a digital data stream starting at an initial frame start and a nominal frame frequency, test the data frame for alignment based on a set of rules, determine an adjustment value in accordance with the set of rules when the data frame is not aligned, adjust the frame start in accordance with the adjustment value, and repeat until the data frame is aligned and the alignment is verified.

Abstract: A method is described for estimating channel impulse responses of a mobile radio channel with a broad bandwidth by a code division multiplexing method, and with a synchronization channel continuously transmitting sequences to mobile radio receivers. The sequences are provided for synchronization of each mobile radio receiver and are known to each of the mobile radio receivers. The transmitted sequences have pilot symbols for identifying the synchronization channel, and the pilot symbols are transmitted at points that are known to the receivers within a time slot. When searching for and identifying the synchronization channel, the pilot symbols and, possibly, further symbols and sequences which are known in the receivers, are evaluated to estimate the delay times and the complex amplitudes, of the mobile radio channel responses.

Abstract: A detector compares a first bit of a bit stream to a first bit of a pattern. If the first bit of the bit stream and the first bit of the pattern are the same, another detector is allowed to read a second bit of the bit stream and compare it to a second bit of the pattern. This continues until all bits of the pattern are detected. By performing the comparison as each bit of the bit stream arrives on a node, the present detectors are able to detect bit patterns in high-speed bit streams.

Abstract: Apparatus and method for correlating a received communication of a known sequence over a wireless channel through the use of a finite impulse response (FIR) filter having a small number of taps to reduce hardware requirement by as much as one-half that of conventional techniques while obtaining amplitude degradation which is no worse than experienced when employing conventional techniques.

Abstract: A timing circuit used in reading disc media or other dada includes multiple sync detection circuits. In the event that an active sync detection circuit fails to detect sync signals within predefined parameters, a different one of the sync detection circuits searches for a sync pattern. Uniquely definable sequences of sync patterns are used to determine a position of sync patterns within a sector of data.

Abstract: A method for detecting synchronization loss of the trellis minimum path metric in V.34 modem communications. The invention detects synchronization loss due to bit inversions in trellis decoding in transmitted digital frames due to a periodic inversion pattern that is used for superframe synchronization. The method provides synchronization loss detection by finding the ratio of moving averages for a series of data blocks to the average of a series of inverted 4D symbols located periodically in the beginning and center of received data frames.

Abstract: A method and system for detecting frame slips due to loss of synchronization in a digital communication channel is described. In an illustrative embodiment, a synchronization bit pattern is periodically embedded in the digital data stream. In a described embodiment, the sign bits of the octets of every N frame of data is robbed to form a periodic control channel carrying the synchronization bit pattern. The control channel can be monitored at the appropriate intervals to detect the appropriate synchronization bit pattern. Failure to detect the synchronization bit pattern at the appropriate interval indicates a loss of synchronization such as a frame slip.

Abstract: A circuit which recovers a synchronization code, and a method thereof. Where a synchronization code is not detected from an incoming bitstream, a plurality of synchronization code recovery candidate patterns are compared with an original synchronization pattern, and location data to produce an optimal synchronization pattern is determined and generated on the basis of a result of the comparison. The synchronization code is recovered to a location corresponding to the location data. Alternatively, where a synchronization code is not detected from an incoming bitstream, a plurality of synchronization code recovery candidate patterns are error-corrected, and location data to produce an optimal synchronization pattern is determined and generated on the basis of a result of the error correction. The synchronization code is recovered to a location corresponding to the location data.

Abstract: A device for the regeneration of a clock signal uses a reference clock signal given by an internal oscillator to measure the number of reference clock pulses between the first two synchronization pulses sent by an external serial bus or USB at the beginning of each transaction. Thus a rough measurement N is obtained of the USB clock signal to be regenerated. The delay of each of these two synchronization pulses with respect to the previous pulse of the reference clock signal is measured. This delay is computed with respect to an internally defined time unit. On the basis of the measurement of these two delays, and the measurement of the number of reference clock periods, and knowing the measurement n of the period of the reference clock signal in the time unit, the period of the USB clock signal to be regenerated is computed with precision.

Abstract: An approach for providing message synchronization in a communication system is disclosed. Using a selected channel coding method (e.g., Golay coding), an encoder encodes a message for transmission over a communication channel. An interleaver applies a predetermined interleaving pattern to the encoded message. A mask pattern with a prescribed sequence of bits is applied to the interleaved message; the prescribed sequence is ordered to eliminate an all zeros bit pattern and an all ones bit pattern. A multiplexer multiplexes the masked message with data traffic over the communication channel. The masked message is segmented into multiple blocks of a fixed length. At the receiver side, the mask pattern is applied to the demultiplexed message. The message is de-interleaved and decoded to restore the original message.

Abstract: A sync pattern detection apparatus includes a sync pattern detection unit configured to detect a sync pattern from an input signal, a plurality of sync pattern protection units configured to protect the sync pattern detected by the sync pattern detection unit, a reliability evaluation unit configured to evaluate the reliabilities of a plurality of sync pattern protection situations by the plurality of sync pattern protection units, and a selection unit configured to select a sync pattern protected by a predetermined sync pattern protection unit, on the basis of the reliability evaluation of the plurality of sync pattern protection situations by the reliability evaluation unit.

Abstract: A communication device includes a transmitter and receiver. The transmitter includes an M-ary encoder configured to generate an M−1 number of distinctive symbols each comprising k bits. M is equal to 2k and k is a positive integer. The transmitter also includes a code generator configured to produce spread spectrum codeword sequences based on the symbols generated by the M-ary encoder and based on a first and a second Gold code polynomials. The transmitter sends a radio signal based on the spread spectrum codeword sequences. The receiver is configured to receive the radio signal. The receiver includes a first shift register configured to receive an input signal generated based on the received radio signal and a second shift register configured to receive and circularly shift a locally generated codeword sequence that is identical to the codeword sequence used to encode the symbols.

Abstract: A detected signal 111 contains a preamble portion which includes symbol alternations, followed by a unique word portion, and a data portion. Each time a symbol alternation is detected, a correction value calculation section 102 averages the phase shift in the detected signal 111 for a predetermined length, thereby calculating a correction value 115. The correction value determination section 103 stores a plurality of correction values 115 in a chronological order. When the unique word portion is detected, the correction value determination section 103 retains, as an effective correction value 118, a correction value which is arrived at by going back a predetermined number of correction values among the stored correction values. A phase rotation section 104 corrects the phase of the detected signal 111 by using an effective correction value 118 calculated by the correction value determination section 103.

Abstract: For each sync frame, an AND circuit detects whether a pre-pit synchronization signal can be obtained within a window set by a timing generator. Detection result of the AND circuit is held by a shift register, where it is shifted in response to each sync frame. On the basis of a parallel output from the shift register, a decoder determines whether the detection of the pre-pit synchronization signal is accurate or erroneous. Count value of a counter is incremented by one each time the decoder determines that the detection of the pre-pit synchronization signal is accurate, but is decremented by one each time the decoder determines that the detection of the pre-pit synchronization signal is erroneous. Identification section identifies stability/instability of the pre-pit synchronization signal detection.

Abstract: The present application discloses an improved mobile communications architecture, in which each base station broadcasts not only data which has been spread by that station's long code word, but also (intermittently) code identification data which has not been spread. The code identification data is a block code which includes multiple symbols, so that multiple intermittent transmissions are required to complete the transmission of the code identification data. This transmission lets the mobile station shorten the search for the base station's long code word in two ways: the code identification data gives at least some information about the long code itself; and the phase of the block code gives at least some information about the phase of the long code word.

Abstract: Described are a system, method and device to synchronize block data received in a data stream where the data stream is received on set data word increments. A synchronization header in each of a plurality of consecutive data word increments may be detected in a common location of a set portion or window of each consecutive fixed word increment. The data stream may be slipped by a fixed bit quantity in response to detecting an absence of the synchronization header in the common location of the set portion of a received data word increment.

Abstract: This proposal describes an optimized synchronization (SYNCH) symbol sequence to be used in transmission systems, which are currently under standardization. The synchronization symbol is constructed using specially designed OFDM (orthogonal frequency division multiplexing) symbols with an optimized sequence, which is mapped onto the modulated subcarriers. The resulting synchronization symbol consists of several repetitions in the time domain. Using the proposed sequence the resulting synchronization symbol achieves a high timing detection and frequency offset estimation accuracy. Furthermore the burst is optimized to achieve a very low envelope fluctuation (low Peak-to-Average Power Ratio) and a very low dynamic range to reduce complexity on the receiver and to save time and frequency acquisition time in the receiver. The proposed sequence is furthermore optimized with respect to all other synchronization symbols that are used to construct the synchronization and training preambles for the BCCH-DLCHs.

Abstract: In a frame sync method, a receiver searches for the presence of an N-symbol long unique word pattern. For each possible frame sync detected, the receiver proceeds to demodulation and FEC processing. After each iteration of the FEC decoder, the detected unique word pattern is compared to the expected one and the frame sync is detected if the number of unique word errors has decreased.

Abstract: A symbol recovery system for a digital VSB signal finds sync pattern correlations in the incoming signal. The present symbol sync acquisition circuit also accounts for static which distort the signal during transmission. Initially, both positive and negative sync pattern correlations are accorded equal weight, with the non sync pattern correlations being accorded a negative weight. Values are accumulated in a segment integrator and stored in a FIFO having a location for each symbol position in a segment. A comparator initially produces an output when sync pattern correlations are found that add to a given value. After a relatively small number of correlations, as tabulated in a confidence counter, a VCO is enabled to change its frequency under control of error pulses based upon the symbol sync.

Abstract: A sync signal detection method for receiving a sync signal regularly radio-transmitted from a predetermined station at a predetermined cycle and detecting the received sync signal is used in which a cycle at which a sync signal is detected is judged, a detection window having a predetermined width is set at every judged cycle, and only a sync signal detected from received signals in the detection window is judged as an effective sync signal.

Abstract: A null symbol position detecting method, apparatus, and receiver for quickly and accurately detecting a null symbol from a broadcast signal containing it in any broadcast signal receiving environment. A digital audio broadcast (DAB) signal is received and tuned in and this signal is I/Q-demodulated. The I and Q signal obtained by the I/Q demodulation are delayed by an I-component delay circuit and a Q-component delay circuit respectively by one valid symbol period to form a delay signal Id and a delay signal Qd respectively. Correlation is obtained between the delay signals Id and Qd and the signals I and Q which are not delayed. The peak of this correlation is determined by a peak decision circuit. The level pattern of the peak is detected by a level pattern decision circuit.

Abstract: A method and apparatus for estimating the timing position of data bursts received in a data stream, where each data burst includes a number of bits comprising a training sequence in a fixed location. The receiver includes circuitry for estimating the timing position of the data bursts received in the data stream. For each of the first N received data bursts, the receiver estimates a plurality of timing locations of the training sequence, correlates the training sequence for each estimated timing location, and determines the timing location associated with the highest correlation value. The receiver then determines the average timing location of the highest correlation values for each of the first N data bursts. For the next M data bursts the receiver estimates the timing location of each data burst based on the average timing location for the first N data bursts.

Abstract: A Universal Serial Bus repeater is provided, comprising a method and apparatus for detecting a specified data pattern and regenerating or retransmitting the recognized data pattern. In some embodiments, the invention recognizes an end of sync signal, and is operable to retransmit the end of sync signal and the following data that is presumed to be valid as a result of sync recognition. In other embodiments, the invention recognizes and retransmits a properly aligned end of packet signal, the size of which is dependent on detection of whether the end of packet signal is a part of a start of frame packet.

Abstract: A receiver in a home phone-lines local area network system is proposed. The receiver can distinguish a valid signal and a collision backoff signal from noises in real time. The receiver for a home phone-lines LAN system comprises a QAM demodulator, an equalizer, a deconstellation, and a transmission data reading device. The receiver further comprises a signal match filter module and a detector. The signal match filter module comprises an adder and at least a cross-correlator. The adder adds the “I” signal and “Q” signal outputted from the QAM demodulator and outputs a combined signal. The cross-correlator performs match operation, such as a comparison operation or a correlation operation, of the combined signal and an identification value and outputs a match value to the detector. Since the signal match filter module connects directly to the output of QAM demodulator, it can immediately identify the identification code TRN16 contained in the received signal.

Abstract: A circuit for receiving data includes a first receiver having an input for receiving data and an input for receiving a first clock signal. The data is clocked into the first receiver by the first clock signal. The circuit also has a second receiver having an input for receiving data and an input for receiving a second clock signal. The first and second clock signals have the same frequency and are phase shifted with respect to one another. The data is clocked into the second receiver by the second clock signal. Determination is provided to determine if at least one of the receivers has correctly received the data. A first output of one of the receivers is enabled in accordance with the determination.

Abstract: A device and method for regulating a sampling rate in a digital data transfer system includes transmitting a synchronizing word used for receiver-side regulation of the sampling rate at regular time intervals. The received signal is filtered by a rate-regulating criterion filter and is simultaneously detected to recognize the synchronizing word. The initial value of the rate-regulating criterion filter controls an adjusting logic for the sampling rate once the synchronizing word is recognized. A rate is formed for the initial value of the rate-regulating criterion filter and the rate undergoes high pass filtering before it is fed to the adjusting logic. An apparatus for controlling the sampling includes a clock control criterion filter, an adjustment logic device, a switch, an apparatus identifying the synchronization word, a magnitude formation circuit, and a high-pass filter. The formation circuit and the high-pass filter are disposed between the criterion filter and the logic device.

Abstract: An apparatus to overcome a metastable state in a communication system employing a common clock period includes a first latch and a second latch, the first latch being clocked by a clock signal and the second latch being clocked by an inverted version of said clock signal, each of the first and second latches receiving a data stream. A delay device delays the output of the second latch by one half of a cycle of the clock signal. A multiplexer outputs the output of the first latch when the received data stream does not exhibit metastability relative to the clock signal and outputs the output of the delay device in the presence of metastability. By latching the data according to the inverted clock, the data is not latched during state transitions thereof and metastability is avoided. The delay device re-synchronizes the latched data with the active edges of the clock signal.

Abstract: A data reading apparatus reads variable length-coded data. A digital signal processor of this data reading apparatus executes a code word reading step of sequentially reading a series of code words partitioned by a plurality of resynchronization markers, and a resynchronization marker detecting step of detecting a next resynchronization marker before a reading position in the code word reading step reaches the next resynchronization marker.

Abstract: Disclosed is a peripheral device for reliably detecting synchronization patterns in CD-ROM media. The peripheral device has an internal circuitry for controlling and processing data that is read from a medium of the peripheral device is disclosed. The peripheral device comprises a digital signal processor, a decoder circuit, and a state machine. The digital signal processor is configured to receive the data that is being read from the medium of the peripheral device. The decoder circuit is coupled to the digital signal processor and forms a part of the internal circuitry. Further, the decoder circuit includes an internal RAM that is configured to store a sector of the data including a current sync pattern and a next sync pattern. The state machine resides in the decoder for analyzing the current sync pattern and the next sync pattern of the sector of the data. In the analysis mode, the state code is configured to determine whether a fatal error is present in the data.

Abstract: In order to extract proper signals out of signals containing jitters and skews, the most stable data rows are selected out of data rows obtained by oversampling. A regenerator circuit of serial data is comprised of means for storing serial data as received for two system clocks, means for comparing special character signals used in transmission with the data as stored for two system clocks, and determination means for determining positions (shift numbers) where patterns of the data match the special character signal, respectively, wherein correction for skews is implemented by sampling the data on the basis of information on the positions where matching is made, as determined by the determination means.

Abstract: Data transactions are partitioned to transfer data across a communication connection requiring naturally aligned data transfers of quad-words. It is determining from byte enable signals whether the bytes of the data to be transferred start in the high order dword or end in the low order dword of a quad-word. The transaction is separated into two transactions if the bytes of the data to be transferred start in the high order dword or end in the low order dword of a quad word. A second transaction is created by pre-appending if the bytes of the data to be transferred start in the high order dword. A second transaction is created by post-appending if the bytes of the data to be transferred end in the low order dword of a quad word.