Abstract: A synchronization method and a receiver used in a radio system in which synchronization is made to a received signal are provided. The radio system includes at least one receiver, which receives a modulated and partly previously known signal that includes symbols. The received signal also contains a time and frequency deviation. The receiver includes a multiplier, a transformer and a comparator. The multiplier multiplies the received signal by the known part of the received signal in order to obtain a product. The transformer correlates the product in order to obtain a ratio. The comparator compares the ratio with a pre-set correlation threshold value. Based upon the comparison made by the comparator, a decision is made whether the received signal is synchronized.

Abstract: A method of generating a frame sync signal of a mobile terminal is provided. The mobile terminal includes an input unit, which receives through an I-channel and a Q-channel frames into which a data frame transmitted from a base station is divided; a preamble detection unit, which detects timing information of the base station from a preamble pattern of the received frames; a frame sync pattern detection unit, which receives the frame through the I-channel and an output of the preamble detection unit and verifies the timing information; and a frame sync signal generation unit, which generates a frame sync signal according to an output of the frame sync pattern detection unit.

Abstract: In the transmission device, a synchronization pattern made by arranging a predetermined basic pattern consisting of a combination of a predetermined number of symbols and a reversal basic pattern made by reversing a polarity of each symbol of the basic pattern, in the order according to a reversal pattern, is generated, and transmission data obtained by adding thus obtained synchronization pattern at predetermined timing is transmitted. In the reception device, the basic pattern and reversal basic pattern in the synchronization pattern are correlated with each other by a matched filter (11) corresponding to the basic pattern, and the correlation of the reversal pattern which appears in a signal obtained as a result, is taken by a matched filter consisting of delay portions (12), multipliers (13) and an adder (14).

Abstract: A method for controlling a transmitter for a serial data port is provided. The method includes receiving a set of data at the serial data port. The data in the set of data is compared with a selected pattern of bits. When data in the set of data matches the selected pattern of bits, a bit in a register is set. When the bit in the register is set, transmissions stop. The method further includes processing the set of data to determine a flow control state. When processing the set of data determines that the flow control state is a first state, transmissions re-start.

Abstract: A method employing multisignal encoded start pulses and end pulses for data transmission by use of radio waves, carries out encoding so that a very large number of kinds of patterns (not less than 1014 kinds are possible) can be effected with one frequency. In the binary system, encoding needs a large number of signal pulses and high frequency, and the frequency of the carrier wave becomes very high also. The multisignal method of this invention makes it possible to reduce the encoding bits and the carrier wave frequency by using level sensing and width comparison techniques. This method also removes noise owing to its level sensing and width comparison techniques which have not been used in conventional digital communication systems. Therefore, the reception of erroneous information, the occurrence of unclear audio-visual images, and noise trouble are prevented in the use of radio waves.

Abstract: An input signal DT contains a segment synchronization signal compliant with the ATSC standard. A clock multiplication section 111 multiplies a clock CK. A switchable sampling section 112 selects a sample point from among a plurality of timing points that are defined by the multiplied clock, and samples the input signal DT at the selected sample point. Moreover, the switchable sampling section 112 switches sample points from one to another in a synchronization-unestablished state. Once the segment synchronization is established, a synchronization detection device may maintain a synchronization-established state until the field synchronization detection fails, or the synchronization detection device may output a synchronization detection signal after shifting it in the time direction based on a bit error rate RT of the input signal.

Abstract: A signal quality measurement system includes a transmitter for transmitting a test signal to a receiver and a device for storing a copy of the test signal at the receiver. The similarity between the stored copy of the test signal and the signal received at the receiver is measured to determine reception quality. The receiver also includes a device for selecting a sequence of different synchronization patterns directly from the stored copy of the test signal, for determining, from said received signal, a sequence of signal segments that best matches the synchronization pattern sequence and for synchronizing the received signal with the signal segment sequence, thereby synchronizing the received signal with the stored copy of the test signal.

Abstract: In an alignment/frame synchronization apparatus, a RSB frequency-dividing circuit generates a second clock. A data width extension circuit extends eight input data into 16 output data. A byte alignment circuit generates byte signals, and byte-aligns the output signals in accordance with a byte alignment control signal. A control circuit outputs byte alignment control signals to the byte alignment circuit in correspondence with the byte signals in accordance with detection of A1A1 and A2A2 patterns, and outputs an A1/A2 consecutive pattern signal indicating the reception of a predetermined number of consecutive A1 and A2 frame patterns. A frame pulse generating circuit generates a frame pulse signal when an A2 frame pattern is received following an A1 frame pattern. A frame sync detection circuit generates a frame sync signal when the frame pulse signal output is consecutively received a first predetermined number of times.

Abstract: I and Q symbol streams are demodulated from a received signal of a wave to be PSK-modulated in which BPSK-modulated frame-synchronizing signal and superframe-identifying signal respectively having a 20-symbol length and an 8 PSK-modulated digital signal are time-multiplexed by a demodulating circuit (1). BPSK-demapped bit streams B0 to B3 are generated by a BSPK demapper (3) in accordance with criterion border lines obtained by rotating a basic BPSK criterion border line and a basic criterion border line whose received-signal points are the same as Q-axis on, I-Q phase plane by &pgr;/4, 2&pgr;/4, and 3&pgr;/4 counterclockwise.

Abstract: The present invention includes bit synchronizers and methods of synchronizing and calculating error. One method of synchronizing with a data signal in accordance with the present invention includes providing a data signal having a first portion and a second portion, generating a timing signal, first adjusting the timing signal during the first portion of the data signal, accumulating a history value during the first portion of the data signal, and second adjusting the timing signal during a second portion of the data signal using the history.

Abstract: Described is a system and method for providing a synchronization pattern in a communication system. The method includes generating a synchronization pattern with good randomness properties; packing a signal for transmission with m headers, each header consisting of the synchronization pattern 1/m symbol-time shifted from the previous header; and transmitting the signal. A further method provides for the sampling the transmitted signal with m headers of symbol-time shifted synchronization patterns; and determining symbol timing offset by computing and reordering correlation peaks from the synchronization patterns. A system includes a transmitting system, a receiving system, and a data channel. The transmitted signal includes m headers with 1/m symbol-time shifted synchronization patterns.. The receiving system undersamples the transmitted signal with m synchronization patterns to simulate an oversampled synchronization pattern.

Abstract: Apparatus and method for correlating a received communication of a known sequence over a wireless channel through the use of a finite impulse response (FIR) filter having a small number of taps to reduce hardware requirement by as much as one-half that of conventional techniques while obtaining amplitude degradation which is no worse than experienced when employing conventional techniques.

Abstract: A threshold detector for detecting synchronization signals at correlator output during packet acquisition. An RF receiver converts RF signals into baseband signals. A matched filter correlator correlates samples of the baseband signals with predetermined synchronization signals, such as long sync symbols, and provides corresponding correlation samples. A long-term integrator integrates a first predetermined number of the correlation samples to provide a long term moving average and a short term integrator integrates a second predetermined number of the correlation samples to provide a short term moving average signal. The short term moving average signal is based on channel delay spread and the long term moving average tracks channel noise. A multiplier multiplies the long term moving average signal by a scale factor to generate a dynamic threshold. A detector detects a crossover between the short term moving average and the dynamic threshold to estimate timing of received synchronization signals.

Abstract: A synchronization detection circuit comprises: a matched filter 105 for outputting a correlation value, between a spreading code and data that is obtained by sampling a code spread signal 101, using a sampling clock for one chip cycle; a sampling clock generator 102 for generating the sampling clock, so that, for each cycle of a code spreading signal, a phase delay for the basic clock of one chip cycle is increased by a value obtained by dividing one chip cycle by an integer; and a synchronization determination unit 107 for determining the timing whereat the maximum correlation value is attained and for performing synchronization detection.

Abstract: The present invention provides a frame synchronous circuit wherein the number of devices handling a high-speed digital signal is limited to the minimum without deteriorating frame pull-in time and an erroneous synchronization rate. For the sake of it, synchronous word decision devices decide frame synchronization from four lines of low-speed digital signals into which the high-speed digital signal is converted by a serial-parallel converter. An OR circuit synthesizes respective outputs of the synchronous word decision devices, and an aperture circuit applies an aperture to the output synthesized. A selection circuit fetches only one output corresponding to the change of the apparent synchronous word after establishment of synchronization. A frame counter circuit estimates a predetermined position of the next frame at the time of applying a narrow aperture. A leading-edge positioning/column change circuit performs leading-edge positioning and column change of data to the output of the selection circuit.

Abstract: A data modulation method resistant to channel distortion and a method of correcting error in data coded by the modulation method. The data modulation method uses a run length limited (RLL) modulation code applied to write data to an optical storage medium, the RLL modulation code being expressed as RLL (d, k, m, n, s) with s=2 or greater, where d is minimum run length, k is maximum run length, m is a data bit length before modulation, n is a codeword bit length after modulation, and s is a space length between codewords. Further, the data modulation method provides run lengths expressed as in+1=in+s (n=1, 2, . . . ), where i1=d.

Abstract: A receiver (200) receives (402) a first signal including a sync portion (308) having a carrier acquisition segment (302) and a timing synchronization pattern (304), and a processing system (216) of the receiver calculates (404) a first plurality of squared magnitude Fourier transforms at a first plurality of frequencies on the carrier acquisition segment. The processing system derives (406) an initial carrier frequency error estimate by locating a peak in the first plurality of squared magnitude Fourier transforms, and corrects (408) the sync portion according to the initial carrier frequency error estimate, thereby producing a carrier-corrected sync portion. The processing system then removes (410) the timing synchronization pattern from the carrier-corrected sync portion, thereby producing a second signal having a residual carrier error.

Abstract: A digital frame determination method and apparatus are provided which collect a data frame from a digital data stream starting at an initial frame start and a nominal frame frequency, test the data frame for alignment based on a set of rules, determine an adjustment value in accordance with the set of rules when the data frame is not aligned, adjust the frame start in accordance with the adjustment value, and repeat until the data frame is aligned and the alignment is verified.

Abstract: The invention provides a method and system for temporarily provisioning a telephone service feature. At the request of a calling or called party, a telephone service feature to be temporarily provisioned can be identified. Once identified, the telephone service feature can be provisioned and activated to handle the telephone service feature. Upon completion of the call, the requested telephone service is deactivated. In order to activate the requested telephone service feature, system resources can be allocated to support the identified telephone service feature. The allocation of system resources can include reserving a pool of resources for activating the identified telephone service feature. For example, a pool of line interface circuits may be reserved specifically for providing temporary provisioning of the telephone service feature for subscribers. An available resource capable of processing the identified telephone service feature can be selected from the pool of resources.

Abstract: A frame synchronism processing apparatus including a first detecting unit for detecting the synchronism of a subframe, a second detecting unit for detecting the synchronism of a multiframe, and a synchronism detection retrying control unit for forcibly bringing the first detecting unit and the second detecting unit into a synchronism detection retrying mode if the second detecting unit has failed to detect the synchronism of the multiframe. Assuring that a false synchronous state is brought about on the subframe synchronism with the result that the detection of the synchronism of the multiframe has been failed, the detection of synchronism of the subframes and the detection of synchronism of the multiframe are retried, thus avoiding a deadlock of frame synchronism process due to the possible false synchronous state and hence improving the reliability in synchronism process.

Abstract: A receiver produces complex data samples from a demodulated received signal. The data samples, which may form a preamble identifying a wireless LAN data burst, are arranged in a sequence comprising sub-sequences having a predetermined relationship with each other. A tuning frequency offset is determined by delaying the complex data samples by a plurality of different delay periods, auto-correlating the complex data samples using said different delay periods in order to produce respective auto-correlation outputs, determining a plurality of phase-dependent values each dependent upon phase errors in a respective auto-correlation output and calculating a value representing frequency offset by combining the phase-dependent values in a weighted manner. The preamble can be recognised by using the same delay means.

Abstract: A method and apparatus for synchronizing ATM cells is disclosed. A synchronization unit receives a data clock signal and a plurality of control signals. Based on those signals, a sync pulse is generated. If synchronization is not achieved within a predetermined time period, the sync pulse is shifted one bit location. Through iterative shifting of the sync pulse, synchronization is ultimately achieved.

Abstract: A method of determining a frame rate of a data frame in a communication system by using apriori knowledge of data frame. In one embodiment, a signal is received at the communication device. Then a data frame portion of the signal is isolated. Next, a potential frame rate is chosen and the data frame is formatted accordingly. Decoding, at the chosen potential frame rate, occurs on the data frame. Then, a tail bit portion of the data frame is isolated. Afterward, a logic level of the decoded tail bit data is compared against the apriori knowledge of a transmitted logic level for the tail bit portion of the data frame. In addition, comparisons are also made between other data metrics and their expected values. Finally, a level of confidence is communicated to the communication device based upon a result of the comparisons.

Abstract: The present invention provides an optical parallel transmission system which can achieve reduction of the processing time without adding many processing functions. A pattern data adder adds, to transmission data, pattern data determined from the transmission data so that the transmission data per one bit becomes data having a form close to a repetition of “1”, “0”, and optical parallel transmission by AC coupling is realized thereby.

Abstract: A burst synchronizing circuit synchronizes a received data signal in a burst fashion and sampling phases with which the received data signal is sampled. A first part samples a data pattern with different sampling phases. A second part selects the received data signal sampled with an optimal sampling phase based on sampling phases with which the data pattern is detected.

Abstract: A sync detection device for an optical disk player. The generation of sync insertion signals is stopped when a sync detection signal is normally generated after a sync protection window signal is out of sync with the sync detection signal. A sync insertion and protection device sets a sync protection window according to a sync detection signal from a sync detector in response to a reset signal. The sync insertion and protection device counts a playback clock to generate a sync protection window signal if the count value is coincident with a position where the sync signal is to be generated, and generates a sync insertion signal in response to a sync insertion request. A sync generator outputs the sync protection window signal if the sync detection signal is in sync with the sync protection window signal, and outputs the sync insertion signal if the sync detection signal is out of sync with the sync protection window signal.

Abstract: A multiple frame rate synchronous detecting apparatus for synchronous-detecting received serial data having one frame rate among a plurality of predetermined frame rates is provided. The apparatus comprises a serial-to-parallel converter for serial-to-parallel converting the received serial data with matching with highest frame rate, a coincidence detector for comparing a portion of the converted parallel data corresponding to a predetermined region defined based on the frame rate, with a pattern for synchronous detection to detect coincidence, and a synchronous determiner for determining to have been synchronized with the frame rate when a periodic cycle of the coincidence detection is the same as a previous one.

Abstract: A timing control circuit includes a synchronous detecting portion which detects a synchronous pattern data of a received signal which has been demodulated based on a first control signal and generates a detection result, a first counter portion which generates a first signal at each first cycle based on the detection result, a second counter portion which generates a second signal at each second cycle based on the detection result, and a first control portion which generates the first control signal based on the first and second signals.

Abstract: A system and method for detecting an impulse radio signal obtains a template pulse train and a received impulse radio signal. The system compares the template pulse train and the received impulse radio signal to obtain a comparison result. The system performs a threshold check on the comparison result. If the comparison result passes the threshold check, the system locks on the received impulse radio signal. The system may also perform a quick check, a sychronization check, and/or a command check of the impulse radio signal.

Abstract: A method is provided for transmitting control information in a digital audio broadcasting system. The method comprises the steps of transmitting a plurality of control bits in each of a plurality of control frames, wherein a first sequence of the control bits represents a transmission mode, and a second sequence of the control bits represents a control data synchronization word. The plurality of control bits can further include a third sequence of bits representative of an interleaver synchronization word. A method performed in a radio receiver for determining transmission mode and synchronization for a digital audio broadcasting signal is also provided. The method comprises the steps of receiving a plurality of interleaver frames containing digital information, wherein each of the interleaver frames includes a plurality of control frames.

Abstract: After a pseudo synchronizing information is detected and a synchronization is lost, an arithmetic operation unit adds a random number outputted from a random number generator to a frame length information calculated. The detection of a synchronizing information is again executed in a stream counter to a bit stream of a plurality of continuous transmission data, from a bit located in delay for the bit of output information being a calculation result by the arithmetic operation unit. The frame synchronous circuit thus constructed achieves a synchronization setup securely in a high speed, if a transmission data containing a pseudo synchronizing information is transmitted.

Abstract: In order to obtain a digital radio communication receiver having a preferable frame-structure decision probability, a frame synchronization state is decided in accordance with separately detected frame-synchronization synchronous words and a frame-structure is decided in accordance with a frame-structure synchronous word and to output the frame synchronization state and the frame structure.

Abstract: There is provided a synchronization acquiring circuit for stably acquiring frame synchronization without pseudo-synchronization lock when the frame synchronization is acquired in reception at the time of a low C/N. The synchronization pattern of a received frame is detected by a frame synchronization detecting circuit 2. The bits of the synchronization pattern of the received frame are compared with those of a frame synchronization pattern on the transmitting side by a frame synchronizing circuit 5 to obtain the number of coincided bits. The frame synchronization is regarded as detected when the obtained number of bits of each frame is equal to or larger than the correlation detection value.

Abstract: A method of simple network synchronization in a bus extension system with expanded capabilities wherein a plurality of independently-operable multimedia multiplexing devices are connected to the same network in parallel. The method of network synchronization for multiplexing devices connected by parallel through an extension bus is provided wherein one of two or more multiplexing devices is used as a clock master and other remaining multiplexing devices as slave devices and wherein the multiplexing device acting as the clock master is operated in synchronization with a clock received from a network while the multiplexing devices acting as the slave devices receive a clock from a clock transmission line of the extension bus which is outputted after the clock master has established synchronization with the network clock and regenerate a clock leading the received clock in phase.

Abstract: A data sync signal detecting device for detecting a sync signal having sync signal detection errors. The detecting device applies the output data of a most-likelihood decoder to shift register bit cells. The data is sequentially shifted and held in the bit cells of the shift register. The bit cell outputs are separated into odd-numbered and even-numbered bit string and applied to first and second pattern matching circuits. The odd-numbered bit string is matched with “01001” by a first pattern matching circuit. The even-numbered bit string is matched with “01011” by a second pattern matching circuit. First and second matching results are applied to a coincidence number adder/majority decision circuit. When coincidence occurs, the matching result is “1”, and when non-coincidence occurs, the matching result is “0”.

Abstract: A modem system includes a programmable synchronization signal format that can be configured at a first modem in response to a request received from a second modem. The synchronization signal format may define a number of parameters of the synchronization signal, such as the sign pattern for symbols transmitted by the first modem during a training sequence. The specific parameters of the synchronization signal format may be associated with the design and operation of the second modem. For example, the particular timing recovery and automatic gain control schemes used by the receiver portion of the second modem may be optimally initialized with a synchronization signal having a specific length, amplitude, or spectrum. In one embodiment, a synchronization signal is configured to convey a single frequency tone for use during a synchronization routine. The modem system may also employ similar techniques to generate, transmit, and analyze a programmable line impairment learning signal.

Abstract: A reception synchronization circuit for receiving a unique word transmitted in a predetermined digital pattern. A detection circuit detects the reception electric field intensity as received power. A UW correlation judgment circuit detects the unique word (hereinafter referred to as “UW”) and takes a correlation between the unique word thus detected and a predetermined digital pattern. A memory stores two or more threshold values for the movement average. After the two or more threshold values and the movement average are compared with each other, the correlation is taken by the UW correlation judgment circuit when the movement average is larger than the minimum values of the two or more threshold values.

Abstract: A system for detecting a burst in a wireless communications system. A signal strength indicator indicates the strength of an incoming signal representative of incoming packets. A signal strength change detector detects changes in the signal strength of the incoming signal. Signal strength detection logic determines if a change in signal strength of a predetermined magnitude has occurred. A pattern detector detects patterns of symbols, or symbol estimates, in the incoming signal to determine if a predetermined pattern of symbols is present. Burst detection logic signals detection of a burst if the signal strength detection logic determines that a change in signal strength of predetermined magnitude has occurred, and the pattern detector determines that a predetermined pattern of symbols is present.

Abstract: A TDMA system in which the mobile receiver performs unique word detection (and hence frame synchronization) by using real correlation coefficients which are not equal to the binary unique word (nor to any shift or scaling of it), but which are dependent on the unique word. In some embodiments, the correlation coefficients are dependent both on the unique word and also on the bit_sync pattern.

Abstract: A data sync signal detecting device for detecting a sync signal having sync signal detection errors. The detecting device applies the output data of a most-likelihood decoder to shift register bit cells. The data is sequentially shifted and held in the bit cells of the shift register. The bit cell outputs are separated into odd-numbered and even-numbered bit string and applied to first and second pattern matching circuits. The odd-numbered bit string is matched with “01001” by a first pattern matching circuit. The even-numbered bit string is matched with “01011” by a second pattern matching circuit. First and second matching results are applied to a coincidence number adder/majority decision circuit. When coincidence occurs, the matching result is “1”, and when non-coincidence occurs, the matching result is “0”.

Abstract: Burst transmissions in a burst-type communication system include a preamble synchronization sequence which allows detection and synchronization a burst transmission while at the same time providing information to a receiver, for example, on the subsequent burst payload data. Each burst transmission includes a preamble synchronization sequence which is one of a plurality of predetermined allowed preamble sequences in the system, according to the information desired to be transmitted. The system may also use differential encoding and decoding to eliminate the effects of frequency uncertainty. In that case, the allowed preamble sequences may be such that, after differential decoding, they differ from one another only by a polarity inversion such that a single matched filter may be used to detect two preamble sequences.

Abstract: A data recording and reproducing apparatus for recording and reproducing video signals in a plurality of formats with different rates to/from a record medium is disclosed. In the data recording and reproducing apparatus, a video signal in a selected format is converted into video data packets and audio data packets whose lengths are optimally designated corresponding to the selected format. With a video data packet and an audio data packet, a video sync block and an audio sync block whose lengths are different are formed, respectively. The video sync block and the audio sync block are encoded with respective error correction codes. The resultant data is recorded as record data to a record medium. Corresponding to the data rate of the video signal, at least one data packet is placed in one video sync block. A synchronization detecting apparatus automatically and accurately detects sync blocks with different lengths from a data sequence of record data reproduced from a record medium.

Abstract: In a communication system including a transmitter and a receiver, the receiver is synchronized with the transmitter, and a modulation type in a signal transmitted by the transmitter and received by the receiver is detected. A first portion of the received signal is correlated with one or more signals representing modulation types used by the communication system to detect the type of modulation being used in the received signal. Synchronization is established between the transmitter and the receiver. The first portion may be correlated with each of one or more different signals representing various modulation types used in the communication system to detect the type of modulation used. Alternately, the first portion of the received signal may be derotated by different amounts to produce a plurality of derotated signals that are correlated with the signal representing modulation used by the communication system in order to detect the type of modulation used.

Abstract: Systems and methods for locating a known multi-symbol syncword in a received signal are disclosed, wherein a potential syncword is located in a first batch of samples of the received signal which has a correlation energy with the known syncword which exceeds a first detection threshold. A correlation energy with the known syncword for a group of samples in a second batch of samples of the received signal is determined, where the group of samples in the second batch of samples are selected based on the location of the potential syncword within the first batch of samples. The correlation energy associated with the group of samples in the second batch of samples is compared with a second detection threshold that is higher than the first detection threshold. The location of the known syncword may be identified based upon the comparison of the correlation energy associated with the group of samples in the second batch of samples with the second detection threshold.

Abstract: A data recovery device for precisely recovering a transmission signal even if the signal having phase variations is provided. The device comprises a demodulator for demodulating a transmission signal, a plurality of symbol recovery units, each generating a corresponding synchronous signal and a lock signal, wherein the lock signals are selectively enabled to select one of the synchronous signals, based on pattern variations of the transmission signal detected by the symbol recovery units, and a data decision unit for performing a data recovery operation using the selected synchronous signal to recover original data of the transmission signal.

Abstract: A status phase processor for a data pattern recognizer or correlator provides an optimized synchronization signal. The synchronization signal can be utilized to adjust the data sampling clock. The data pattern correlator utilizes two or more samples per symbol of the signal which is expected to be received. The system provides high accuracy correlation without significant hardware and software overhead. The status phase processor relies on a counter circuit and a logic circuit for generating the synchronization signal.

Abstract: A data modulation method and a data modulation device and a communication device are disclosed. The present invention relates to the synchronization and training preamble. The reference symbol optimized in order to contain the structure of “IA-A-IA-A-A-IA-A-IA-IA” is allocated to sub-carriers of the OFDM symbol. More specifically, by designing the structure of the preamble of the time domain, distinction from the other communication system can be certainly conducted holding the correctness of the clock synchronization. Also, we have adopted the series having low peak average ratio and dynamic range of sync symbol using the OFDM. Since the generation and the detection processings can be conducted in utilizing the generation device and the detection device of the sync preamble used in the convention system, this system has an advantage in increasing the common use of the LSI chip.

Abstract: Methods and apparatus for feature recognition time shift correlation are presented. An exemplary method includes the step of identifying a feature in an input data stream. A starting time associated with the identified feature relative to a boundary of the input data stream is stored. A time interval until the identified feature is next repeated in the input data stream is then measured. Next, the measured time interval is compared to each of a set of valid interval values for the identified feature. A difference is then calculated between the stored starting time and a starting time associated with the identified feature relative to a boundary of a reference data sequence when the measured time interval matches one of the valid interval values. The calculated difference determines an amount that the input data stream must be time-shifted to achieve correlation with the reference data sequence.

Abstract: A method is disclosed for receiving a transmitted signal in a communication system employing CDMA techniques wherein the transmitted signal includes a plurality of short codes, each of which is transmitted repetitively over a fixed period of time and where the received signal has CW interference in addition to the transmitted signal. The method includes using a Sequential Ratio Probability Test (SPRT) for detecting the presence of the short code in a plurality of time phases of the received signal by calculating a likelihood ratio for each phase. A likelihood ratio is a comparison of the signal's Probability Distribution Function (PDF) with a background noise PDF. The background noise PDF is calculated by combining in the RAKE the current short code with the input signal.

Abstract: A device for identifying a determined repetitive sequence of predetermined signals arriving on a modem. The device includes a delay circuit so that all the words of a sequence are simultaneously present; a combination circuit for providing a combined word; a circuit for calculating the modulus of each combined word and for comparing this modulus with a threshold; a circuit for counting clock pulses corresponding to the rate at which words arrive; a circuit for inhibiting the counting circuit when the modulus of the combined word is lower than the threshold; and a circuit for providing an identification signal when a predetermined number of clock signals is counted.