Abstract: Techniques are provided for handling positioning sessions in response to a timing source outage. An example method for configuring a positioning method based on a timing source outage includes receiving an indication of the timing source outage from a station, determining the positioning method based at least in part on the indication of the timing source outage, and sending an indication of the positioning method to one or more network entities.

Abstract: A clock and data recovery circuit includes a phase detector (PD), a phase frequency detector (PFD), a multiplexer circuit, a conversion stage and an oscillator. The PD detects a difference in phase between a data signal and an oscillating signal to generate a first set of error signals. The PFD detects a difference in phase and frequency between a reference clock signal and the oscillating signal to generate a second set of error signals. The multiplexer circuit selectively outputs the first set of error signals or the second set of error signals as a third set of error signals according to a selection signal. The conversion stage determines a set of gains according to the selection signal, and converts the third set of error signals with the set of gains to generate a set of input signals. The oscillator generates the oscillating signal according to the set of input signals.

Abstract: A clock and data recovery circuit includes a first sampling phase detector and filter circuitry, a frequency detector circuit, a current source circuit, a band controller circuit, and a voltage controlled oscillator. The first sampling phase detector and filter circuitry generates a first voltage according to a pair of data and a first set of clock signals. The frequency detector circuit generates an up control signal and a down control signal according to the pair of data and the first set of clock signals. The current source circuit generates the first voltage according to the up control signal and the down control signal. The band controller circuit generates a band control signal according to the first voltage. The voltage controlled oscillator adjusts the first set of clock signals according to the band control signal and the first voltage.

Abstract: Techniques for estimating a phase relation between a first binary signal and a second binary signal, in particular to a clock-to-data phase detection in double-data-rate signals. The binary signals may include both rising and falling signal edges. Techniques may include determining a first and second signal edge for the first binary signal and comparing the signal edges of the first binary signal to one or more signal edges of the second binary signal, then performing one or more calculations based on the comparisons. The phase relation between the first binary signal and the second binary signal may be determined based on the one or more calculations.

Abstract: An analog-to-digital converter for converting a pixel signal generated from sensed light into a digital signal includes a comparator configured to compare the pixel signal with a ramp signal having a constant slope to generate a comparison signal; a delay circuit configured to generate a first signal corresponding to the comparison signal, the delay circuit including a plurality of delay elements configured to generate a second signal by delaying the first signal by a first time period; and a compensator circuit configured to measure a period of the comparison signal to output a delay select signal to the delay circuit based on the measured period, the delay select signal delaying the first signal by the first time period, wherein the first time period is obtained by dividing the period of the comparison signal.

Abstract: Apparatuses, systems, ambient RF backscatter transceivers, and methods for communicating using MIMO and spread spectrum coding of backscattered ambient RF signals are described. An example system may include an ambient RF backscatter transceiver that include an antenna configured to receive a backscattered ambient radio frequency (RF) signal, and a receiver coupled to the antenna. The receiver may be configured to demodulate the backscattered ambient RF signal using one of multiple input, multiple output multiplexing demodulation or spread spectrum code demodulation to retrieve the first data. The backscattered ambient RF signal may be generated by backscattering an ambient RF signal at a first frequency. The ambient RF signal may be configured to provide other data at a second frequency.

Abstract: Apparatuses, systems, ambient RF backscatter transceivers, and methods for communicating using MIMO and spread spectrum coding of backscattered ambient RF signals are described. An example system may include an ambient RF backscatter transceiver that include an antenna configured to receive a backscattered ambient radio frequency (RF) signal, and a receiver coupled to the antenna. The receiver may be configured to demodulate the backscattered ambient RF signal using one of multiple input, multiple output multiplexing demodulation or spread spectrum code demodulation to retrieve the first data. The backscattered ambient RF signal may be generated by backscattering an ambient RF signal at a first frequency. The ambient RF signal may be configured to provide other data at a second frequency.

Abstract: A time-to-digital converter includes a clock signal generation circuit that generates a first cycle signal having a voltage level that monotonously increases or decreases in a cycle corresponding to the clock frequency of a reference clock signal and further generates a first clock signal based on a first signal and the first cycle signal, a clock signal generation circuit that generates a second cycle signal having a voltage level that monotonously increases or decreases in a cycle corresponding to the clock frequency of a reference clock signal and further generates a second clock signal based on a second signal and the second cycle signal, and a processing circuit that converts a time difference between the transition timing of the first signal and the transition timing of the second signal into a digital value based on the first and second clock signals.

Abstract: Apparatuses, systems, ambient RF backscatter transceivers, and methods for communicating using MIMO and spread spectrum coding of backscattered ambient RF signals are described. An example system may include an ambient RF backscatter transceiver that include an antenna configured to receive a backscattered ambient radio frequency (RF) signal, and a receiver coupled to the antenna. The receiver may be configured to demodulate the backscattered ambient RF signal using one of multiple input, multiple output multiplexing demodulation or spread spectrum code demodulation to retrieve the first data. The backscattered ambient RF signal may be generated by backscattering an ambient RF signal at a first frequency. The ambient RF signal may be configured to provide other data at a second frequency.

Abstract: Apparatuses, systems, ambient RF backscatter transceivers, and methods for communicating using MIMO and spread spectrum coding of backscattered ambient RF signals are described. An example system may include an ambient RF backscatter transceiver that include an antenna configured to receive a backscattered ambient radio frequency (RF) signal, and a receiver coupled to the antenna. The receiver may be configured to demodulate the backscattered ambient RF signal using one of multiple input, multiple output multiplexing demodulation or spread spectrum code demodulation to retrieve the first data. The backscattered ambient RF signal may be generated by backscattering an ambient RF signal at a first frequency. The ambient RF signal may be configured to provide other data at a second frequency.

Abstract: An example burst mode clock data recovery circuit may include a clock recovery circuit coupled to receive a plurality of data signals, and provide a recovered clock signal in response. Each of the plurality of data signals includes data and an embedded clock signal, and the plurality of data signals may be based on an encoded symbol. The clock recovery circuit is coupled to generate the recovered clock signal in response to a first one of the plurality of data signals. A data recovery circuit may be coupled to receive the plurality of data signals and the recovered clock signal, and provide a plurality of recovered data signals in response to the recovered clock signal. The data recover circuit is coupled to delay each of the plurality of data signals, and capture each of the delayed plurality of data signals in response to the at least one clock pulse.

Abstract: System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.

Abstract: A method and apparatus of clock recovery is disclosed. A communications device matches the frequency of a local clock signal with the frequency of a transmit clock signal of a transmitting device based on a first set of signals received from the transmitting device during a low-speed information exchange. The low-speed information exchange may correspond to an autonegotiation operation, wherein each of the transmitting device and the communications device declares its communication capabilities to the other device. The communications device then determines a frequency offset to be applied to the local clock signal during a high-speed data communication with the transmitting device. During the high-speed communication, the communications device may apply the frequency offset to the local clock signal and match the phase of the receive clock signal with the phase of the transmit clock signal based on a second set of signals received from the transmitting device.

Abstract: A clock and data recovery circuit may include: a phase detection unit configured to generate an early phase detection signal and a late phase detection signal by comparing a clock signal and data; a filtering unit configured to generate an up signal and a down signal based on a number of generation times of the early phase detection signal and a number of generation times of the late phase detection signal; a phase information summing unit configured to receive an output of the filtering unit at each cycle of the clock signal, and generate first and second phase control signals by summing up numbers of the up signals and the down signals received from the filtering unit during a summing-up time; and a phase interpolator configured to adjust a phase of the clock signal according to the first and second phase control signals.

Abstract: Systems and methods for tuning a voltage are described herein. In one embodiment, a method comprises sending a data signal to first and second flops via a data path, latching in the data signal at the first flop using a clock signal, and latching the data signal at the second flop using a delayed version of the clock signal. The method also comprises detecting a mismatch between outputs of the first and second flops, and adjusting the voltage based on the detected mismatch.

Abstract: A low power data retiming circuit incorporates CMOS components in certain sections that operate at a lower frequency in comparison to certain other sections that use components based on bipolar technology for operating at a relatively higher frequency. The data retiming circuit includes a clock recovery circuit wherein a voltage controlled oscillator provides a recovered clock to a clock generator circuit for generating a latched clock that is provided to a phase detector and a data serializer. The data serializer operates as a synchronous multiplexer for generating a retimed data output signal from a pair of latched data input signals. The phase detector and the data serializer operate in a half-rate mode wherein high and low voltage levels of the latched clock are used for clocking data. The half-rate mode of operation permits the use of a clock frequency that is half that of an input data rate.

Abstract: Methods and apparatus including a latency control circuit are described. An example apparatus includes a delay line circuit configured to delay a clock signal, and a latch control circuit configured to receive the clock signal and the delayed clock signal. The latch control circuit is configured to provide first control signals based on a count associated with the first clock signal. The latch control circuit is further configured to provide second control signals based on the count associated with the first clock signal. The second clock signals are delayed relative to the first clock signals by an amount substantially equal to a delay between the clock signal and the delayed clock signal. The example apparatus further includes a latch circuit configured to latch an input signal responsive to the first control signals. The latch circuit is further configured to provide the latched signal to an output responsive to the second control signals.

Abstract: Embodiments for reference-less voltage controlled oscillator (VCO) calibration are provided. Embodiments include a VCO calibration module which uses one or more signals from a frequency detector to automatically select a proper VCO band and bring the VCO clock frequency close enough to the data rate. The VCO calibration module uses a calibration code to calibrate the VCO. In embodiments, the calibration code is determined using a frequency search scheme, which includes a discovery phase to determine the proper VCO band, and a binary search phase and a monitoring phase to select the calibration code that brings the VCO clock frequency closest to the data rate.

Abstract: A half-rate clock and data recovery (CDR) circuit includes a first and a second gated voltage-controlled oscillators (GVCOs) and a first and a second frequency detectors. The first frequency detector generates a first output current according to a reference signal and a second divided clock, and the second frequency detector generates a second output current according to a first divided clock and the second divided clock. A loop filter converts either the first output current or the second output current to a first control voltage to control the second clock, and generates a second control voltage according to the first control voltage to control the first clock. A lock detector receives the reference signal and the second divided clock, and accordingly generates a lock signal.

Abstract: A method and a system are described for controlling and stabilizing in time, as temperature changes, the frequency of a signal generated by a controllable oscillator (3), the method includes the steps of: measuring the frequency of the signal generated by the controllable oscillator (3) by using a first signal, whose duration is proportional to the length of a delay line (5) includes at least a first (7) and a second (9) delay line portions arranged in series and having a first (L1) and a second (L2) lengths, respectively; applying a frequency correction to the signal generated by the controllable oscillator (3) if the difference in frequency between the signal and the desired frequency value exceeds a predetermined threshold; providing the first portion of the delay line (5) by coupling a conductive material to a first dielectric material having a first negative gradient of its dielectric constant as a function of temperature; providing the second portion (9) of the delay line (5) by coupling or another cond

Abstract: A control method utilized in a clock data recovery device supporting a plurality of frequency bands, for controlling the clock data recovery device to select an operating frequency band from the plurality of frequency bands and to generate a recovery clock for generating retimed data, includes receiving a serial data stream with a data frequency; making each frequency band of the plurality of frequency bands correspond to a plurality of frequency band groups, wherein each frequency band group includes at least one frequency band and corresponds to different frequency ranges; selecting a frequency band group from the plurality of frequency band groups as a coarse-tuned frequency band group according to the data frequency and a locking voltage range; and selecting a frequency band from the plurality of frequency bands according to the data frequency, the locking voltage range and the coarse-tuned frequency band group for generating the recovery clock.

Abstract: Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.

Abstract: A phase-frequency detector (PFD) circuit is disclosed. The PFD circuit includes a PFD portion adapted to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference and a delay and reset portion adapted to delay the generated control signals, to generate reset signals for resetting the PFD portion based on a combination of the control signals and the delayed control signals, and to provide the generated reset signals to the PFD portion.

Abstract: A method and system is includes configurable carrier phase noise shaping. A fractional phase locked loop (PLL) uses a bank of delta-sigma modulators (DSM) to generate fractional ratios of the reference signal frequency. The bank of delta-sigma modulators provides for dynamic adjustments in the fractional PLL based phase noise performance of the communications network. The bank of DSMs is designed such that they have different and conflicting phase noise profiles. The communication network parameters are monitored and utilized for selecting a specific DSM from the bank of DSMs which most closely resembles a desired communications network phase noise profile.

Abstract: Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.

Abstract: Disclosed is a receiving circuit which includes: a data selection circuit selecting two input data located while placing in between the center phase of one unit interval of a binary input data; a correction circuit correcting the two input data selected by the data selection circuit; a phase detection circuit detecting a phase at which the level of input data changes as a boundary phase in the one unit interval, based on the two input data corrected by the correction circuit; an arithmetic unit calculating the center phase, based on the boundary phase detected by the phase detection circuit; and data decision circuit determining and outputting the level of one of the two input data, based on the center phase and the boundary phase, the correction circuit implements the correction based on a correction value corresponded to the past data level output by the data decision circuit.

Abstract: Systems and methods for stabilizing clock data recovery (CDR) by filtering the abrupt phase shift associated with data pattern transition in the input signal. The CDR circuit includes a data pattern detector coupled to a data pattern filter. The data pattern detector is capable of detecting the data patterns of the input signal. Accordingly, the data pattern filter can selectively generate a filter indication indicating to freeze or suppress the CDR phase caused by data pattern transition. The filter indication can be incorporated to a phase error signal, a gain function, and/or the control voltage driving the VCO.

Abstract: A frequency locking system for locking a clock frequency in a CDR circuit without crystal oscillator is provided. Reference data information is inputted into a first low-pass filter; the first low-pass filter is connected to a first swing detector; the first swing detector is connected to a non-inverting terminal of a comparator; an output terminal of the comparator is connected to a charge pump; the charge pump is connected to a first terminal of a capacitor; the capacitor is grounded. The capacitor is also connected to a voltage-controlled oscillator; the voltage-controlled oscillator is connected to a code pattern conversion generator; the code pattern conversion generator is connected to of a second low-pass filter; the second low-pass filter is connected to an input terminal of a second swing detector; an output terminal of the second swing detector is connected to an inverting terminal of the comparator.

Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock.

Abstract: The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.

Abstract: A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. The CDR circuit further includes a delay locked loop (DLL) configured to receive the clock signal from the LCVCO and generate multiple clock phases and a first charge pump configured to control the LCVCO. The CDR circuit further includes a phase detector configured to receive a data input and the multiple clock phases from the DLL, and to align a data edge of the data input and the multiple clock phases.

Abstract: A system and method are provided for determining a time for safely sampling a signal of a dock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first dock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.

Abstract: A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a phase and frequency detector driving a charge pump and a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit increases the charge pump current above a nominal current value during the closed loop curve search operation and set the charge pump current to the nominal current value after an operating curve is selected.

Abstract: In one embodiment, a method includes adjusting a first frequency of a first clock signal based on a frequency difference between the first frequency and a reference clock signal frequency of a reference clock signal, and further adjusting the first frequency and a first phase of the first clock signal based on a phase difference between the first clock signal and an input data bit stream and the frequency difference between the first frequency and the reference clock signal frequency to substantially lock the first frequency and the first phase of the first clock signal to the input data bit frequency and input data bit phase of the input data bit stream.

Abstract: Methods and apparatus are provided for determining one or more channel compensation parameters based on data eye monitoring. According to one aspect of the invention, a method is provided for evaluating the quality of a data eye associated with a signal. The received signal is sampled for a plurality of different phases, for example, using at least two latches, and the samples are evaluated to identify when the signal crosses a predefined amplitude value, such as a zero crossing. It is determined whether the points of predefined amplitude crossing satisfy one or more predefined criteria. One or more parameters of one or more channel compensation techniques can optionally be adjusted based on a result of the determining step. One or more parameters of an adjacent transmitter can also be adjusted to reduce near end cross talk based on a result of the determining step.

Abstract: A system and method are provided for resynchronizing a transmission signal using a jitter-attenuated clock derived from an asynchronous gapped clock. A first-in first-out (FIFO) memory accepts an asynchronous gapped clock derived from a first clock having a first frequency. The gapped clock has an average second frequency less than the first frequency. The input serial stream of data is loaded at a rate responsive to the gapped clock. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock, averaged, and an averaged numerator (A and an averaged denominator (AD) are generated. The first frequency is multiplied by the ratio of AN/AD to create a jitter-attenuated second clock having the second frequency. The FIFO memory accepts the jitter-attenuated second clock and supplies data from memory at the second frequency. A framer accepts the data from the FIFO memory and the jitter-attenuated second clock.

Abstract: An output signal adjustment system includes a signal adjustment unit, a reference slope generating unit, a slope detecting unit, a voltage-to-current conversion unit, and a control unit. The slope detecting unit compares the slope of the rising and falling edges of the output signal of the reference slope generating unit with that of the signal adjustment unit and outputs a voltage signal. The voltage-to-current conversion unit converts the voltage signal into a current signal. Based on the current signal, the control unit outputs a control signal for controlling the adjustment of the signal adjustment unit to the slope of the rising and falling edges of the output signal. The output signal adjustment system can automatically adjust the slope of the rising and falling edges of the output signal, so that the output signal is insensitive to the packaging, the printed circuit board, the transmission line and other sender loads.

Abstract: An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.

Abstract: In order to provide an interface circuit (100; 100?) as well as a method for receiving and/or for decoding, in particular for recovering, data signals (D; R, G, B), in particular high speed data signals, for example high speed sequential digital data signals, wherein at least one sampling clock signal (SC), in particular at least one multi-phase sampling clock signal (PC[n-1:0]) with n different phases, and/or the data signals (D; R, G, B) are delayed, and wherein it is possible to optimize the components, in particular the analog components, for a fixed operating frequency, it is proposed that the sampling clock signal (SC), in particular the multi-phase sampling clock signal (PC[n-1:0]), is asynchronous—to at least one interface clock signal (IC), by which the interface circuit (100; 100?), in particular the input of the interface circuit (100; 100?), can be provided with, and/or to the data signals (D; R, G, B).

Abstract: A method for frequency acquisition comprising steps of, acquiring samples of an input signal, each sample having edges, making sets with a fixed number of consecutively taken samples, numbering the edges in each set and determining a number of edges, comparing the number of edges in each set with an expected number of edges in the sets, increasing a frequency of a reference oscillator used in acquiring samples if the actual number of edges exceeds the expected number of edges, and decreasing the frequency of the reference oscillator used in acquiring samples if the expected number of edges exceeds the actual number of edges in a set.

Abstract: A system includes a memory controller and a plurality of semiconductor devices that are series-connected. Each of the devices has memory core for storing data. The memory controller provides a clock signal for synchronizing the operations of the devices. Each device includes a phase-locked loop (PLL) that is selectively enabled or disabled by a PLL enable signal. In each group, the PLLs of a selected number of devices are enabled by PLL enable signals and the other devices are disabled. The enabled PLL provides a plurality of reproduced clock signals with a phase shift of a multiple of 90° in response to an input clock signal. The data transfer is synchronized with at least one of the reproduced clock signals. In the devices of disabled PLLs, the data transfer is synchronized with the input clock signal. The enabled PLL and disabled PLL cause the devices to be the source and the common synchronous clocking, respectively. The devices can be grouped.

Abstract: Circuit and method for resetting clock circuitry. The circuit includes a chain of cascading units, each of which receives an input of a number of parallel bit streams and outputs a different number of parallel bit streams. A chain of dividers provides one or more divided clock signals to the cascading units, wherein the divided clock signals are based on a gated common clock signal. An asynchronous reset signal is delivered to the dividers, and when asserted sets the dividers to a reset state. A clock source provides an ungated common clock signal. A clock gating circuit generates the gated common clock signal based on the ungated common clock signal, and is configured to hold the gated common clock signal while the asynchronous reset signal is asserted. The clock gating circuit provides the gated common clock signal to the dividers when the asynchronous reset signal is de-asserted.

Abstract: Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.

Abstract: A frequency calibration apparatus and method are provided. A frequency calibration method includes determining a frequency band according to results of frequency comparisons between a synchronized reference signal whose phase is synchronized to a phase of a prescale signal and a divided signal, and performing a Phase Locked Loop (PLL) operation on a reference signal and the divided signal at the determined frequency band to lock the divided signal.

Abstract: A frequency synthesizer and a frequency synthesis method thereof are provided. The frequency synthesizer includes a phase-locked loop unit, a voltage-controlled oscillating unit, and a frequency mixing unit. The phase-locked loop unit receives a reference signal and a feedback injection signal and generates a first oscillating signal according to the reference signal and the feedback injection signal. The voltage-controlled oscillating unit receives the feedback injection signal and generates a second oscillating signal according to the feedback injection signal. The frequency mixing unit is coupled to the phase-locked loop unit and the voltage-controlled oscillating unit, receives the first oscillating signal and the second oscillating signal, and mixes the first oscillating signal and the second oscillating signal to generate the feedback injection signal and an output signal.

Abstract: A phase locked loop circuit includes a phase frequency detector, a control circuit, a charge pump, a loop filter, a supply circuit, a ring oscillator, a frequency divider and a voltage detector. The phase frequency detector generates a frequency-increasing signal and a frequency-decreasing signal according to a phase difference between an input signal and a feedback signal. The control circuit generates a first control signal and/or a second control signal according to the frequency-increasing signal and the frequency-decreasing signal. The charge pump generates a current signal according to the first control signal and/or the second control signal. The voltage detector monitors a supply voltage of the supply circuit, and controls the control circuit to generate only the second control signal so as to reduce the supply voltage if the supply voltage is greater than a high reference voltage.

Abstract: A control method utilized in a clock data recovery device supporting a plurality of frequency bands, for controlling the clock data recovery device to select an operating frequency band from the plurality of frequency bands and to generate a recovery clock for generating retimed data, includes receiving a serial data stream with a data frequency; making each frequency band of the plurality of frequency bands correspond to a plurality of frequency band groups, wherein each frequency band group includes at least one frequency band and corresponds to different frequency ranges; selecting a frequency band group from the plurality of frequency band groups as a coarse-tuned frequency band group according to the data frequency and a locking voltage range; and selecting a frequency band from the plurality of frequency bands according to the data frequency, the locking voltage range and the coarse-tuned frequency band group for generating the recovery clock.

Abstract: A clock and data recovery circuit is disclosed. The clock and data recovery circuit in accordance with an embodiment of the present invention uses a hybrid phase detector that is constituted by including a linear phase detector and a binary phase detector. Since the clock and data recovery circuit basically is constituted with the linear phase detector, a charge pump, a loop filter, a voltage controlled oscillator and a D flip flop to recover clock and data, a phase detector gain is irrelevant to the jitter of received data and recovered clock, and it is possible to make a fine adjustment of the size of up/down currents of the charge pump using the binary phase detector and a charge pump controller, thereby compensating a phase offset between the received data and the recovered clock.

Abstract: A clock data recovery circuit includes a phase detector circuit, a majority voter circuit, and a phase shift circuit. The phase detector circuit is operable to compare a phase of a periodic signal to a phase of a data signal to generate a phase error signal. The majority voter circuit includes a shift register circuit. The shift register circuit is operable to generate an output signal based on the phase error signal. The majority voter circuit is operable to generate a majority vote of the phase error signal based on the output signal of the shift register circuit. The phase shift circuit is operable to set the phase of the periodic signal based on the majority vote generated by the majority voter circuit.

Abstract: A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK1) having a first clock frequency to generate a second clock signal (CLK20) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK1), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK1) to generate a plurality of shifted clock signals (CLK 21, . . . , CLK32) at respective data outputs of the plurality of flip-flops.