Abstract: The present invention relates to a detector arrangement and a charge pump circuit for a recovery circuit recovering timing information for random data. The detector arrangement comprises a first latch circuit for sampling a quadrature component of a reference signal based on an input signal, to generate a first binary signal, a second latch circuit for sampling an in-phase component of the reference signal based on the input signal, to generate a second binary signal, and a third latch circuit for sampling the first binary signal based on the second binary signal, to generate a frequency error signal. Furthermore, the charge pump circuit comprises a differential input circuit and a control circuit for controlling a tail current of the differential input circuit in response to a frequency-locked state of frequency detector arrangement.

Abstract: A phase locked loop and method thereof are provided. The example phase locked loop may include a loop filter filtering a charge pump output signal to generate a voltage signal and a voltage-controlled oscillator configured to operate in a given one of a plurality of frequency zones, the given frequency zone within which the voltage-controller oscillator is operating in being based on a voltage level of the voltage signal, the voltage-controlled oscillator outputting an oscillator signal at a frequency corresponding to the voltage level of the voltage signal output from the loop filter. The example method may include filtering a charge pump output signal to generate a voltage signal and outputting an oscillator signal at a frequency corresponding to a voltage level of the voltage signal, the frequency of the oscillator signal based on which of a plurality of frequency zones is currently selected, the currently selected frequency zone being selected based on the voltage level of the voltage signal.

Abstract: A dual path loop filter circuit for a phase lock loop is described. The filter circuit allows the filter to be integrated into a phase lock loop IC circuit without using active circuit components that may create additional noise and consume additional power. The filter circuit structure allows for a low capacitance capacitor to be used to filter out any undesired signals.

Abstract: A two-point frequency modulation apparatus is proposed whereby the spectrum of transmission waves is kept within the spectrum mask. Voltage is supplied to the control voltage terminal of VCO 1 in accordance with modulation data via noise shaper 101 that has operating characteristics of attenuating more noise at higher frequencies. As a result, by virtue of the working of noise shaper 101, the signal level outputted from the PLL circuit combining the modulation signal and the quantization noise decreases in proportion to the distance form the central frequency, so that two-point frequency modulation apparatus 100 is made possible whereby the spectrum of an RF modulation signal is kept within the spectrum mask.

Abstract: A method and apparatus for recovering data by a digital audio interface begins by receiving a stream of biphase encoded data. The processing continues by determining whether a next transition of a frame of the plurality of frames occurs during a first, second, or third time window after a preceding transition of the frame. When the next transition occurs during the second predetermined time, the digital audio interface synchronizes to a data rate of the stream of biphase encoded data based on the next transition and the preceding transition. If, the next transition occurs during the first or third predetermined windows, the digital audio interface synchronizes to a data rate of the stream of biphase encoded data based on the preceding transition edge and a subsequent transition. When the transition occurs during the third time window, the biphase encoding is violated, which indicates that a preamble is being received.

Abstract: In one embodiment, a circuit includes a voltage-controlled oscillator (VCO) configured to generate k first clock signals that each have a first phase based on a charge-pump control voltage signal; one or more phase interpolators (PIs) configured to receive the k first clock signals and one or more first feedback controls signals and generate m second clock signals that each have a second phase based on the k first clock signals and the one or more first feedback control signals; a first phase detector (PD) configured to receive the m second clock signals and generate the one or more first feedback control signals based on the m second clock signals; a second PD configured to generate one or more second feedback control signals based on the m second clock signals; and a charge pump configured to output the charge-pump control voltage signal based on the second feedback control signals.

Abstract: A receiver for a digital communication signal has a first decision gate (DGa), which has a first decision threshold (xd) for outputting a first decision signal, a second decision gate (DGb), which has a second decision threshold (xm) for outputting a second decision signal, a counter (CNT) for counting events where the first and second decision signals of the first and second decision gates (DGa, DGb) differ from each other, and a controller (PROC) capable of controlling the decision thresholds of said first and second decision gates in accordance with count values delivered by said counter. The controller (PROC) determines an initial decision threshold value by performing a statistical analysis of the received signal and setting the decision threshold such that the distribution of logical ‘0’ and logical ‘1’ in the decided signal corresponds to the expected distribution, which is in typically 50%/50%.

Abstract: A phase locked loop having reduced inherent noise is provided. The phase locked loop comprises a controlled oscillator for outputting a periodic output signal as a result of a control signal; a feedback unit for providing at least two periodic feedback signals having a constant phase shift to each other and each depending on the output signal; a phase/frequency detector for providing difference signals each depending on a periodic input signal and at least one of the feedback signals; and a control circuit for providing the control signal to the controlled oscillator depending on the difference signals.

Abstract: A timing recovery system and method for accelerated clock synchronization of remotely distributed electronic devices is provided. The system includes a phase locked loop, a linear estimator and control logic. The method includes sampling a clock signal received from an electronic device, applying a linear estimation technique to estimate the frequency and phase of the received signal and providing those estimates to a phase locked loop to accelerate the phase locked loop acquisition rate and secure signal lock quickly.

Abstract: A phase measurement circuit is described that receives a signal with irregularly spaced edges and assigns a numerical value to the phase of each edge. An interpolator provides linear interpolation between successive values to provide continuous phase values at smaller, regular intervals. The interpolated values are resampled at a lower, regular rate to simplify subsequent processing by filters or other data-reduction means. The interpolation is performed without dividers or two-variable multipliers.

Abstract: A technology capable of avoiding malfunction of a delay locked loop without generating a constant phase error in a delay locked loop circuit is provided. In a delay locked loop circuit, a control circuit is disposed in the outside of a delay locked loop, and in phase comparison of the delay locked loop, the control circuit outputs a control signal to the delay locked loop so that the relation in the phase comparison between a reference signal and an output signal is shifted by a set cycle.

Abstract: A phase locked loop (PLL) architecture provides voltage controlled oscillator (VCO) gain compensation across process and temperature. A simulator may be used to calculate the control voltages for the maximum and minimum output frequency of the VCO for each combination of the process and temperature corners. The maximum and minimum values of control voltage are then selected from these control voltages. Using a counter, the number of cycles of VCO in some cycles of the PLL input clock are counted in binary form and stored in latches for the extreme control voltages. The difference between them and the corresponding difference for typical process and temperature corner is used to modify the charge pump to change the current delivered to the loop filter. After the charge pump bits have been decided, the input control voltage of the VCO connects to the charge pump output to start the normal operation of the PLL.

Abstract: A phase rotator generates an output signal having plurality of possible output phases with reduced phase jitter. The low jitter phase rotator includes a plurality of differential amplifiers configured to receive a plurality of input differential signals having different phases, and configured to generate a plurality of weighted signals responsive to the plurality of input differential signals. A plurality of digital-to-analog converters (DAC) are arranged into a plurality of groups, each group of DACs configured to provide current for one of the corresponding differential amplifiers. The number of active DACs in each group of DACs determines a relative weighting of the weighted signals, where relative weighting determining an output phase of an output signal of the phase rotator. The DACs are configured to adjust the output phase of the phase rotator. At a kth phase, N/4 adjacent DACs are activated that are indexed as m0, m1, . . . m((N/4)?1), wherein N is the number of said plurality of DACs.

Abstract: An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.

Abstract: A method for automatically calibrating intra-cycle timing relationships between command signals, data signals, and sampling signals for an integrated circuit device. The method includes generating command signals for accessing an integrated circuit component, accessing data signals for conveying data for the integrated circuit component, and accessing sampling signals for controlling the sampling of the data signals. A phase relationship between the command signals, the data signals, and the sampling signals is automatically adjusted to calibrate operation of the integrated circuit device.

Abstract: A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.

Abstract: Techniques are provided for calculating a clock rate for a serial clock of a transmitter where information sent by the transmitter is sent in packets from the transmitter over an asynchronous network. The techniques involve minimizing the number of adjustments to the clock rate that are needed to fine tune the clock rate to match the serial clock of the transmitter.

Abstract: A dual loop, clock synchronization circuit for a receiver in a communication system. The circuitry uses a first loop of a digital phase lock loop for coarse synchronization to time stamps within the received data and uses a second loop for fine synchronization of a second numerically controlled oscillator.

Abstract: A phase locked loop includes a phase-frequency detector and a loop filter. The phase-frequency detector compares phases of an input signal and a feedback signal to generate first and second control signals. The loop filter includes a pull-up resistor, a pull-down resistor and a capacitance unit. The loop filter receives a first reference voltage to charge the capacitance unit through a path formed by the pull-up resistor to the capacitance unit, receives a second reference voltage to discharge the capacitance unit through a path formed by the pull-down resistor to the capacitance unit and outputs a control voltage generated based on a charge amount of the charged capacitance unit. Therefore, the phase locked loop can operate at a relatively low voltage and can operate based on a control voltage with a wide input range.

Abstract: A self-tuning 3rd order type III phase-locked loop (PLL) is disclosed. In one aspect, the PLL provides frequency control that is implemented in three (3) parallel paths. The PLL provides frequency response tracking using a number of elements including a triple control voltage-controlled oscillator (VCO), a frequency-to-current (F2I) converter, and a switched capacitor loop filter. In addition to compensation for feedback ratio variation, near constant F2I gain over process variations and switched capacitor filters synchronized to a reference signal, near constant VCO gain over process variations allows the open loop frequency response to be tailored to track the reference signal. A high-speed locking technique is employed which significantly reduces acquisition time in low bandwidth cases. This PLL may be fabricated in a 0.18 ?m CMOS logic process.

Abstract: A clock-data recovery circuit includes a phase rotator, a phase detector and a charge pump. The phase rotator receives first and second reference clocks and differential control signals. The phase rotator generates a modified clock signal responsive to the first and second reference clocks and the control signals. The phase detector receives a data signal and the modified clock signal. The phase detector generates a modified data signal and a phase error signal responsive to the data signal and the modified clock signal. The charge pump receives the phase error signal and generates the differential control signals, which direct the phase rotator to interpolate between select clock phases.

Abstract: A clock rate used in rendering broadcast streaming audio/video data is adjusted to converge on a clock rate associated with broadcasting the streaming data. The clock rate is adjusted by monitoring the buffer depth associated with a receive buffer that stores the incoming streaming data. The buffer depth provides an estimate of clock drift between the two clock rates. From the estimate of clock drift, the clock rate used in rendering broadcast streaming data is adjusted to avoid the clock drift causing skips or pauses in the rendered audio/video data.

Abstract: A charge pump for use in a locked loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage. The charge pump further includes a startup circuit to establish a predetermined voltage level at the charge pump output node during startup.

Abstract: A phase comparison process in a timing recovery process for high-speed data communication defines a data window and compares the phase of a clock in the window with the phase of an edge of data so as to realize a parallel process, wherein the phase comparison and the process of determining whether a data edge lies within the window are performed in parallel to each other, and the phase comparison result is output only if the data edge lies within the window. With this configuration, it is possible to perform an accurate phase comparison process with no errors without requiring high-precision delay circuits.

Abstract: The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.

Abstract: A method and an apparatus for stabilizing output from a Phase Lock Loop (PLL) and the PLL thereof is disclosed. The method mainly relates to enabling the control voltage of a voltage control oscillator VCO in the PLL remained unchanged by means of turning off a charge-discharge current source of a charge pump in a PLL in response to a detected reference signal lower than a default value. Furthermore, the method enables the pulse frequency output from the VCO no exceeding a default tolerant frequency range in a distance from a desired output frequency. Thus, when the reference signal resumes the original frequency, the PLL can quickly lock the phase and the frequency again.

Abstract: A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The control signal may be used to adjust the delay value of a voltage-controlled delay circuit in order to adjust the phase relationship between the first and second clock signals to have a predetermined phase relationship.

Abstract: Methods and apparatus are provided for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications. An interface is provided for use between a parallel bus and a serial bus. The interface includes a plurality of serializer/deserializer circuits that generate a clock signal, wherein one of the serializer/deserializer circuits is a master circuit generating a master clock signal and the remaining of the serializer/deserializer circuits are slave circuits generating slave clock signals. The master clock signal is substantially phase-aligned to a reference clock and is distributed to the slave circuits. The interface also includes a clock divider associated with the master circuit for selectively generating a master clock signal having one or more lower data rates than the reference clock; and a frequency detector associated with each of the slave circuits for automatically detecting a rate of the master clock signal.

Abstract: One embodiment of a method of generating a clock signal and synchronizing the generated clock signal with a digital data stream comprises generating a clock signal using an oscillator, identifying a transition in a portion of the data stream, and synchronizing a transition of the clock signal with the identified transition in the data stream by changing a state of the oscillator using control circuitry in response to the identification of the transition in the data stream, wherein the clock signal is synchronized with the data stream for both situations where the oscillator operates at a frequency greater than the data rate and where the oscillator operates a frequency less than the data rate. Other methods and systems are also provided.

Abstract: A clock data recovery loop that can be used over a wide range of data rates and maintain second-order behavior includes a nonlinear (e.g., Bang-Bang) phase detector, a charge pump, an RC loop filter, and signal generator (e.g., a voltage controlled oscillator (VCO)). At low data rates, the loop may be operated with the charge pump and loop filter with stable second-order behavior, with the resistor R of the loop filter serving as a proportional path. A separate proportional path is also provided that provides phase detector output directly to a control input of the VCO, while the resistor R of the loop filter is also bypassed. As increasing data rates give rise to third-order effects, the separate proportional path may be activated to maintain second-order behavior.

Abstract: A method and apparatus for determining a relationship between an input signal frequency and a reference signal frequency is envisioned. The system derives a plurality of internal reference signals from the reference signal. The internal reference signals are provided to a level detection circuit which in turn samples the input signal a number of times within a period of time. Values associated with these samples are stored, as is one value of a sample from a previous period. The stored samples are correlated, and a relationship between the input signal frequency and the reference signal frequency is derived.

Abstract: A phase lock loop device further includes a probability shaping device provided between a phase detection device and charge pump and loop filter (CPLF) device. The probability shaping device operates to reduce the frequency of outputting up-index or down-index; thereby shaping probability distribution to reduce degradation due to mismatching of the CPLF device.

Abstract: For EMI reduction the current modulation profile is preferably used for frequencies over 1 GHz while the frequency deviation is increased at least to ±2.5 MHz and the modulation frequency is increased to at least 150 kHz, preferably about 260 kHz. In an alternative embodiment, the modification frequency is 1 MHz or greater so that a segmented spectrum is achieved. For clocks having basic frequency below 1 GHz, but having strong harmonics higher than 1 GHz, modulation of the foregoing is combined with the slower modulation currently used. EMI reduction is realized both at the lower and the higher harmonics.

Abstract: Provided is a frequency control loop circuit changing division ratios of a frequency synthesizer to oscillate frequencies in a broadband with high precision. The circuit comprises a clock oscillator, a frequency synthesizer, and a demodulator.

Abstract: A method includes receiving a serial data signal including a preamble and an embedded clock signal having an embedded clock signal frequency, and processing the preamble using logic to determine the embedded clock signal frequency. An apparatus includes a counter unit, a state machine, and a logic unit. The counter unit includes a data port, a clock port and a plurality of counters. In operation, the data port receives a serial data signal and the clock port receives a clock signal having a clock signal frequency. The serial data signal includes a preamble and an embedded clock signal having an embedded clock signal frequency. The state machine identifies at least one of the plurality of counters to count between transitions in the preamble in response to the clock signal. The logic unit is coupled to the plurality of counters and determines the embedded clock signal frequency.

Abstract: A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PFD to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.

Abstract: A receiver that includes: an oversampling module that converts a serial stream of data into a plurality of streams of oversampled data based on the receive clock; a transition location module that determines transition locations of the streams of oversampled data and the receive clock; a pointer adjust module that determines a pointer variable based on the transition locations and the receive clock; a data selection module that determines an equivalent data value for the streams of oversampled data based on the pointer variable; a staging register module that produces an offset data word and an extra data word from the equivalent data value for the oversampled data streams; and a output register module that produces a parallel data output from at least one of the offset data word and the extra data word.

Abstract: An automatic frequency correction phase-locked loop (PLL) circuit includes an analog control circuit and a digital control circuit. The digital control circuit includes a High-side comparator and a Low-side comparator which receive an analog control voltage, a state monitor circuit, and a counter and decoder circuit. At least one of the High-side comparator and the Low-side comparator includes a threshold switching circuit which selectively provides a first threshold voltage and a second threshold voltage, the first and second threshold voltages having different magnitudes. When the analog control voltage remains stable between the High-side threshold voltage and the Low-side threshold voltage and the threshold switching circuit is providing the first threshold voltage, the state monitor circuit switches the threshold switching circuit from the first threshold voltage to the second threshold voltage, thereby expanding the interval between the High-side threshold voltage and the Low-side threshold voltage.

Abstract: A PLL circuit has (i) a counter which divides a frequency of a VCO output whose frequency has been divided by a frequency divider and (ii) a memory which stores plural patterns of set cycles of the counter. The memory reads out one of the set cycles designated by a selection signal inputted through a serial bus (SB) from an outside of the PLL circuit. The set cycle, read out from the memory, which has a large amount of data, is inputted through a parallel bus (PB) into the counter, so that it hardly takes time to set a cycle for the counter. Further, even when the number of bits of the counter increases, the setting time is not lengthened.

Abstract: An apparatus for adjusting the phase of a wobble clock including a phase adjusting circuit for receiving a wobble signal and a wobble clock to generate a phase adjusting value, and a frequency divider coupled to the phase adjusting circuit for adjusting the phase of the wobble clock according to the phase adjusting value.

Abstract: A clock data recovery circuit with feedback type phase discrimination. The clock data recovery circuit has an output signal of B bits and comprises a sampler, a phase region decision circuit, a phase status register and a multiplexer. The sampler oversamples k*B bits per cycle from a data input signal according to a sampling clock signal. The phase region decision circuit generates a plurality of binary up-down decision signals according to the oversampled data input signal and a current phase status signal. The phase status register generates the current phase status signal according to the binary up-down decision signals. The multiplexer selects data of B bits from the oversampled data input signal according to the current phase status signal.

Abstract: A low jitter digital frequency synthesizer includes a first counter module, a second counter module, a snapshot module, an error value generation module, and a tapped delay line. The first counter module counts intervals of M cycles of an input clock to produce a first count. The second counter module count intervals of D cycles of an output clock to produce a second count, wherein an average rate of the output clock corresponds to M/D times a rate of the input clock. The snapshot module periodically takes a snapshot of the first and second counts to produce snapshots. The error value generation module generates a modulated error value based on the snapshots and a modulation value, where the modulation value is used to spread the spectrum of the output clock. The tapped delay line module produces the output clock based on the modulated error value.

Abstract: Disclosed are embodiments of a phase control circuit with an analog phase controller having first and second order integration. In some embodiments, the analog control circuit generates first and second control signals and controls the first control signal based on the sign of the second control signal and controls the second control signal based on the sign of the first control signal.

Abstract: A signal generator, such as a fractional-N PLL, has, in its feedback signal path, a divider, a phase circuit, and a fractional accumulator that generates control signals for the divider and the phase circuit. The divider control signal controls the divisor value applied by the divider. In one embodiment, a phase selector selects, based on the phase-circuit control signal, one of a plurality of phase-shifted output signals generated by the PLL's main signal path (e.g., by a multi-phase VCO) and the divider generates the feedback signal for the PLL from the selected signal. In another embodiment, the divider generates a divided signal from one of the phase-shifted output signals, and a phase mixer generates, from the divided signal, a plurality of phase-shifted divided signals and selects, based on the phase-circuit signal, one of the phase-shifted divided signals as the PLL's feedback signal.

Abstract: The phase locked loop (PLL) with adjustable phase shift is described. The PLL includes a voltage controlled oscillator which is capable of generating multiple phase shifted output signals, and multiple phase detectors capable of determining the phase differences between the output signals and a reference clock. The PLL further includes a weighting device capable of weighting the phase differences and generating a control signal for the voltage controlled oscillator.

Abstract: A clock and data recovery circuit has a voltage controlled oscillator that provides a clocking signal synchronized to a received serialized data. A multiple phase generator converts the clocking signal to a plurality of multiple phased clocking signals. A data capture device acquires the serialized data with each of the plurality of multiple phased clocking signals to create multiple phased data signals. A phase detector determines if the clocking signal is in phase with the recovered serialized data and providing a lead signal and a lag signal indicating whether the clocking signal is in phase with the recovered serialized data. A frequency initializing device assists acquisition of lock of the voltage controlled oscillator to a reference clock signal. A recovered data selector selects which of the multiple phased data signals are to be transferred to external circuitry for further processing.

Abstract: This patent disclosure presents circuits, systems and methods to extract the clock signal from a data stream. This new invention is far better than the current technologies in the range of frequency locking and tracking. Since the new data clock recovery system is built by digital circuits only, it can be implemented inside an IC easily. This invention is especially helpful for high speed data communication products since the clock can be recovered at full data rate.

Abstract: An optical (disc) driving system including the DLL based multiphase clock generator circuit capable of generating 32 different phases from input clock having a frequency of 800 MHz or greater. The multiphase clock generator includes on a delay locked loop (DLL) having a frequency divider for outputting an N-divided clock to a first set of M voltage-controlled delay cells within a feedback loop, and further including an identical set of M voltage-controlled delay cells outside of the feedback loop for delaying the undivided clock and for outputting M multiphase clocks. An optical driver circuit of an optical driving system and a method for implementing a write-strategy for preventing “overlapping” of marks written on adjacent grooves on an optical disc. The circuit and method produce multiple write-strategy waveforms (channels) switching at a high resolution (e.g., T/32) in the Gigahertz frequency range.

Abstract: A high speed transceiver without using an external clock signal and a communication method used by the high speed transceiver which applies a clock recovery circuit including a coarse code generator, a frequency detector, and a linear phase detector to the receiver so as to solve problems such as skew between a reference clock and data that may occur during data transmission and jitter of a recovered clock while an embedded clock method of applying clock information to data is used.

Abstract: The present invention provides a multi-phase-locked loop without dead zone, which can reduce clock jitter and provide larger tolerance for data random jitter. It generates and output multiple sets of control signals (upk/dnk) via a multi-phase voltage controlled oscillator which generates a plurality of multi-phase clock signals for detecting the transition edge of data signal. Therefore, the phase error ?e and the voltage Vd of the multi-phase-locked loop can be adjusted to be nearly linear according to the control signals. A multi-phase-locked loop without dead zone thus can be provided.