Abstract: A device and method for providing clock data recovery (CDR) in a receiver is disclosed. The method comprises receiving a Phase Amplitude Modulation (PAM) signal; on startup, using a non-return-to-zero (NRZ)-based phase frequency detector (PFD) to acquire signal frequency from the received PAM signal; and responsive to a determination, switching to a PAM phase detector (PD) for steady state operation.

Abstract: A radio communication apparatus operable over a wide range of frequencies including a signal processing device is provided. The device performs an analog to digital conversion at a predetermined sample rate independent of a selected frequency band within the wide range of frequencies to generate a digital signal, and digitally processes the digital signal to output a data signal at baseband associated with the selected frequency band.

Abstract: A circuit includes a phase detector circuit, a shift register ring circuit, and a phase shift circuit. The phase detector circuit generates an indication of a phase error between a periodic signal and an input signal. The shift register ring circuit shifts stored signals through a variable number of storage circuits coupled in the shift register ring circuit. The variable number of storage circuits coupled in the shift register ring circuit is determined based on the indication of the phase error. The phase shift circuit adjusts a phase of the periodic signal based on the stored signals.

Abstract: System and methods for a clock system disciplined to an external reference. In one embodiment, the clock includes a flywheel oscillator controlled by the external reference and a free running holdover oscillator. The holdover oscillator provides increased accuracy during periods of holdover when the external reference is not available. In a further embodiment, the flywheel oscillator is additionally controlled by a phase-locked loop with the holdover oscillator frequency as input, and a control switch for switching the flywheel oscillator to analog control if the phase-locked loop exhibits a fault.

Abstract: A phase-locked loop (PLL) is provided. The PLL comprises a dithering circuit that is configured to receive a second tuning signal, and dither the second tuning signal to generate a dither signal to decrease a magnitude of a spur of the PLL. The dither signal is used by a digitally controlled oscillator (DCO) to generate an output signal of the PLL. Operation of the dithering circuit is controlled using a spur-cancel control circuit. The spur-cancel control circuit receives a frequency command word (FCW) signal and determines a value of an enable signal based on the FCW signal. In some embodiments, the dithering circuit dithers the second tuning signal based on the enable signal.

Abstract: A system for generating a local clock, configurable to utilize a forwarded clock and a data stream, or a data stream only, as frequency and phase references. In one embodiment, the system includes a phase locked loop that may be referenced to a forwarded clock, or to a phase reference formed from received data, utilizing a sampler, a crossing sampler, and a bang-bang phase detector. The system includes a local phase recovery loop which may utilize the bang-bang phase detector as part of a phase detector for controlling a phase interpolator, the output of the phase interpolator serving as the local clock for clocking received data.

Abstract: An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be caused by phase noise, delay errors or skew errors. Several methods and devices may reduce the quantization error. A noise source may add dithering to the reference clock at an input of the time to digital converter. A digital processor may use two successive rising edges of the oscillator signal to count time delays of the time to digital convertor to the reference clock. The digital processor uses these counts to determine a ratio of the time delays and the time period of the oscillator signal for controlling a digitally controlled oscillator. A radio frequency counter circuit detects whether the oscillator signal leads or lags the reference clock because of skew and generates a phase signal to correct the skew.

Abstract: Disclosed herein is an apparatus for radio frequency digital-to-analog conversion of in-phase and quadrature bit streams. The apparatus may include a plurality of in-phase multiplying cells that receive an in-phase local oscillator signal and a plurality of in-phase bits, a plurality of quadrature multiplying cells that receive a quadrature local oscillator signal and a plurality of quadrature bits, a first output line connected to a first set of the plurality of in-phase multiplying cells and a first set of the plurality of quadrature multiplying cells, and a second output line connected to a second set of the plurality of in-phase multiplying cells and a second set of the plurality of quadrature multiplying cells. Each multiplying cell produces an output signal based on a received input bit. The output signals from each multiplying cell combine in phase on the connected output line.

Abstract: A clock generation circuit includes a delay clock generation unit configured to generate a predetermined number of delay clock signals having different delay time periods for a reference clock signal; a low-speed clock generation unit configured to generate a low-speed clock signal having a lower frequency than the reference signal in accordance with a control signal that controls a phase; a control signal processing unit configured to perform, on the control signal, a quantization process for quantizing a value of the control signal into the predetermined number of discrete values and a modulation process for distributing a quantization error in the quantization process in a band of frequencies higher than a predetermined frequency; a selection unit configured to select any one of the predetermined number of delay signals in accordance with the control signal; and an output unit configured to output the low-speed signal in synchronization with the selected signal.

Abstract: Embodiments of the present invention provide a phase detection method and apparatus. The apparatus comprises a phase detector, the phase detector comprising a calculation unit configured to calculate a phase difference according to a product of receiving power at different moments, so as to perform clock recovery by using the phase difference; wherein the receiving power is that obtained in sampling input signals at a predefined sampling rate, the predefined sampling rate being 2 times of a symbol rate. With the method and apparatus of the embodiments of the present invention, the problem that in case of a relatively large frequency difference or line width, or the transmitted signals are Nyquist signals of spectral widths close to the symbol rate, a conventional phase detection method will be invalid, is solved by calculating a phase difference only according to a product of receiving power at different moments.

Abstract: A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided.

Abstract: A time-to-digital converter (TDC) in which a chain of inverters with finite propagation delays form a delay line in which a level transition applied to one end of the delay line from an input line produces a series of progressively delayed level transitions of alternating polarity along the delay line. Each inverter has an associated pass gate, with the output of the inverter together with the output of the preceding delay line element driving the complementary gate inputs of the pass gate. The complementary gate inputs of each pass gate are coupled to the corresponding delay line outputs in an alternating manner so that, as the level transitions traverse the delay line, the pass gates are progressively enabled to couple the input line to corresponding output lines to produce a series of progressively delayed level transitions of like polarity on those output lines.

Abstract: A phase interpolator is described. The phase interpolator may comprise a first plurality of digital-to-analog converters coupled to receive a first phase of a clock signal; a second plurality of digital-to-analog converters coupled to receive a second phase of the clock signal; and a third plurality of digital-to-analog converters coupled to both the first phase of the clock signal and the second phase of the clock; wherein each digital-to-analog converter is configurable to receive either the first phase of the clock signal or the second phase of the clock signal. A method of implementing a phase interpolator is also described.

Abstract: A method for performing chip level electromagnetic interference (EMI) reduction is provided, where the method is applied to an electronic device. The method includes: providing at least one EMI suppression circuit within at least one chip of the electronic device; and utilizing the at least one EMI suppression circuit within the at least one chip to perform EMI reduction on at least one signal within the at least one chip. In particular, the at least one chip includes a first chip and a second chip; and the at least one EMI suppression circuit includes a first EMI suppression circuit positioned within the first chip, and further includes a second EMI suppression circuit positioned within the second chip. An associated apparatus is also provided.

Abstract: Disclosed are various exemplary embodiments of a clock recovery apparatus for recovering clock signals of multiple data channels. In one exemplary embodiment a clock recovery apparatus for a plurality of data channels may include a plurality of channel blocks, where each channel block may include a frequency detection block configured to generate an intermediate signal based on a respective data signal received from a respective data channel and a global signal, and a recovery block configured to recover a clock signal for the respective data channel in response to the respective data signal and the global signal. The apparatus may also include a global signal generation block configured to receive and combine the intermediate signals from the plurality of channel blocks to generate the global signal.

Abstract: One embodiment provides a data-receiving device component comprising a phase shifter, timer logic, and control logic. The phase shifter is configured to release a train of clock pulses with a controlled phase shift. The timer logic is configured to receive data from a data-sending device, and for each transition of the data received, to determine whether a clock pulse from the train is early or late with respect to the transition, and to tally the late clock pulses relative to the early clock pulses. The control logic, operatively coupled to the phase shifter and to the timer logic, is configured to incrementally advance the phase shift when the late clock pulses outnumber the early clock pulses by a non-integer power of two.

Abstract: A first phase setting circuit generates a first phase setting signal. A first synchronous signal generator generates a first synchronous clock signal having a phase set by the first phase setting signal from a multi-phase local clock signal. By removing a phase fluctuation component representing phase fluctuation of the reception data signal from a first signal including a frequency component representing a frequency offset between a multi-phase local clock signal and a reception data signal and the phase fluctuation component, a second generation unit generates a second signal including the frequency component. The first phase setting circuit updates the first phase setting signal according to the second signal.

Abstract: Provided is an analog front end of a digital TV, a digital TV system having the same, and a method of operating the same. The analog front end includes: a first selection circuit which selectively outputs differential sound intermediate frequency signals or differential TV broadcast signals in response to a first selection signal; a second selection circuit which outputs a clock signal among a plurality of clock signals having a different sampling frequencies, in response to a second selection signal; and an analog-to-digital converter which converts output signals output from the first selection circuit to a digital code, according to a sampling frequency of a clock signal output from the second selection circuit.

Abstract: An apparatus including a bang-bang clock data recovery module and a decision feedback equalizer. A phase detector of the bang-bang clock and data recovery module may be configured to eliminate coupling between the bang-bang clock and data recovery module and the decision feedback equalizer based upon an error signal of the decision feedback equalizer and a predetermined coefficient.

Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Abstract: An output portion of a charge pump receives control signals from a phase frequency detector and in response outputs positive current pulses and negative current pulses to a loop filter. A current control portion of the charge pump controls the output portion such that the magnitudes of the positive and negative current pulses are the same. Within the current control portion there is a “Charge Pump Output Voltage Replica Node” (CPOVRN). The voltage on this CPOVRN is maintained to be the same as a voltage on the charge pump output node. A capacitor leakage compensation circuit indirectly senses the voltage across a leaking capacitor of the loop filter by sensing the voltage on the CPOVRN. The compensation circuit imposes the sensed voltage across a replica capacitor, mirrors a current leaking through the replica, and supplies the mirrored current in the form of a compensation current to the leaking capacitor.

Abstract: An apparatus and method for compensating output signals of a magnetic encoder are disclosed. The apparatus includes a pre-calibration unit, an advanced phase detector, a loop filter, a voltage controlled oscillator (VCO), and a pulse generator. The pre-calibration unit obtains two phase-compensated waveforms through trigonometric function operations, and adjusts the amplitudes of the two phase-compensated waveforms to the same value, thereby generating input sine and cosine waves. The advanced phase detector generates an error output signal through trigonometric function operations. The loop filter sets the filter transfer function of an active lead-lag filter, and then filters the error output signal. The VCO generates a compensated signal. The pulse generator outputs a phase index, and generates two output pulses having a phase difference of 90 degrees in accordance with a pulse generation rule of a look-up table.

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link, which may indicate a change in frequency on the primary link. The source processor to the sink processor via the primary link may send initialization parameters, which may include a clock data recovery lock parameter and an idle parameter.

Abstract: Circuitry for measuring a propagation delay in a circuit path. The circuitry includes a one-shot edge triggered element that can be connected in a loop with the circuit path. An edge signal propagating through the circuit path triggers the one-shot element to output a pulse. The pulse propagates around the loop, again triggering the one-shot element to produce a pulse, creating a repeating series of pulses. The period between these pulses is influenced by propagation time of an edge through the loop such that a difference in the period with the circuit path connected and not connected in the loop indicates propagation delay in the circuit path. Such circuitry can be configured to independently measure, and therefore calibrate for, propagation delays associated with rising and falling edges. Calibration to separately equalize propagation delays for rising and falling edges can increase the timing accuracy of an automatic test system.

Abstract: In one embodiment, an apparatus including a phase detector unit to determine a phase difference between a reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.

Abstract: Embodiments are described for a method and system of enabling updates from a clock controller to be sent directly to a predictive synchronizer to manage instant changes in frequency between transmit and receive clock domains, comprising receiving receive and transmit reference frequencies from a phase-locked loop circuit, receiving receive and transmit constant codes from a controller coupled to the phase-locked loop circuit, obtaining a time delay factor to accommodate phase detection between the transmit and receive clock domains, and calculating new detection interval and frequency information using the time delay factor, the reference frequencies, and the constant codes.

Abstract: An integer frequency divider capable of achieving a 50% duty cycle includes a source clock input end that provides a source clock, and two or more latches connected in series according to a connection order. Each of the latches includes: a signal input stage, configured to receive an input signal; a clock receiving stage, configured to treat the source clock as an input clock and an inverted clock of the source clock as an inverted signal of the input clock when the latch corresponds to an odd number in the connection order, and to treat the inverted clock as the input clock and the source clock as the inverted signal of the input clock when the latch corresponds to an even number in the connection order; and a signal output stage, configured to output an output signal according to the input signal and the source clock.

Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including an on-chip measurement circuit. The measurement circuit includes a buffer line, a ring oscillator, a first measurement unit measuring a duty cycle of a periodic pulse output from the buffer line, and a second measurement unit measuring a frequency of a periodic pulse output from the ring oscillator. The buffer line including a plurality of delay elements connected in series. Each of the plurality of delay elements includes a former-stage inverter unit including a PMOS transistor and an NMOS transistor and having a first delay amount, and a latter-stage inverter unit including a PMOS transistor and an NMOS transistor and having a second delay amount different from the first delay amount.

Abstract: A method and apparatus for performing clock extraction are provided. The method includes: performing edge analysis on a Training Sequence Equalization (TSEQ) pattern carried by a set of received signals that are received from a Universal Serial Bus (USB) port of an electronic device, to dynamically generate a plurality of analysis results; and performing frequency calibration on a frequency of an output clock of a Numerically Controlled Oscillator (NCO) according to a frequency that different types of analysis results within the plurality of analysis results alternatively occur, to utilize the output clock as a reference clock after completing the frequency calibration. More particularly, the method further includes: generating a set of de-multiplexed signals respectively corresponding to a plurality of bits, to perform the edge analysis by comparing respective voltage levels of de-multiplexed signals corresponding to every two adjacent bits of the plurality of bits within the set of de-multiplexed signals.

Abstract: A data recovery unit (DRU) includes: an oscillator; a phase detector unit configured to receive a reference phase and to receive input data through N wires, where N is an integer, to compare the reference phase with the input data to obtain phase errors, and to determine an average of the phase errors; a subtractor to subtract an output of the oscillator from the average of the phase errors to obtain an unbiased phase error; a delay unit to receive the input data; and a sample selector configured to receive an output from the delay unit and the output of the oscillator, and to output recovered data.

Abstract: The present invention provides a phase jump detection method, apparatus, and system. In embodiments of the present invention, by collecting N frequency control words, a phase jump in an intermediate frequency signal is detected according to the N frequency control words. An extra phase jump meter is not required, and therefore detection may be supported on massive microwave communication devices, thereby improving the detection efficiency.

Abstract: A method and an apparatus for generating PWM signals is provided. Upon detection of a load transient, a new PWM period is started if the load transient occurs during the off-time of a PWM signal and exceeds a specific magnitude.

Abstract: In a serial communication circuit, a data extracting section extracts reception data based on a reception clock signal with maximum speed. A pattern determining section compares a reception bit pattern of the reception data corresponding to a characteristic pattern and each of a plurality of detection bit patterns for the characteristic pattern, and indicates when the reception bit pattern matches one of the detection bit patterns. A periodicity determining section determines a period when the reception bit pattern matches the detection bit pattern, based on the pattern match indication, detects that the detection bit pattern emerges continuously in a stream of the reception data every the period, and determines a generation difference between transmission and reception speeds based on the detection bit pattern. A transmission rate setting section determines the transmission speed of a connected device transmitting the reception data based on the generation difference and maximum speed.

Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

Abstract: A high performance CDR circuit. The circuit includes a first and second sampler, a first and second charge-pump coupled to the first and the second sampler, a capacitor coupled to the first charge pump, and a filter coupled to the second charge pump. A VCO circuit is coupled to the first charge pump and the second charge pump, wherein a path for setting a frequency is provided by the first charge pump and the capacitor, and wherein a path for phase is provided by the second charge pump, wherein a voltage of the capacitor is stable to enable the VCO to tolerate CIDs.

Abstract: A transmission device includes a memory which stores a program, and a processor which executes, based on the program, a procedure including calculating a difference between a first time when a frame is received by a first port which is in a blocked state and a second time when the frame is received by a second port which is not in a blocked state, and correcting a frame received after topology of a network is changed in accordance with states of the first and second ports after the topology is changed and the difference.

Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.

Abstract: A fractional-N phase locked loop is provided. The fractional-N phase locked loop includes a phase adjusting circuit detecting a phase difference between a reference clock signal and a feedback clock signal and outputting a plurality of phase clock signals in response to the detected phase difference, a phase selector selecting and outputting one of the plurality of phase clock signals output from the phase adjusting circuit in response to a phase selection signal, a control circuit generating the phase selection signal by using a sigma-delta modulator operation clock signal, which is generated by dividing the selected phase clock signal by each of N or more different integers (N is an integer more than or equal to 2), and a first divider generating the feedback clock signal by dividing the selected phase clock signal by an integer.

Abstract: Disclosed herein is an information processor including: a processing section adapted to perform a predetermined process on a data signal output in synchronism with one of positive and negative edges of a clock signal and output an execution result thereof; a holding section adapted to hold the execution result in synchronism with the other of the positive and negative edges; a timing determination section adapted to determine whether a grace period lasting until the execution result is held by the holding section meets a setup time of the holding section; a clock control section adapted, if it is determined that the grace period does not meet the setup time, to control at least the timing of either the positive or negative edge in such a manner that the grace period meets the setup time; and a clock generation section adapted to generate the clock signal according to the controlled timing.

Abstract: A method includes generating one of a first clock signal and a second clock signal from the other clock signal. The first clock signal is configured to be used to synchronize an operation of an analog system, and the second clock signal is configured to be used to synchronize an operation of a digital system. The method includes using a phase detector of the analog system to measure a timing of the first clock signal relative to the second clock signal; and the method includes controlling a delay element of the digital system to regulate the timing based on the measurement by the phase detector to suppress noise in the analog system.

Abstract: A frequency tracking loop receives a result from a phase detector that detects an advance and a retard of a phase between input data and an extracted clock signal, and conducts a control to reduce a frequency deviation between the input data and the extracted clock signal. A phase interpolator adjusts a phase of the clock signal subjected to spread-spectrum frequency modulation on the basis result of the frequency deviation in the frequency tracking loop, and outputs the extracted clock signal. In the frequency tracking loop, the frequency deviation between the data signal and the clock signal is corrected to offset a variation of the frequency of the clock signal, on the basis of the frequency modulation information related to the clock signal subjected to the spread-spectrum frequency modulation which is input to the phase interpolator. The frequency of the clock signal seemingly follows the frequency of the data signal.

Abstract: A circuit includes a sampler circuit, a filter circuit, a control circuit, and a phase shift circuit. The sampler circuit samples input data in response to a clock signal. The filter circuit is coupled to the sampler circuit. The control circuit is coupled to the filter circuit. The phase shift circuit provides the clock signal to the sampler circuit. The control circuit causes the phase shift circuit to shift a phase of the clock signal by a first phase shift, and by a second phase shift after the phase of the clock signal has shifted by the first phase shift, in response to the filter circuit indicating to shift the phase of the clock signal by more than a predefined phase shift.

Abstract: A clock data recovery circuit includes: a phase detector circuit configured to generate a phase detection signal indicating a first detection result between a phase of a reception data signal and a phase of a first clock signal; a clock signal generation circuit configured to generate the first clock signal and a second clock signal based on the phase detection signal, the second clock signal having a frequency substantially equal to a frequency of the first clock signal, a phase difference between the first clock signal and the second clock signal being less than 180°; a phase combining circuit configured to combine the first clock signal and the second clock signal in accordance with a phase relation and generate a recovered clock signal; and a recovered data generation circuit configured to sample the reception data signal and generate a recovered data signal based on the recovered clock signal.

Abstract: A frequency synthesizer is disclosed that includes an oscillator having an output to deliver a signal of a controllable frequency. The oscillator includes a capacitor bank responsive to an N-bit control signal to exhibit a capacitance. The oscillator output frequency is based on the capacitance. Control logic generates the N-bit control signal and determines each bit of the N-bit control signal through a binary search step and a modulation of a least-significant-bit (LSB) of the N-bit control signal. The LSB modulation, combined with the binary search for each bit, results in a higher accuracy frequency estimation.

Abstract: An electronic device has a calibration arrangement for controlling a frequency characteristic of a PLL circuit having a phase comparator having an output for generating a phase difference signal, a voltage controlled oscillator and a divider. The divisor of the divider is programmable, and the oscillator is also directly modulated by an oscillator modulation signal. A modulation unit has a modulation input for receiving a modulation signal and generates the oscillator modulation signal and the divisor such that modulation generates a predefined change of the output frequency and a change of the divisor proportional to said predefined change. The calibration arrangement receives the phase difference signal, and has a ripple detector for providing a detector output signal by detecting a ripple on the phase difference signal correlated to edges in the modulation signal. A calibration control unit adjusts the oscillator modulation signal based on the detector output signal such that the ripple is reduced.

Abstract: A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal.

Abstract: A serializer circuit may include a recovery circuit, an adjusting circuit, and a multiplexer circuit. The recovery circuit may be configured to receive a first data signal at a first frequency, to generate a first clock signal at the first frequency using the first data signal, and to retime the first data signal based on the first clock signal to generate a retimed first data signal. The adjusting circuit may be configured to receive a second data signal and retime the second data signal based on the first clock signal to generate a retimed second data signal. The multiplexer circuit may be configured to multiplex the retimed first data signal and the retimed second data signal.

Abstract: This disclosure provides a clock recovery circuit having a phase-locked loop (PLL) with two-point modulation. A binary phase-error signal controls a variable frequency oscillator's (VFO's) feedback path, while a linear phase-error signal controls the PLL outside of that feedback path. The linear phase-error signal is injected using an ultra-low latency delay path. While the binary phase-error signal sets the lock-point of the PLL, the linear phase-error path dominates at high frequencies and also helps reduce dither jitter. Other optional features include an area-efficient hybrid phase detector that generates both the binary and linear phase-error signals, use of a phase interpolator inside the PLL to further smooth dither jitter, recovered clock update filtering for specific data transitions, and support for multi-PAM signaling.

Abstract: A clock data recovery circuit includes a binary phase detector configured to receive an incoming data signal and a recovered clock, and output a phase offset signal and recovered data; a digital loop control circuit configured to receive the phase offset signal and output a control signal; and a digital frequency generator configured to receive the control signal and output the recovered clock. A method of clock recovery includes generating a digital phase offset signal from incoming data and feedback clock signals; generating a clock frequency control signal from the phase offset signal; generating a recovered clock in response to the control signal; slowing down the recovered clock when the digital phase offset signal has a first binary state; speeding up the recovered clock when the digital phase offset signal has a second binary state; and holding the recovered clock when the digital phase offset signal has a third binary state.

Abstract: An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be caused by phase noise, delay errors or skew errors. Several methods and devices may reduce the quantization error. A noise source may add dithering to the reference clock at an input of the time to digital converter. A digital processor may use two successive rising edges of the oscillator signal to count time delays of the time to digital convertor to the reference clock, and uses these counts to determine a ratio of the time delays and the time period of the oscillator signal for controlling a digitally controlled oscillator. A radio frequency counter circuit detects whether the oscillator signal leads or lags the reference clock because of skew and generates a phase signal to correct the skew.