Abstract: A transmission circuit includes a filter circuit configured to compensate for degradation of a multiplexed signal, based on a tap coefficient to be updated based on a first signal and a second signal which are time-division-multiplexed to the multiplexed signal, a phase locked loop (PLL) circuit configured to control, based on control information corresponding to phases of the first signal and the second signal, a frequency of a clock signal to be synchronized with the multiplexed signal whose degradation has been compensated, and a control circuit configured to generate, in response to an interruption of an input of the first signal or the second signal, the control information corresponding to the phase of the first signal or the second signal of which the interruption is not detected so as to output the control information to the PLL circuit.

Abstract: In an embodiment, a clock generator has a variable-modulus frequency divider that receives a high-frequency clock signal and outputs a divided clock signal having a frequency controlled by a modulus-control signal generated by a temperature-compensation circuit. A jitter filter is coupled to the output of the variable-modulus frequency divider and to the temperature-compensation circuit and generates a compensated clock signal having switching edges that are delayed, with respect to the divided clock signal, by a time correlated to a quantization-error signal.

Abstract: The proposed Power Management Integrated Circuit (PMIC) features the option to synchronize the charge-pump of a PMIC with the system clock, and then to swap and self-oscillate and skip pulses, when the digital controls of the PMIC send a first order to the charge-pump. The clock control circuitry of the PMIC also features the option for the charge-pump to then swap and use the system clock again, when the digital controls of the PMIC send a second order to the charge-pump. The designed transition of the clock from clock sync-mode to self-oscillate, and from self-oscillate back to clock sync-mode, does not present any phase discontinuity.

Abstract: The present disclosure includes a time-to-digital converter (TDC) based RF-to-digital (RDC) data converter for time domain signal processing polar receivers. Polar data conversion achieves better SNR tolerance owing to its phase convergence near the origin in a polar coordinate. The proposed RDC consists of a TDC for phase detection and an analog-to-digital converter (ADC) for amplitude conversion. Unlike the conversional data converter, the proposed ADC's sampling position is guided by the detected phase result from the TDC's output. This TDC assisted data-converter architecture reduces the number of bits required for the ADC. In addition, oversampling is no longer needed. With precisely controlled tunable delay cells and gain compensator, this hybrid data convertor is capable to directly convert Quadrature Amplitude Modulation (QAM) waveforms and Amplitude Phase Shift Keying (APSK) waveforms directly from the RF signal without down-conversion.

Abstract: A clock data recovery circuit includes: a first detecting circuit for detecting phases of an incoming data signal and a sampling clock signal to generate a first detection signal; a loop filter for generating a control signal according to the first detection signal; a second detecting circuit for detecting phases of a reference signal and a feedback signal to generate a second detection signal; a control voltage generating circuit for generating a control voltage based on the second detection signal; a voltage-controlled oscillator for generating the sampling clock signal according to the control voltage; a phase adjustment circuit for adjusting the phase of the sampling clock signal according to the control signal to generate the phase-adjusted signal; and a frequency divider circuit for conducting a frequency division operation on the phase-adjusted signal to generate the feedback signal.

Abstract: Apparatus, circuits and methods for calibrating time to digital converters (TDCs) are disclosed herein. In some embodiments, a circuit for calibrating a TDC is disclosed. The circuit includes a multi-bit delay circuit, a counter, and a register. The multi-bit delay circuit is configured for delaying a clock signal by a total delay time. The counter is configured for counting rising edges of the clock signal within the total delay time to generate a counted output. The register is configured for controlling the total delay time of the multi-bit delay circuit based on the counted output.

Abstract: An integrated level-shifter and memory clock is disclosed that minimizes delay of voltage level-shifting from an external clock on a first logic supply voltage to an internal clock on a higher array supply voltage that is pulse-width independent of the external clock used to generate the internal clock. The generation of the internal clock on the higher array supply voltages is accomplished in two stages of logic. An array-tracking timing delay circuit mimics access delay to generate a MRST_P to reset the internal clock on the higher array supply voltage.

Abstract: A synchronous mirror delay (SMD) circuit is provided in the invention. The SMD circuit includes a delay monitor circuit (DMC), a forward delay circuit, a first shift circuit, a backward delay circuit, a second shift circuit and a clock-frequency-checker (CSC) circuit. The CSC circuit is coupled to the first shift circuit and the second shift circuit. The CSC circuit determines whether the frequency of the external input clock signal is slower than the frequency of the reference clock signal to generate a judgment result, and the CSC circuit transmits the judgment result to the first shift circuit and the second shift circuit. The first shift circuit and the second shift circuit determine whether to delay the external input clock signal according to the judgment result.

Abstract: In certain aspects, an apparatus includes a multiplexer having a first input, a second input, a select input, and an output, wherein the first input is configured to receive a first reference clock signal, the second input is configured to receive a second reference clock signal, and the select input is configured to receive a select signal. The multiplexer is configured to select one of the first and second reference clock signals based on the select signal, and output the selected one of the first and second reference clock signals at the output of the multiplexer. The apparatus also includes a clock driver having an input and an output, wherein the input of the clock driver is coupled to the output of the multiplexer.

Abstract: Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a first divided signal and a second divided signal that is complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enabled period and produce a first count value, a second circuit configured to count the second divided signal during a second enabled period and produce a second count value, and an adder configured to produce a third count value responsive to the first and second count values.

Abstract: Disclosed is a DDR SDRAM physical layer interface circuit including: a multiphase clock generator generating a plurality of clocks including a reference clock, a first clock, a second clock and a third clock; a frequency dividing circuit generating a PHY clock according to the first clock; a clock output path outputting the reference clock to a storage circuit; a first output circuit outputting a first output signal to the storage circuit according to a first input signal of a memory controller, the first clock and the PHY clock; a second output circuit outputting a second output signal to the storage circuit according to a second input signal of the memory controller, the second clock and the PHY clock; and a third output circuit outputting a third output signal to the storage circuit according to a third input signal of the memory controller, the third clock and the PHY clock.

Abstract: A circuit for duty cycle detection and correction, for a serial data transmitter. The circuit includes a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter, and a duty cycle detection circuit, connected to the output of the serial data transmitter. The pattern generator is configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones. The duty cycle detection circuit is configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.

Abstract: A frequency drift compensation system for a radio receiver includes a pilot signal generator that is configured to generate two pilot signals, a local oscillator that is configured to generate a local oscillator frequency signal, a first mixer that generates a first offset pilot signal, a second mixer that generates a second offset pilot signal, and a summer that is configured to add the first offset pilot signal and the second offset pilot signal to the intermediate frequency signal to obtain a composite signal. The frequency drift compensation system includes a processor that is configured to detect frequency drift in the offset pilot signal responsive to the composite signal and to generate a frequency drift control signal to compensate for the frequency drift. Related radio receivers, GPS receivers, and methods are described.

Abstract: A time-to-digital converter includes a first oscillation circuit that starts oscillating at the transition timing of a first signal and generates a first clock signal having a first clock frequency, a second oscillation circuit that starts oscillating at the transition timing of a second signal and generates a second clock signal having a second clock frequency, a first adjustment circuit that adjusts the oscillation frequency of the first oscillation circuit based on a reference clock signal, a second adjustment circuit that adjusts the oscillation frequency of the second oscillation circuit based on the reference clock signal, and a processing circuit that converts the time difference between the transition timing of the first signal and the transition timing of the second signal into a digital value based on the first and second clock signals.

Abstract: An apparatus comprising an accumulator circuit and an offset register. The accumulator circuit may be configured to (a) receive a plurality of frequency offset values from a plurality of sourcing DPLLs and (b) generate a current combined offset value in response to a sum of the frequency offset values. The offset register may be configured to (a) store an offset value corresponding to the current combined offset value in a first mode and (b) store an offset value corresponding to an updated offset value in a second mode. The updated offset value may comprise a difference between the offset value stored in the offset register and the current combined offset value. The offset value may be presented to a receiving DPLL during a re-arrangement of the sourcing DPLLs. Presenting the offset value may reduce a phase transient caused by the re-arrangement.

Abstract: Certain aspects of the present disclosure are directed to a digitally controlled oscillator (DCO). The DCO generally includes an oscillator, a current mirror having a first branch coupled to a control input of the oscillator, a first current source, and a first transistor having a drain coupled to the first current source and a gate of the first transistor, a source of the first transistor being coupled to the control input of the oscillator. The DCO may also include a second current source coupled to the source of the first transistor, and a second transistor having a gate coupled to the gate of the first transistor, a drain of the second transistor being coupled to a second branch of the current mirror.

Abstract: A delay circuit includes: a variable delay line suitable for receiving an input signal and generating an output signal by delaying the input signal; a first phase difference detector suitable for detecting a phase difference between the input signal and a first clock; a second phase difference detector suitable for detecting a phase difference between the output signal and a second clock; and a control circuit suitable for adjusting a delay value of the variable delay line in response to a detection result of the first phase difference detector and a detection result of the second phase difference detector.

Abstract: Systems and methods for improvement in transmission antenna design and, more particularly, for rapid determine phase determination of incoming signals are described herein. In some embodiments, a phase detection system is described. The phase detection system includes a phase detection apparatus and a control system. The phase detection apparatus includes a phase shifting element and a phase detector element. The phase shifting element is configured to phase-shift a reference signal multiple times per detection cycle. The phase detector element is configured to compare an incoming signal to multiple phases of the phase-shifted reference signal during the detection cycle, and generate an output indicating a relative phase difference between the incoming signal and the phase-shifted reference signal for each of the multiple phases. The control system is configured to determine a relative phase of the incoming signal based, at least in part, on the outputs.

Abstract: Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.

Abstract: A high data rate integrated circuit, such as an integrated circuit including a large sensor array, may be implemented using clock multipliers in individual power domains, coupled to sets of transmitters, including a transmitter pair configuration. Reference clock distribution circuitry on the integrated circuit distributes a relatively low speed reference clock. In a transmitter pair configuration, each pair comprises a first transmitter and a second transmitter in a transmitter power domain. Also, each pair of transmitters includes a clock multiplier connected to the reference clock distribution circuitry, and disposed between the first and second transmitters, which produces a local transmit clock.

Abstract: A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

Abstract: There is disclosed an apparatus comprising a first phase-locked loop comprising: a phase detector (302, 304), arranged to receive a reference clock signal (306) and a feedback clock signal (308) and to output a frequency control signal based on a phase difference between the reference clock signal (306) and the feedback clock signal (308); a variable-frequency oscillator (312, 314) arranged to output an oscillator signal having a frequency dependent on said frequency control signal; first divider circuitry (316) for generating said feedback clock signal (308) by frequency-dividing said oscillator signal; and second divider circuitry (320) for generating an output clock signal (3220 by frequency-dividing said oscillator signal; wherein a phase relation between said first divider circuitry (316) and said second divider circuitry (320) is adjustable to delay or advance said output clock signal (322) relative to said feedback clock signal (308). The apparatus may be a radar receiver or transceiver.

Abstract: Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

Abstract: The present invention relates to a WiFi network system. More specifically, a digital network & control unit (DNCU) which is a digital network controller in one WiFi access point (AP) and a WiFi radio unit (wRU) which is a radio signal transmitter are separated from each other, and common DNCUs in each WiFi AP are placed in an operating station. Thus, the common DNCUs are concentrated on one place and managed. In addition, since only the wRU is placed in outdoor and indoor WiFi service areas in which radio signals are actually transceived, the product price and the network investment cost and management cost can be reduced. To this end, a digital networking & control unit (DNCU) which includes a digital controller and a network processing unit and a WiFi radio service unit (wRSU) which includes a WiFi radio and an antenna unit are independently separated from each other and are connected to each other by a cable.

Abstract: Automatic frequency controllers, automatic frequency control methods, wireless communication devices, and/or wireless communication methods are provided. The automatic frequency controllers for correcting a frequency offset between a base station and a terminal includes at least one processor communicatively coupled to a memory and configured to execute computer-readable instructions stored in the memory to obtain a phase estimate from a reference signal received from the base station; classify a downlink channel as a High Speed Train (HST) channel or a non-HST channel based on the phase estimate; adjust a loop gain according to the classified downlink channel; calculate a phase error based on the phase estimate and the loop gain; correct the frequency offset using the phase error; and communicate with the base station after correcting the frequency offset.

Abstract: A transceiver includes a frequency modulation continuous wave generator to generate a frequency sequence and a digital phase locked loop to generate a waveform based on the frequency sequence. The digital phase locked loop includes a plurality of control registers. A main controller captures a reference state defined in the plurality of configuration registers prior to the frequency sequence, initiates the frequency sequence, restores the reference state of the configuration registers after completion of the frequency sequence, and repeats the frequency sequence after restoring the reference state.

Abstract: Disclosed herein are methods and systems that may help a base station provide high-speed data communication under a protocol such as LTE or WiMAX, even when a GPS signal is not available to the base station.

Abstract: A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.

Abstract: A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.

Abstract: An electronic device includes a transmitter configured to generate a signal. The electronic device also includes tuning circuitry coupled to the transmitter, wherein the tuning circuitry comprises a variable capacitance element and at least one fixed capacitance element having a fixed capacitance, wherein the variable capacitance element is configured to provide a dynamic capacitance based upon a voltage value related to a determined phase difference between the signal and a second signal, wherein the tuning circuitry is configured to adjust a frequency of the first signal to generate a tuned signal based upon a total capacitance comprising the fixed capacitance and the dynamic capacitance. The electronic device further includes an antenna coupled to the tuning circuitry and configured to generate an electromagnetic field based on the tuned signal.

Abstract: An actuator of a camera module includes a magnet, a coil facing the magnet, a driver configured to apply a driving signal to the coil to move the magnet in a direction, and a position estimator. The position estimator is configured to convert an oscillation signal into a digital signal in a delta sigma modulation scheme, and estimate the position of the magnet from the digital signal. A frequency of the oscillation signal varies based on a position of the magnet.

Abstract: The variation of the oscillation frequency of an oscillator can be suppressed even in the case where the amount of interference with the oscillator accompanied by an amplifying operation of a power amplifier and the polarity are not constant. An oscillator is configured to be capable of oscillating at an oscillation frequency in accordance with control signals Vcont and FREQ_CTRL. A phase locked loop allows the oscillator to output an oscillation signal Vout in synchronization with a reference signal RELCLK using the control signal Vcont. A power amplifier amplifies the electric power of the oscillation signal Vout. A variation detection unit detects a variation with respect to the time change of the control signal Vcont after an amplifying operation is started by the power amplifier causing 3interference with the oscillator.

Abstract: An example device in accordance with an aspect of the present disclosure includes a first stage and an accumulator. The first stage is based on digital logic and integer arithmetic to scale a reference clock by a configurable ratio of integers according to a line drawing technique to obtain an output clock. The accumulator is to store an accumulated error of a variable used in the line drawing technique.

Abstract: At least some embodiments are directed to a receiver system that comprises a first oscillation module configured to provide oscillating signals of differing frequencies and a second oscillation module configured to provide other oscillating signals of the differing frequencies. The second oscillation module is configured to produce less noise than the first oscillation module. A controller is coupled to the first and second oscillation modules and configured to selectively activate and deactivate each of the first and second oscillation modules based on signal strengths of primary signals received via a wireless medium and based on signal strengths of interference signals received via the wireless medium.

Abstract: Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

Abstract: A method for optimizing communication modes between network nodes includes: storing, in a first node in a communication network, a data success rate for each of a plurality of communication modes; receiving, by the first node, mode data from a second node in the communication network including at least a mode identifier for at least two of the plurality of communication modes; determining, by the first node, a metric for each of the at least two communication modes based on at least a data success rate of transmissions using the respective communication mode; selecting, by the first node, a preferred communication mode of the at least two communication modes based on the determined metric for each of the at least two communication modes; and transmitting, by the first node, an initiation data message to the second node via the communication network indicating the selected preferred communication mode.

Abstract: Systems, methods, circuits and computer-readable mediums for adaptive speed single-wire communications. In one aspect, a method includes receiving a sensing signal from a device through a single-wire bus, analyzing one or more properties of the received sensing signal, the one or more properties including at least one of a pulse width of the sensing signal and a duration between sequential pulses in the sensing signal, adjusting one or more communication parameters for single-wire communications with the device based on the analyzed one or more properties, and transmitting a specific signal to the device through the single-wire bus at an adjusted transmission speed based on the adjusted one or more communication parameters.

Abstract: A method of recovering a clock and data from an input data signal including an embedded clock, the method including generating a recovery clock signal from the input data signal based on a first window signal; detecting a unit interval corresponding to one bit of the input data signal based on the recovery clock signal; delaying a signal synchronized with the recovery clock signal based on the unit interval; and generating the first window signal based on the delayed signal.

Abstract: An apparatus comprising an accumulator circuit and an offset register. The accumulator circuit may be configured to (a) receive a plurality of frequency offset values from a plurality of sourcing DPLLs and (b) generate a current combined offset value in response to a sum of the frequency offset values. The offset register may be configured to (a) store an offset value corresponding to the current combined offset value in a first mode and (b) store an offset value corresponding to an updated offset value in a second mode. The updated offset value may comprise a difference between the offset value stored in the offset register and the current combined offset value. The offset value may be presented to a receiving DPLL during a re-arrangement of the sourcing DPLLs. Presenting the offset value may reduce a phase transient caused by the re-arrangement.

Abstract: Systems and methods for providing improved linearity and reduced noise in a digital phase-locked loop in which a differential time-to-digital converter is implemented. Digital-to-time converters are used for adjusting a reference clock signal based on a fractional change signal and for adjusting a feedback signal based on another fractional change signal. Each fractional change signal is centered about a midpoint, M, and offset from the midpoint by a fraction, x, such that the fractional change signals can be described as (M+x) and (M?x), respectively. By implementing a differential time-to-digital converter, the sum of delays in each input path is kept constant so that integral non-linearity is improved. Supply sensitivity is also reduced, as the same supply is applied to both differential input paths. Since the differential delay can be both positive and negative, the delay range of a differential digital-to-time converter is half that of a single input digital-to-time converter.

Abstract: A digital phase-locked loop with an automatic calibration function and an automatic calibration method thereof are provided. The digital phase-locked loop includes a frequency and phase detector, a calibration circuit, a frequency and phase locked circuit, and an oscillator circuit. The frequency and phase locked circuit outputs an initial control signal. The calibration circuit calibrates an initial frequency and outputs an initial calibration signal having a calibrated initial frequency when determining that the initial frequency does not fall within an allowable error calibration range. The frequency and phase locked circuit locks the calibrated initial frequency when determining that the calibrated initial frequency falls within a locked frequency range. The oscillator circuit outputs an oscillator signal according to the initial calibration signal and the initial control signal.

Abstract: In one embodiment, a differential to single ended conversion circuit is configured to convert a differential signal to a single ended signal without using an operational amplifier and without using a current source to charge a capacitor.

Abstract: An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations.

Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

Abstract: A pulse counting circuit receives pulses supplied by a source circuit having at least two inverted pulse signal supply terminals. The circuit includes a first counter to count pulses of a first pulse signal and supply a first count and a second counter to count pulses of a second pulse signal and supply a second count. A selection circuit selects one of the first and second counts.

Abstract: Described herein are systems and methods of receiving first and second input signals at a first two-input comparator, responsively generating a first subchannel output, receiving third and fourth input signals at a second two-input comparator, responsively generating a second subchannel output, receiving the first, second, third, and fourth input signals at a third multi-input comparator, responsively generating a third subchannel output representing a comparison of an average of the first and second input signals to an average of the third and fourth input signals, configuring a first data detector connected to the second subchannel output and a second data detector connected to the third subchannel output according to a legacy mode of operation and a P4 mode of operation.

Abstract: Implementing a distributed boundary clock in situations where book-end devices such as microwave TX/RX pairs must collaborate in achieving PTP on-path support is described. A dedicated channel, generally low-speed compared to the main channel is used to transfer timing from the master side to the slave side using framing and super-framing applied to the digital channel. Time-stamps of events such as super-frame boundaries are communicated between the two sides to enable timing transfer.

Abstract: Aspects are generally directed to optical receivers and methods for detecting a non-persistent communication superimposed on an overt communication channel. In one example, an optical receiver includes an optical resonator to receive an optical signal having one or more symbols encoded thereon at a modulated symbol repetition rate, the modulated symbol repetition rate being modulated relative to a nominal symbol repetition rate. The optical resonator is configured to emit an intensity-modulated output optical signal that has a variation in an intensity thereof corresponding to a symbol transition in the optical signal. The optical receiver further includes signal processing circuitry including a clock configured to generate a reference signal, a photodetector configured to generate a trigger signal, and a non-persistent communication decoder configured to determine a temporal misalignment between the symbol transition and the nominal symbol repetition rate based on the reference signal and the trigger signal.

Abstract: The present disclosure relates to a receiver and to a method implemented in the receiver for recovering a signal clock from a received data signal. Successive edge transitions between successive data samples of the received data signal are detected according to a clock recovered in the receiver. The recovered clock is adjusted based on a combination of weights assigned to at least some edge transitions among the plurality of successive edge transitions. In particular, (i) each very early transition is assigned a first weight having a first sign, (ii) each early transition is assigned a second weight having the first sign, (iii) each late transition is assigned a third weight having a second sign opposite from the first sign, and (iv) each very late transition is assigned a fourth weight having the second sign.

Abstract: An electronic device for a deaf person is provided. The device includes sound sensors arranged at different positions of the electronic device, and configured for sensing an external sound and converting the sensed external sound into sound signals; a processor connected to the sound sensors, and configured for generating a prompt signal when any sound parameters of the sound signals transmitted by the sound sensors meets a prompt condition; a vibrator connected to the processor, and configured for vibrating upon receiving the prompt signals; a first comparator connected to the processor, and configured for, in response of receiving the prompt signal, determining a sound sensor corresponding to a sound signal with a highest intensity, and generating orientation information corresponding to the sound sensor that corresponds to the sound signal with the highest intensity; and an indicator connected to the first comparator, and configured for indicating the orientation information.