Abstract: A transmitter comprises a demodulation means for demodulating inputted stream data to digital data, and outputting the digital data to a digital interface; a decoding means for decoding the digital data to obtain an analog signal; and a format conversion means 125 for converting the format of the analog signal, and outputting the analog signal to an analog interface. A recorder comprises a judgement means for judging whether the inputted digital data is recordable by the recorder or reproducible after recording; a data recording means for recording the digital data on a recording medium when the judgement means judges that the digital data is recordable; and a coding means for coding the analog signal when the judgement means judges that the digital data is unrecordable. Therefore, the data outputted from the transmitter such as a set-top box can be reliably recorded by the recorder.

Abstract: A method and apparatus for negotiating service configuration in a digital communication system is disclosed. In an exemplary embodiment the service negotiation system is implemented in a wireless spread spectrum communication system. The service configuration comprises data rates, frame formats and types of services. Types of service may include speech encoding, facsimile or digital data services. Further described herein is a digital transmitter and receiver using the service negotiation system to provide service configuration mutually acceptable at both ends of a communication link.

Abstract: A sole means global navigation apparatus adapted for use on an aircraft includes a GPS receiver to provide GPS measurement data and an inertial sensor system adapted to provide inertial translational and rotational data which during time periods is independent of the GPS position data. A navigation system coupled to both of the GPS receiver(s) and the inertial sensor system determines a navigation solution as a function of both the condition of the GPS satellite data and the uncertainty in the Inertial data. An augmentation system coupled to the navigation solution determining system is used to increase the accuracy and/or integrity of the GPS/inertial sensor, thereby achieving style means navigation requirements.

Abstract: A host signal processor (HSP) modem has a software interface between HSP modem hardware and native audio hardware in a host computer. No hard wire connections between modem hardware and audio hardware are required for synchronization. Instead, a software clock recovery system matches a transfer rate of the HSP modem hardware and a transfer rate of the audio hardware by duplicating or deleting samples. The software interface allows the native audio hardware to make audible the handshaking sequence during modem connections which eliminates the need for a speaker and speaker drivers in the modem hardware. The combination of HSP modem hardware, audio hardware, and software executed by the host computer also allows the HSP modem to perform voice communication such as telephone or speakerphone functions.

Abstract: Even if a signal line is momentarily disconnected while data communication, such as image data communication, is being performed by using, for example, an ITU-T Recommendation V.34 modem, communication is suitably continued. A main controller (CPU) determines the operating state (status) of a modem having the following mode. In this mode, the receiving operation of an image signal is automatically shifted to control signal communication upon detecting a pattern of a training signal. The main controller enables the above mode if it determines that the receiving status of the modem is not normal. It is thus possible for the modem to shift from the receiving of an image signal to control signal communication when the signal line is momentarily disconnected.

Abstract: A power saving infrared keyboard transmission method adapted for data transmission of a cordless computer keyboard is disclosed. The cordless keyboard has a transmission modulus comprising a microprocessor which converts the information related to the operation status of the keys of the keyboard into a series of pulses comprised of at least a first data byte and a second data byte. A leader code and a start code are added to the series of pulses in front of the first data byte and the leader code and the start code are transmitted before the data bytes are transmitted. A receiving modulus which is coupled to a host machine receives the data bytes together with the leader code and the start code. The leader code and the start code are received first to serve as an identification of the transmission of the data bytes so that the receiving modulus receives and interrupts the received data efficiently and effectively.

Abstract: Complex multiplication is performed using a multiplier by generating time division signals with a first clock and a second clock having a speed twice as fast as the first clock and operating the multiplier in a time division mode by the time division signals. Using a first clock and a second clock, the time division signals delayed by one-forth cycle are generated during one cycle of the first clock. Real element and imaginary element of two complex numbers are stored in D flip flops. A multiplexer driven by the time division signals selects each element of the complex numbers. A multiplier multiplies the selected elements in the selected time order. The multiplication results are latched in a plurality of D flip flops according to the time division signals. The latched multiplication results are added or subtracted with adder and subtracter. The outputs of the adder and subtracter are stored in D flip flops and output from the D flip flops, thereby obtaining the multiplication of two complex numbers.

Abstract: A system and method for source coding a signal to localize transmission errors to a set of samples is disclosed. The signal comprises a plurality of signal elements (SEs) with each SE having a plurality of components. The signal is divided into a plurality of data sets with each data set having a set of SEs. Each SE component of a data set is grouped into a plurality of divisions with each SE component having a plurality of bits. The plurality of bits of the SE components are distributed from the plurality of divisions across a generated bitstream. In one embodiment, this is used in the transmission of video signals over a potentially lossy communications channel.

Abstract: A digital cordless telecommunications unit that serves for communications when paired with a similar unit and connected with a network is disclosed. The unit receives and transmits analog voice signals and also transmits digital baseband signals and receives digital formatted baseband signals. The unit includes a baseband chip, as well as an audio functions block and a system control functions block. The audio functions block comprises an audio front end for receiving and transmitting the analog voice signals and an adaptive differential pulse code modulator codec, connected to the audio front end. The codec converts the analog voice signals to the digital baseband signals and converts the digital formatted baseband signals to the analog voice signals for transmission.

Abstract: A digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the ADC offset signal during normal operation of the isolation barrier system. The offset calibration system includes a coarse offset signal generator which provides ;elected increments of offset voltage to the ADC outside of the outgoing data signal channel, In order to increase the calibration range and to avoid injecting large offset voltages into the outgoing data channel. Fixed bias signals are also provided for the ADC and for a DAC in the system.

Abstract: A signal processing apparatus having a register unit with the number of bits required for signal processing, which is not larger than predetermined number of bits, and comprising a ROM which inputs, as an address signal, an output signal from the register unit or an input signal to the signal processing apparatus, and uses an input signal to the register unit as a part of an output signal from the ROM. This makes it possible to greatly reduce the cost of a system which executes complex processing yet requires a reduced number of bits in the input signals and a reduced number of bits for the register that is essentially required by reducing the amount of signal processing and the number of electric components, to greatly improve the quality of the apparatus accompanying the reduction in the number of electric components, and to cheaply increase the signal processing functions without decreasing the processing speed.

Abstract: A remote XDSL transceiver unit (16) includes an XDSL transceiver (19) and a control block (18). The XDSL transceiver (19) is operable to establish and communicate across an XDSL physical layer. The control block (18) is coupled to the XDSL transceiver (19) and operates to transmit a request for service to a loop termination point. The control block (18) also operates to identify a signal received from the loop termination point (14) and respond based upon a current context of the remote XDSL transceiver unit (16). Further, the control block (18) operates to control power-up and training of the XDSL transceiver (19) such that the XDSL physical layer can be dynamically brought up and down. In one embodiment, the control block (18) operates to store profile information for an established XDSL physical layer to use for future re-establishing of the XDSL physical layer.

Abstract: An interface circuit transmits data via a serial interface to and from a processor. A first-in-first-out memory is disposed between the serial interface and the processor. A suitable method transmits data which are received and read into the memory serially bit by bit and are read out of it byte by byte by the processor, or, respectively, can be written byte by byte into the memory by the processor and can be transmitted from the memory bit by bit.

Abstract: In a CELP coder, a comparison between a target signal and a plurality of synthetic signals is made. A synthetic signal is derived by filtering a plurality of excitation sequences by a synthesis filter having parameters derived from the target signal. The excitation signal, which results in a minimum error between the target signal and the synthetic signal, is selected. The search for the best excitation signal requires a substantial computational complexity. To reduce the complexity, a preselection of a small number of excitation sequences is made by selecting a small number of excitation sequences resembling the most backward filtered target signal. With this small number of excitation sequences a full complexity search is made. Due to the reduced number of excitation sequences involved in the final selection the required computational complexity is reduced.

Abstract: A method of forming an aggregation of N>1 band-limited time signals, each with a bandwidth of ≦B, which are present as analog and/or digital sampling values, with a respective sampling frequency of fA>2B, is characterized in that the sampling values of all N time signals are offset in time and superimposed on each other, and are jointly input to a low-pass filter (12) with a bandwidth of B′>B, and that a composite signal is tapped off from the output of the low-pass filter (12). This allows the aggregation to be performed in a considerably shorter calculation time, a number of slow and expensive aggregation elements can possibly be saved, and the damping of the signals during processing can be minimized, as well as the corresponding loss of information.

Abstract: A system for digitizing voiceband signals at the remote terminal (20) of a Digital Subscriber Line (DSL) connection and embedding the digitized voiceband component into an active DSL data stream using a DSL modem (24). Voiceband transmissions between the remote terminal (20) and the central office call switching equipment (1) occur in the analog domain when the DSL modem (28) is OFF and in the digital domain when the DSL modem (28) is ON with the digital voiceband signals transmitted over a DSL link. Preferably, the remote terminal (20) can drive a real analog telephone (30) by providing battery feed, ring-trip detection, off-hook detection and ringing generation (60) In-house 4-wire lines pairs (21, 23) are configured between the modem, telephones and computer or home network to permit all digital transmission from the subscriber to the central office.

Abstract: A communication system where the data rate of a given transmission has been encoded by a transmitter and is then used to adjust a plurality of convolutional decoders sharing common memory. The system uses common processing resources to provide up to four discrete channels having multi-rate convolutional error correction decoding resulting in a reduced silicon area and low power operation. The system is capable of supporting data communication at 8 kbps up to 64 kbps for high rate ISDN communication in receivers of both base station and consumer unit locations.

Abstract: A host signal processor (HSP) modem has a software interface between HSP modem hardware and native audio hardware in a host computer. No hard wire connections between modem hardware and audio hardware are required for synchronization. Instead, a software clock recovery system matches a transfer rate of the HSP modem hardware and a transfer rate of the audio hardware by duplicating or deleting samples. The software interface allows the native audio hardware to make audible the handshaking sequence during modem connections which eliminates the need for a speaker and speaker drivers in the modem hardware. The combination of HSP modem hardware, audio hardware, and software executed by the host computer also allows the HSP modem to perform voice communication such as telephone or speakerphone functions.

Abstract: A net sample is added or removed from an audio sample stream by fading in or out fractional samples over many sample periods. A sample-rate converter has a FIFO that is written with an input sample by an input clock synchronized to the input audio stream. The samples are read from the FIFO by a derived clock. The derived clock is generated from an output clock using a nominal ratio of Q/P. Read and write counters for the FIFO are compared. When the write counter is ahead of the read counter by exactly a target amount the derived clock is a ratio of Q/P of the output clock. When the write counter is ahead of the read counter by more than the target, the read rate is increased by removing one net sample over many sample periods. When the write counter is ahead of the read counter by less than the target amount, the read rate is decreased by adding one net sample over many sample periods.

Abstract: A serial communication system for two IC devices has a separate master chip connected to both of the IC devices, the master chip having a clock generator and circuitry for affecting serial data transmission and control between the master chip and the devices. There is a slave component on each IC device for transforming data between parallel and serial data formats and for sending and receiving a serial data stream. The master chip provides a clock signal to both slave components for gating serial data communication, and manages all communication between the two slave components. In a preferred embodiment all circuitry in the slave components is digital circuitry, and all analog circuitry is implemented on the master chip. Also in a preferred embodiment each slave periodically checks phase between data stream and clock stream received, and inserts a correction code in the data stream sent back to the master chip, so the master chip can regularly correct the phase for clock and data sent to each slave.

Abstract: An apparatus for detecting errors in an asynchronous data receiver and transmitter include a first sample block for sampling a received serial data bit, a first storing part for storing a first value of the serial data bit sampled by the first sample block for a predetermined time, a second sample block for sampling the received serial data bit, a second storing part for storing a second value of the serial data bit sampled by the second sample block for a predetermined time, and a comparing part for receiving and comparing the first value and the second value of the serial data bit stored in the first and second storing parts and outputting an error signal if the first value and the second value are not identical.

Abstract: A semiconductor integrated circuit device capable of carrying out reliable reset operation is provided. This semiconductor integrated circuit device comprises a first circuit which is reset on the basis of reset signal SR and serves to generate clock signal fi, a delay circuit adapted to receive the reset signal to output a delayed reset signal SDR, and a second circuit including a flip-flop operative in synchronism with the generated clock signal fi and serving to take thereinto the delayed reset signal SDR in synchronism with the generated clock signal fi.

Abstract: A mobile wireless terminal comprises an RF receiving means for receiving a transmission radio wave received from a base station on a designated channel, a waveform equalizer for equalizing waveform distortion of a signal received by said RF receiving means, a unique word detector for detecting a unique word from a reception signal sequence whose waveform distortion has been equalized by said waveform equalizer, a channel switching controlling means for switching the current reception channel of said RF receiving means to another reception channel corresponding to a channel switch request, a carrier detector for detecting whether or not a transmission radio wave has been received by said RF receiving means and supplying a channel switch request to said channel switching controlling means when the transmission radio wave has not been received for a predetermined time period, and a sliding controlling means for performing an on/off control for the power of said waveform equalizer at predetermined intervals for a

Abstract: A radio receiver receives a 4-FSK signal through a radio system and a detector detects a four-level detected signal from the 4-FSK signal. The four-level detected signal is converted into digital form by an AD converter. The digital signal is stored onto a memory. The AD conversion is performed at intervals obtained from the four-level detected signal. A CPU performs the data processing of the received digital data when the AD conversion is not performed and does not perform it when the AD conversion is performed.

Abstract: A communication system having a transmitter chaotic signal generator and a receiver chaotic signal generator which when uncoupled generate state signals along substantially identical chaotic attractor trajectories in an out of phase relation. A controller controls the transmitter chaotic signal generator to transmit a state signal having segments of the deterministic state trajectory which identify a subsequent length of the deterministic state trajectory matching an input N-bit sequence. A receiver coupler receives the transmitted state signal and, if the signal is above a threshold for a duration of approximately two bit periods, synchronizes the receiver chaotic signal generator to the segment of its deterministic state trajectory indicated by the state signal to generate, with or without coupling, the subsequent length of that state trajectory matching the input N-bit sequence. A receiver symbol detector reconstructs the N-bit sequence based on the receiver chaotic oscillator state signal.

Abstract: A constant phase crossbar switch system which avoids phase discontinuities at the outputs of the crossbar switch. The crossbar switch system includes input logic, a crossbar switch, output logic and a phase locked loop. The phase locked loop is used to generate a high speed internal clock from a system clock. High speed serial data streams transmitted at the internal clock frequency are received from corresponding transmitters and are coupled to the input logic. The input logic generates multiple versions of each serial data stream, one of the versions being undelayed and the other versions delayed by some fraction of a bit time. State machines are employed to selects the version of the serial data stream which results in the data stream data window being generally centered with respect to the high speed internal clock. The selected version of the data stream is employed as the active input to the crossbar switch.

Abstract: A device for communicating with a portable data medium using at least a power signal (AL) supplied by an electric energy source (4), a control signal (SC1) and a data transmission signal (I/O), comprises an interrupter (5) for interrupting the power signal (AL) to the medium from the source if the portable data medium does not cooperate with the device (1), means (8) for storing electric energy received from the source and for supplying the power signal to the medium when the source does not supply power and a data processor (3) arranged to ensure transmission of the power, control and data transmission signals (AL, SC1, I/O) to the medium according to a predetermined sequencing, as well as for detecting the interruption of the power signal (AL) from the source, then for triggering the interruption of the control and data transmission signals (SC1, I/O) according to the predetermined sequencing during the supply of the power signal from the energy storage mean.

Abstract: In response to the inputting of an asynchronous signal (DATA) which is not synchronized with a clock signal, the inputting of the clock signal to the inside of the device is controlled to an on-state. Further, in response to the termination of the operation of the device, the inputting of the clock signal to the inside of the device is controlled to an off-state. In this case, the level change of the asynchronous signal is detected by a comparator, and based on the detection result, the inputting of the clock signal is controlled to either the on-state or the off-state by a clock control circuit. By stopping the inputting of the clock signal, the power consumption of the device can be reduced.

Abstract: A data processing apparatus includes a first circuit unit operating with first clocks of a predetermined cycle, a second circuit unit operating with second clocks of a predetermined cycle different from the first clock cycle, and a first circuit block which generates and outputs a train of pulses in accordance with the first clock cycle.

Abstract: A data stream (DS) comprises a time multiplex of coded data (D) and control data (C). The data stream (DS) may be, for example, of the MPEG type representing a sequence of pictures. The coded data (D) is transcoded (T) so as to obtain transcoded data (DT) which differs in size from the coded data (D). The control data (C) is adapted for the transcoded data (DT) so as to obtain adapted control data (CA) which does not substantially differ in size from the control data (C). The transcoded data (DT) and the adapted control data (CA) are written into a transcoder output buffer (TOB) and read from the transcoder output buffer (TOB) so as to obtain a transcoded data stream (DST). This allows an efficient use of a transmission channel via which the transcoded data stream (DST) is to be transmitted and, consequently, it allows a satisfactory transcoding quality.

Abstract: A data communication device includes a controller and a baud rate generator, which is initially set to receive a data stream at the highest baudrate. In response to a start bit in the data stream, the controller suspends the operation of the baud rate generator and determines the proper baudrate by polling for the presence or absence of the start bit. During the suspended period, the baud rate generator is set to the actual incoming baudrate. The baud rate generator is then turned on, and the rest of the characters are then received at the actual baudrate. The device utilizes the execution times of background processing instructions to serve as the polling times. As such, loss of data bits are prevented since all baudrate determinations are completed during the receipt of the start bit.

Abstract: The present invention relates to a method for setup of a signal in multicarrier modulation, including clipping the signal, in amplitude, with respect to a threshold value, and of reinjecting, with a delay and on the signal to be set up, a clipping noise redistributed, at least partly, outside the useful slip of the signal in multicarrier modulation.

Abstract: A method and apparatus is presented where for transmitting data between two or more components. Data signals are sent in parallel with a clocking signal (e.g., on a bus) so that the data signal can be latched in relation to the clocking signal. For example, two clocking signals, out of phase from each other by 180 degrees, can be sent on bidirectional clocking signal lines and data signals can be sent on a data signal line, the component receiving the clocking and data signals can latch the data signals on each high-to-low transition of either of the two clocking signals. Using the method and apparatus of the present invention, skew problems seen with other bus systems can be reduced which leads to an increase in data transfer rates.

Abstract: A multiple access communications data and information transport system and methodology for employing the noise present in any conduit as a carrier form using wireless chaotic waveform signals supported by nonlinear noise sustaining structures. The communications system utilizes digital devices and software embodying various algorithms designed to manipulate the nonlinear perturbations of any given conduit to establish a high bandwidth bidirectional, isochronous noise immune communications signal. Additionally, the system can be combined with any of a number of wireless or wireline communication methodologies to further enhance performance in terms of bandwidth, throughput, noise immunity, power consumption, cell size, and number of users without disturbing any concurrent signal traffic.

Abstract: A novel and improved method for implementing a high-transmission-rate over-the-air interface is described. A transmit system provides an in-phase channel set and a quadrature-phase channel set. The in-phase channel set is used to provide a complete set of orthogonal medium rate control and traffic channels. The quadrature-phase channel set is used to provide a high-rate supplemental channel and an extended set of medium rate channels that are orthogonal to each other and the original medium rate channels. The high-rate supplemental channel is generated over a set of medium rate channels using a short channel code. The medium rate channel are generated using a set of long channel codes.

Abstract: An autobaud method for automatic detection of baud rate and character configuration of a received asynchronous serial data stream by detecting a first predetermined two character sequence in uppercase and lowercase form, notably "AT" and "at", from patterns of signal states and their durations, also provides for detecting a second predetermined two character sequence of "A/" and "a/" and for substantially immediate automatic echoing of the first and second predetermined character sequences if autoechoing is enabled. The baud rate and character configuration used for subsequent characters is not be changed unless, after the autobaud function is enabled, the first predetermined two character sequence in either uppercase or lowercase form is received, and a different baud rate and/or character configuration is determined from the received pattern of signal states and their durations.

Abstract: A calibration circuit adjusts a differential output voltage from a line driver circuit when the differential output voltage falls outside a specified tolerance range. The calibration circuit includes a sample and hold circuit which samples the differential output voltage and holds a representative signal. A comparator compares the held signal with a reference voltage signal. When the held signal is greater than the reference voltage signal the comparator outputs a LOW signal and when the held signal is less than the reference voltage signal the comparator outputs a HIGH signal. The comparator output signal is stored in a memory circuit of a control logic. The control logic instructs an up/down counter to increment when the comparator output is LOW and to decrement when the comparator output is HIGH. A calibration current source sinks a unit of calibration current when the comparator output is LOW and sources a unit of calibration current when the comparator output is HIGH.

Abstract: A pulse modulation operation circuit includes a current bus, a plurality of switch current sources connected parallel to each other and commonly connected to the current bus for generating current pulses corresponding to external input signals, charge conversion element connected to the current bus for integrating the current pulses and converting them into a charge, and an output for converting the charge into a binary digital signal and outputting the binary digital signal. Each pulse width modulation signal is input to a corresponding one of the switch current sources, which in turn generates a constant current for a period corresponding to the width of each pulse of the signal, to convert each signal pulse into a current pulse. The thus-obtained current pulses are added on the common current bus, thereby obtaining, by capacitive integration, a total charge Q.sub.total proportional to the sum of the widths of the current pulses.

Abstract: A computer system with a semi-differential bus-signaling scheme is described. The computer system includes a transmitter coupled to a common bus. The transmitter sends clock signals and a data signal to logic-comparing devices within a receiver. The logic-comparing devices compare the data signal to a reference voltage while comparing the clock signals to each other. After the comparison, the clock signals can be used to capture the data into a retiming circuit.

Abstract: An adaptive arrangement and method for the coded digital transmission of images includes an adaptive transmitter (101) having an image coder (109) which is operable at multiple image coding rates, a channel coder (111) which is operable at a plurality of channel coding rates, and is further operable to provide a plurality of power outputs, baud rates, and a plurality of image delivery rates. The transmitter (101) further includes a channel status monitor (115) which monitors the communication channel (105) connecting the transmitter (101) to a receiver (103). The channel status monitor (115) responds to changes in the quality of the communications channel by varying one or more of the image coding rate, the channel coding rate, the power, the baud rate, and the image delivery rate.

Abstract: When a frame information (F1)C2 defining the frame type in a transmission protocol format is received in a pager, data of a following interleaving portion is received. A receiving buffer circuit converts the received data from serial data into parallel data in accordance with the frame type, and a deinterleaving circuit reproduces (deinterleaves) the converted parallel data.

Abstract: A code division multiple access (CDMA) is a type of spread-spectrum communication system having a plurality of subscriber units and at least one base station. In order for a first subscriber unit to communicate with a second subscriber unit, a transmitter unit of the first subscriber unit imprints a unique code upon transmission and the second subscriber unit includes a receiver, which uses the code to decode the transmission. In addition, each transmitter with a CDMA communication system includes a stream cipher generator for enciphering the voice and data communications. Each receiver within a CDMA communication system contains an identical or similar stream cipher generator, which is used to decipher the received enciphered communication. The present invention relates to a stream cipher generator having a plurality of linear feedback shift registers to produce a stream cipher for increasing security using ciphered messages.

Abstract: A system of distributing video and/or audio information employs digital signal processing to achieve high rates of data compression. The compressed and encoded audio and/or video information is sent over standard telephone, cable or satellite broadcast channels to a receiver specified by a subscriber of the service, preferably in less than real time, for later playback and optional recording on standard audio and/or video tape.

Abstract: A method and a system for acquiring data frame timing in a discrete multitone modem system in which an acquisition frame is generated having a first predetermined number of impulse signals. Each impulse signal is spaced in time by 2(P+1)T.sub.s, such that 1/T.sub.s is a sample transmission rate, and P is a time length in samples of a cyclic prefix that is added to a data frame. The cyclic prefix length P is chosen such that a channel impulse response seen at a receiver effectively spans no more than P+1 samples when a received signal is sampled at the 1/T.sub.s rate. Data frames are generated subsequent to the acquisition frame. Each data frame includes a cyclic prefix and at least as many data samples as samples of the cyclic prefix. The acquisition and data frames are converted to an analog signal for transmission. The received acquisition frame is sampled and a summation window is advanced one sample at a time through the received acquisition frame.

Abstract: A peak detector for a maximum likelihood decoding system, using an automatic threshold control (ACT), and a method therefor are provided. In the peak detector, positive and negative peak values are detected from an input signal having digital information, based on positive and negative threshold values, and then each threshold value is evaluated according to positive and negative values of the input signal, to reset each threshold value to a predetermined value based on the detected peak value having the opposite polarity thereto. Accordingly, data can be detected exactly, improving performance of Viterbi decoding.

Abstract: An audio encoding transmission system is provided for a transmitting station which performs data transmission with respect to a receiving station through a network. The transmitting station contains a scalable encoder which performs an encoding process on audio signals input thereto in response to bit rate information representing a bit rate which is variable in response to a condition of the network. Results of the encoding process are partitioned into outline data, having a low bit rate, and detail data. Herein, the outline data correspond to low-frequency components of the audio signals while the detail data correspond to high-frequency components of the audio signals, for example. A bit stream is constructed using the outline data and detail data as well as additional information such as a header and a boundary identifier which are created on the basis of the audio signals and bit rate information. Thus, the transmitting station transmits the bit stream to the receiving station via the network.

Abstract: An apparatus and method employs a First In, First Out (FIFO) buffer to separate a first logic block operating at a first rate, such as 33.75 MHz, from a second logic block operating at a second rate, such as 27 MHz, which is lower than the first rate. The dual port FIFO operates with asynchronous Read and Write ports, and the Write port controls the input of data from the first logic block at the first rate to the FIFO. The FIFO provides a value indicating that the FIFO is full. Enablement of the Read port is based upon the presence of data in the FIFO and a synchronization signal for the data. Once enabled, the data is transferred from the FIFO to the second logic block at the second rate. A flag value of the FIFO is set when the FIFO buffer is full, and is used by the first logic block to interrupt data transfer into the FIFO at the first rate to allow data provided at the FIFO output at the second rate to empty the FIFO buffer.

Abstract: A device for identifying a determined repetitive sequence of predetermined signals arriving on a modem. The device includes a delay circuit so that all the words of a sequence are simultaneously present; a combination circuit for providing a combined word; a circuit for calculating the modulus of each combined word and for comparing this modulus with a threshold; a circuit for counting clock pulses corresponding to the rate at which words arrive; a circuit for inhibiting the counting circuit when the modulus of the combined word is lower than the threshold; and a circuit for providing an identification signal when a predetermined number of clock signals is counted.

Abstract: A transmitter unit generates a carrier signal in the form of a periodic bipolar signal. The carrier signal has intrapulse periods between two pulses of different polarity. A transmission antenna is operated with the bipolar signal. To prevent the harmonic oscillations of the transmitted signals from having excessively great amplitudes, the intrapulse period is defined such that the amplitude of the first harmonic of the transmitted oscillation, ascertained by Fourier analysis, is greater than 90% and the amplitude of the third harmonic oscillation is less than 25%, in comparison with the amplitude of the fundamental oscillation of a rectangular oscillation without intrapulse periods.

Abstract: A method and apparatus for providing multi-channel telephony multimedia services. A multi-tasking DSP processes a plurality of multimedia services for a plurality of telephone channels. The DSP operates in conjunction with a host processor. The host processor indicates to the DSP, in real-time, the services required for a channel. The DSP in response allocates a portion of its fast memory in which a program is stored comprising the multimedia services routines required for the channel. The multimedia services program stored in the portion of fast memory allocated to a channel is then utilized to process the incoming channel signal data. The processed signal data is then output to memory shared between the DSP and the host processor. The portion of memory and the program for each channel can be dynamically reconfigured in real-time on a per channel basis.